drivers/pci/host/pci-keystone-dw.c

   1 /*
   2  * Designware application register space functions for Keystone PCI controller
   3  *
   4  * Copyright (C) 2013-2014 Texas Instruments., Ltd.
   5  *              http://www.ti.com
   6  *
   7  * Author: Murali Karicheri <m-karicheri2@ti.com>
   8  *
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/irq.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_pci.h>
  20 #include <linux/pci.h>
  21 #include <linux/platform_device.h>
  22
  23 #include "pcie-designware.h"
  24 #include "pci-keystone.h"
  25
  26 /* Application register defines */
  27 #define LTSSM_EN_VAL                    1
  28 #define LTSSM_STATE_MASK                0x1f
  29 #define LTSSM_STATE_L0                  0x11
  30 #define DBI_CS2_EN_VAL                  0x20
  31 #define OB_XLAT_EN_VAL                  2
  32
  33 /* Application registers */
  34 #define CMD_STATUS                      0x004
  35 #define CFG_SETUP                       0x008
  36 #define OB_SIZE                         0x030
  37 #define CFG_PCIM_WIN_SZ_IDX             3
  38 #define CFG_PCIM_WIN_CNT                32
  39 #define SPACE0_REMOTE_CFG_OFFSET        0x1000
  40 #define OB_OFFSET_INDEX(n)              (0x200 + (8 * n))
  41 #define OB_OFFSET_HI(n)                 (0x204 + (8 * n))
  42
  43 /* IRQ register defines */
  44 #define IRQ_EOI                         0x050
  45 #define IRQ_STATUS                      0x184
  46 #define IRQ_ENABLE_SET                  0x188
  47 #define IRQ_ENABLE_CLR                  0x18c
  48
  49 #define MSI_IRQ                         0x054
  50 #define MSI0_IRQ_STATUS                 0x104
  51 #define MSI0_IRQ_ENABLE_SET             0x108
  52 #define MSI0_IRQ_ENABLE_CLR             0x10c
  53 #define IRQ_STATUS                      0x184
  54 #define MSI_IRQ_OFFSET                  4
  55
  56 /* Config space registers */
  57 #define DEBUG0                          0x728
  58
  59 #define to_keystone_pcie(x)     container_of(x, struct keystone_pcie, pp)
  60
  61 static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
  62 {
  63         return sys->private_data;
  64 }
  65
  66 static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
  67                                              u32 *bit_pos)
  68 {
  69         *reg_offset = offset % 8;
  70         *bit_pos = offset >> 3;
  71 }
  72
  73 phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
  74 {
  75         struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
  76
  77         return ks_pcie->app.start + MSI_IRQ;
  78 }
  79
  80 void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
  81 {
  82         struct pcie_port *pp = &ks_pcie->pp;
  83         u32 pending, vector;
  84         int src, virq;
  85
  86         pending = readl(ks_pcie->va_app_base + MSI0_IRQ_STATUS + (offset << 4));
  87
  88         /*
  89          * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
  90          * shows 1, 9, 17, 25 and so forth
  91          */
  92         for (src = 0; src < 4; src++) {
  93                 if (BIT(src) & pending) {
  94                         vector = offset + (src << 3);
  95                         virq = irq_linear_revmap(pp->irq_domain, vector);
  96                         dev_dbg(pp->dev, "irq: bit %d, vector %d, virq %d\n",
  97                                 src, vector, virq);
  98                         generic_handle_irq(virq);
  99                 }
 100         }
 101 }
 102
 103 static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
 104 {
 105         u32 offset, reg_offset, bit_pos;
 106         struct keystone_pcie *ks_pcie;
 107         struct msi_desc *msi;
 108         struct pcie_port *pp;
 109
 110         msi = irq_data_get_msi_desc(d);
 111         pp = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
 112         ks_pcie = to_keystone_pcie(pp);
 113         offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
 114         update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos);
 115
 116         writel(BIT(bit_pos),
 117                ks_pcie->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
 118         writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI);
 119 }
 120
 121 void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
 122 {
 123         u32 reg_offset, bit_pos;
 124         struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
 125
 126         update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
 127         writel(BIT(bit_pos),
 128                ks_pcie->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
 129 }
 130
 131 void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
 132 {
 133         u32 reg_offset, bit_pos;
 134         struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
 135
 136         update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
 137         writel(BIT(bit_pos),
 138                ks_pcie->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
 139 }
 140
 141 static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
 142 {
 143         struct keystone_pcie *ks_pcie;
 144         struct msi_desc *msi;
 145         struct pcie_port *pp;
 146         u32 offset;
 147
 148         msi = irq_data_get_msi_desc(d);
 149         pp = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
 150         ks_pcie = to_keystone_pcie(pp);
 151         offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
 152
 153         /* Mask the end point if PVM implemented */
 154         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 155                 if (msi->msi_attrib.maskbit)
 156                         pci_msi_mask_irq(d);
 157         }
 158
 159         ks_dw_pcie_msi_clear_irq(pp, offset);
 160 }
 161
 162 static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
 163 {
 164         struct keystone_pcie *ks_pcie;
 165         struct msi_desc *msi;
 166         struct pcie_port *pp;
 167         u32 offset;
 168
 169         msi = irq_data_get_msi_desc(d);
 170         pp = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
 171         ks_pcie = to_keystone_pcie(pp);
 172         offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
 173
 174         /* Mask the end point if PVM implemented */
 175         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 176                 if (msi->msi_attrib.maskbit)
 177                         pci_msi_unmask_irq(d);
 178         }
 179
 180         ks_dw_pcie_msi_set_irq(pp, offset);
 181 }
 182
 183 static struct irq_chip ks_dw_pcie_msi_irq_chip = {
 184         .name = "Keystone-PCIe-MSI-IRQ",
 185         .irq_ack = ks_dw_pcie_msi_irq_ack,
 186         .irq_mask = ks_dw_pcie_msi_irq_mask,
 187         .irq_unmask = ks_dw_pcie_msi_irq_unmask,
 188 };
 189
 190 static int ks_dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
 191                               irq_hw_number_t hwirq)
 192 {
 193         irq_set_chip_and_handler(irq, &ks_dw_pcie_msi_irq_chip,
 194                                  handle_level_irq);
 195         irq_set_chip_data(irq, domain->host_data);
 196
 197         return 0;
 198 }
 199
 200 static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
 201         .map = ks_dw_pcie_msi_map,
 202 };
 203
 204 int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
 205 {
 206         struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
 207         int i;
 208
 209         pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
 210                                         MAX_MSI_IRQS,
 211                                         &ks_dw_pcie_msi_domain_ops,
 212                                         chip);
 213         if (!pp->irq_domain) {
 214                 dev_err(pp->dev, "irq domain init failed\n");
 215                 return -ENXIO;
 216         }
 217
 218         for (i = 0; i < MAX_MSI_IRQS; i++)
 219                 irq_create_mapping(pp->irq_domain, i);
 220
 221         return 0;
 222 }
 223
 224 void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
 225 {
 226         int i;
 227
 228         for (i = 0; i < MAX_LEGACY_IRQS; i++)
 229                 writel(0x1, ks_pcie->va_app_base + IRQ_ENABLE_SET + (i << 4));
 230 }
 231
 232 void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
 233 {
 234         struct pcie_port *pp = &ks_pcie->pp;
 235         u32 pending;
 236         int virq;
 237
 238         pending = readl(ks_pcie->va_app_base + IRQ_STATUS + (offset << 4));
 239
 240         if (BIT(0) & pending) {
 241                 virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
 242                 dev_dbg(pp->dev, ": irq: irq_offset %d, virq %d\n", offset,
 243                         virq);
 244                 generic_handle_irq(virq);
 245         }
 246
 247         /* EOI the INTx interrupt */
 248         writel(offset, ks_pcie->va_app_base + IRQ_EOI);
 249 }
 250
 251 static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d)
 252 {
 253 }
 254
 255 static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d)
 256 {
 257 }
 258
 259 static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d)
 260 {
 261 }
 262
 263 static struct irq_chip ks_dw_pcie_legacy_irq_chip = {
 264         .name = "Keystone-PCI-Legacy-IRQ",
 265         .irq_ack = ks_dw_pcie_ack_legacy_irq,
 266         .irq_mask = ks_dw_pcie_mask_legacy_irq,
 267         .irq_unmask = ks_dw_pcie_unmask_legacy_irq,
 268 };
 269
 270 static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d,
 271                                 unsigned int irq, irq_hw_number_t hw_irq)
 272 {
 273         irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip,
 274                                  handle_level_irq);
 275         irq_set_chip_data(irq, d->host_data);
 276
 277         return 0;
 278 }
 279
 280 static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = {
 281         .map = ks_dw_pcie_init_legacy_irq_map,
 282         .xlate = irq_domain_xlate_onetwocell,
 283 };
 284
 285 /**
 286  * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
 287  * registers
 288  *
 289  * Since modification of dbi_cs2 involves different clock domain, read the
 290  * status back to ensure the transition is complete.
 291  */
 292 static void ks_dw_pcie_set_dbi_mode(void __iomem *reg_virt)
 293 {
 294         u32 val;
 295
 296         writel(DBI_CS2_EN_VAL | readl(reg_virt + CMD_STATUS),
 297                reg_virt + CMD_STATUS);
 298
 299         do {
 300                 val = readl(reg_virt + CMD_STATUS);
 301         } while (!(val & DBI_CS2_EN_VAL));
 302 }
 303
 304 /**
 305  * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode
 306  *
 307  * Since modification of dbi_cs2 involves different clock domain, read the
 308  * status back to ensure the transition is complete.
 309  */
 310 static void ks_dw_pcie_clear_dbi_mode(void __iomem *reg_virt)
 311 {
 312         u32 val;
 313
 314         writel(~DBI_CS2_EN_VAL & readl(reg_virt + CMD_STATUS),
 315                      reg_virt + CMD_STATUS);
 316
 317         do {
 318                 val = readl(reg_virt + CMD_STATUS);
 319         } while (val & DBI_CS2_EN_VAL);
 320 }
 321
 322 void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
 323 {
 324         struct pcie_port *pp = &ks_pcie->pp;
 325         u32 start = pp->mem->start, end = pp->mem->end;
 326         int i, tr_size;
 327
 328         /* Disable BARs for inbound access */
 329         ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
 330         writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0);
 331         writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1);
 332         ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
 333
 334         /* Set outbound translation size per window division */
 335         writel(CFG_PCIM_WIN_SZ_IDX & 0x7, ks_pcie->va_app_base + OB_SIZE);
 336
 337         tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
 338
 339         /* Using Direct 1:1 mapping of RC <-> PCI memory space */
 340         for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
 341                 writel(start | 1, ks_pcie->va_app_base + OB_OFFSET_INDEX(i));
 342                 writel(0, ks_pcie->va_app_base + OB_OFFSET_HI(i));
 343                 start += tr_size;
 344         }
 345
 346         /* Enable OB translation */
 347         writel(OB_XLAT_EN_VAL | readl(ks_pcie->va_app_base + CMD_STATUS),
 348                ks_pcie->va_app_base + CMD_STATUS);
 349 }
 350
 351 /**
 352  * ks_pcie_cfg_setup() - Set up configuration space address for a device
 353  *
 354  * @ks_pcie: ptr to keystone_pcie structure
 355  * @bus: Bus number the device is residing on
 356  * @devfn: device, function number info
 357  *
 358  * Forms and returns the address of configuration space mapped in PCIESS
 359  * address space 0.  Also configures CFG_SETUP for remote configuration space
 360  * access.
 361  *
 362  * The address space has two regions to access configuration - local and remote.
 363  * We access local region for bus 0 (as RC is attached on bus 0) and remote
 364  * region for others with TYPE 1 access when bus > 1.  As for device on bus = 1,
 365  * we will do TYPE 0 access as it will be on our secondary bus (logical).
 366  * CFG_SETUP is needed only for remote configuration access.
 367  */
 368 static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
 369                                        unsigned int devfn)
 370 {
 371         u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
 372         struct pcie_port *pp = &ks_pcie->pp;
 373         u32 regval;
 374
 375         if (bus == 0)
 376                 return pp->dbi_base;
 377
 378         regval = (bus << 16) | (device << 8) | function;
 379
 380         /*
 381          * Since Bus#1 will be a virtual bus, we need to have TYPE0
 382          * access only.
 383          * TYPE 1
 384          */
 385         if (bus != 1)
 386                 regval |= BIT(24);
 387
 388         writel(regval, ks_pcie->va_app_base + CFG_SETUP);
 389         return pp->va_cfg0_base;
 390 }
 391
 392 int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 393                              unsigned int devfn, int where, int size, u32 *val)
 394 {
 395         struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
 396         u8 bus_num = bus->number;
 397         void __iomem *addr;
 398
 399         addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
 400
 401         return dw_pcie_cfg_read(addr + where, size, val);
 402 }
 403
 404 int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 405                              unsigned int devfn, int where, int size, u32 val)
 406 {
 407         struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
 408         u8 bus_num = bus->number;
 409         void __iomem *addr;
 410
 411         addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
 412
 413         return dw_pcie_cfg_write(addr + where, size, val);
 414 }
 415
 416 /**
 417  * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
 418  *
 419  * This sets BAR0 to enable inbound access for MSI_IRQ register
 420  */
 421 void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
 422 {
 423         struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
 424
 425         /* Configure and set up BAR0 */
 426         ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
 427
 428         /* Enable BAR0 */
 429         writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0);
 430         writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0);
 431
 432         ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
 433
 434          /*
 435           * For BAR0, just setting bus address for inbound writes (MSI) should
 436           * be sufficient.  Use physical address to avoid any conflicts.
 437           */
 438         writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0);
 439 }
 440
 441 /**
 442  * ks_dw_pcie_link_up() - Check if link up
 443  */
 444 int ks_dw_pcie_link_up(struct pcie_port *pp)
 445 {
 446         u32 val = readl(pp->dbi_base + DEBUG0);
 447
 448         return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
 449 }
 450
 451 void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
 452 {
 453         u32 val;
 454
 455         /* Disable Link training */
 456         val = readl(ks_pcie->va_app_base + CMD_STATUS);
 457         val &= ~LTSSM_EN_VAL;
 458         writel(LTSSM_EN_VAL | val,  ks_pcie->va_app_base + CMD_STATUS);
 459
 460         /* Initiate Link Training */
 461         val = readl(ks_pcie->va_app_base + CMD_STATUS);
 462         writel(LTSSM_EN_VAL | val,  ks_pcie->va_app_base + CMD_STATUS);
 463 }
 464
 465 /**
 466  * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware
 467  *
 468  * Ioremap the register resources, initialize legacy irq domain
 469  * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
 470  * PCI host controller.
 471  */
 472 int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
 473                                 struct device_node *msi_intc_np)
 474 {
 475         struct pcie_port *pp = &ks_pcie->pp;
 476         struct platform_device *pdev = to_platform_device(pp->dev);
 477         struct resource *res;
 478
 479         /* Index 0 is the config reg. space address */
 480         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 481         pp->dbi_base = devm_ioremap_resource(pp->dev, res);
 482         if (IS_ERR(pp->dbi_base))
 483                 return PTR_ERR(pp->dbi_base);
 484
 485         /*
 486          * We set these same and is used in pcie rd/wr_other_conf
 487          * functions
 488          */
 489         pp->va_cfg0_base = pp->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
 490         pp->va_cfg1_base = pp->va_cfg0_base;
 491
 492         /* Index 1 is the application reg. space address */
 493         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 494         ks_pcie->va_app_base = devm_ioremap_resource(pp->dev, res);
 495         if (IS_ERR(ks_pcie->va_app_base))
 496                 return PTR_ERR(ks_pcie->va_app_base);
 497
 498         ks_pcie->app = *res;
 499
 500         /* Create legacy IRQ domain */
 501         ks_pcie->legacy_irq_domain =
 502                         irq_domain_add_linear(ks_pcie->legacy_intc_np,
 503                                         MAX_LEGACY_IRQS,
 504                                         &ks_dw_pcie_legacy_irq_domain_ops,
 505                                         NULL);
 506         if (!ks_pcie->legacy_irq_domain) {
 507                 dev_err(pp->dev, "Failed to add irq domain for legacy irqs\n");
 508                 return -EINVAL;
 509         }
 510
 511         return dw_pcie_host_init(pp);
 512 }