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intel-gtt: maximize ggtt size on platforms that support this
[linux/fpc-iii.git] / drivers / char / agp / intel-gtt.c
blob5dc1f5db55a79fe3143561b2e21f0884151d0018
1 /*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <asm/smp.h>
25 #include "agp.h"
26 #include "intel-agp.h"
27 #include <linux/intel-gtt.h>
28 #include <drm/intel-gtt.h>
29
30 /*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_DMAR).
34 * Only newer chipsets need to bother with this, of course.
35 */
36 #ifdef CONFIG_DMAR
37 #define USE_PCI_DMA_API 1
38 #else
39 #define USE_PCI_DMA_API 0
40 #endif
41
42 /* Max amount of stolen space, anything above will be returned to Linux */
43 int intel_max_stolen = 32 * 1024 * 1024;
44
45 static const struct aper_size_info_fixed intel_i810_sizes[] =
46 {
47 {64, 16384, 4},
48 /* The 32M mode still requires a 64k gatt */
49 {32, 8192, 4}
50 };
51
52 #define AGP_DCACHE_MEMORY 1
53 #define AGP_PHYS_MEMORY 2
54 #define INTEL_AGP_CACHED_MEMORY 3
55
56 static struct gatt_mask intel_i810_masks[] =
57 {
58 {.mask = I810_PTE_VALID, .type = 0},
59 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
60 {.mask = I810_PTE_VALID, .type = 0},
61 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
62 .type = INTEL_AGP_CACHED_MEMORY}
63 };
64
65 #define INTEL_AGP_UNCACHED_MEMORY 0
66 #define INTEL_AGP_CACHED_MEMORY_LLC 1
67 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
68 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
69 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
70
71 struct intel_gtt_driver {
72 unsigned int gen : 8;
73 unsigned int is_g33 : 1;
74 unsigned int is_pineview : 1;
75 unsigned int is_ironlake : 1;
76 unsigned int dma_mask_size : 8;
77 /* Chipset specific GTT setup */
78 int (*setup)(void);
79 /* This should undo anything done in ->setup() save the unmapping
80 * of the mmio register file, that's done in the generic code. */
81 void (*cleanup)(void);
82 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
83 /* Flags is a more or less chipset specific opaque value.
84 * For chipsets that need to support old ums (non-gem) code, this
85 * needs to be identical to the various supported agp memory types! */
86 bool (*check_flags)(unsigned int flags);
87 void (*chipset_flush)(void);
88 };
89
90 static struct _intel_private {
91 struct intel_gtt base;
92 const struct intel_gtt_driver *driver;
93 struct pci_dev *pcidev; /* device one */
94 struct pci_dev *bridge_dev;
95 u8 __iomem *registers;
96 phys_addr_t gtt_bus_addr;
97 phys_addr_t gma_bus_addr;
98 u32 PGETBL_save;
99 u32 __iomem *gtt; /* I915G */
100 int num_dcache_entries;
101 union {
102 void __iomem *i9xx_flush_page;
103 void *i8xx_flush_page;
104 };
105 struct page *i8xx_page;
106 struct resource ifp_resource;
107 int resource_valid;
108 struct page *scratch_page;
109 dma_addr_t scratch_page_dma;
110 } intel_private;
111
112 #define INTEL_GTT_GEN intel_private.driver->gen
113 #define IS_G33 intel_private.driver->is_g33
114 #define IS_PINEVIEW intel_private.driver->is_pineview
115 #define IS_IRONLAKE intel_private.driver->is_ironlake
116
117 static void intel_agp_free_sglist(struct agp_memory *mem)
118 {
119 struct sg_table st;
120
121 st.sgl = mem->sg_list;
122 st.orig_nents = st.nents = mem->page_count;
123
124 sg_free_table(&st);
125
126 mem->sg_list = NULL;
127 mem->num_sg = 0;
128 }
129
130 static int intel_agp_map_memory(struct agp_memory *mem)
131 {
132 struct sg_table st;
133 struct scatterlist *sg;
134 int i;
135
136 if (mem->sg_list)
137 return 0; /* already mapped (for e.g. resume */
138
139 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
140
141 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
142 goto err;
143
144 mem->sg_list = sg = st.sgl;
145
146 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
147 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
148
149 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
150 mem->page_count, PCI_DMA_BIDIRECTIONAL);
151 if (unlikely(!mem->num_sg))
152 goto err;
153
154 return 0;
155
156 err:
157 sg_free_table(&st);
158 return -ENOMEM;
159 }
160
161 static void intel_agp_unmap_memory(struct agp_memory *mem)
162 {
163 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
164
165 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
166 mem->page_count, PCI_DMA_BIDIRECTIONAL);
167 intel_agp_free_sglist(mem);
168 }
169
170 static int intel_i810_fetch_size(void)
171 {
172 u32 smram_miscc;
173 struct aper_size_info_fixed *values;
174
175 pci_read_config_dword(intel_private.bridge_dev,
176 I810_SMRAM_MISCC, &smram_miscc);
177 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
178
179 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
180 dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
181 return 0;
182 }
183 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
184 agp_bridge->current_size = (void *) (values + 1);
185 agp_bridge->aperture_size_idx = 1;
186 return values[1].size;
187 } else {
188 agp_bridge->current_size = (void *) (values);
189 agp_bridge->aperture_size_idx = 0;
190 return values[0].size;
191 }
192
193 return 0;
194 }
195
196 static int intel_i810_configure(void)
197 {
198 struct aper_size_info_fixed *current_size;
199 u32 temp;
200 int i;
201
202 current_size = A_SIZE_FIX(agp_bridge->current_size);
203
204 if (!intel_private.registers) {
205 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
206 temp &= 0xfff80000;
207
208 intel_private.registers = ioremap(temp, 128 * 4096);
209 if (!intel_private.registers) {
210 dev_err(&intel_private.pcidev->dev,
211 "can't remap memory\n");
212 return -ENOMEM;
213 }
214 }
215
216 if ((readl(intel_private.registers+I810_DRAM_CTL)
217 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
218 /* This will need to be dynamically assigned */
219 dev_info(&intel_private.pcidev->dev,
220 "detected 4MB dedicated video ram\n");
221 intel_private.num_dcache_entries = 1024;
222 }
223 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
224 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
225 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
226 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
227
228 if (agp_bridge->driver->needs_scratch_page) {
229 for (i = 0; i < current_size->num_entries; i++) {
230 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
231 }
232 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
233 }
234 global_cache_flush();
235 return 0;
236 }
237
238 static void intel_i810_cleanup(void)
239 {
240 writel(0, intel_private.registers+I810_PGETBL_CTL);
241 readl(intel_private.registers); /* PCI Posting. */
242 iounmap(intel_private.registers);
243 }
244
245 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
246 {
247 return;
248 }
249
250 /* Exists to support ARGB cursors */
251 static struct page *i8xx_alloc_pages(void)
252 {
253 struct page *page;
254
255 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
256 if (page == NULL)
257 return NULL;
258
259 if (set_pages_uc(page, 4) < 0) {
260 set_pages_wb(page, 4);
261 __free_pages(page, 2);
262 return NULL;
263 }
264 get_page(page);
265 atomic_inc(&agp_bridge->current_memory_agp);
266 return page;
267 }
268
269 static void i8xx_destroy_pages(struct page *page)
270 {
271 if (page == NULL)
272 return;
273
274 set_pages_wb(page, 4);
275 put_page(page);
276 __free_pages(page, 2);
277 atomic_dec(&agp_bridge->current_memory_agp);
278 }
279
280 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
281 int type)
282 {
283 int i, j, num_entries;
284 void *temp;
285 int ret = -EINVAL;
286 int mask_type;
287
288 if (mem->page_count == 0)
289 goto out;
290
291 temp = agp_bridge->current_size;
292 num_entries = A_SIZE_FIX(temp)->num_entries;
293
294 if ((pg_start + mem->page_count) > num_entries)
295 goto out_err;
296
297
298 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
299 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
300 ret = -EBUSY;
301 goto out_err;
302 }
303 }
304
305 if (type != mem->type)
306 goto out_err;
307
308 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
309
310 switch (mask_type) {
311 case AGP_DCACHE_MEMORY:
312 if (!mem->is_flushed)
313 global_cache_flush();
314 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
315 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
316 intel_private.registers+I810_PTE_BASE+(i*4));
317 }
318 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
319 break;
320 case AGP_PHYS_MEMORY:
321 case AGP_NORMAL_MEMORY:
322 if (!mem->is_flushed)
323 global_cache_flush();
324 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
325 writel(agp_bridge->driver->mask_memory(agp_bridge,
326 page_to_phys(mem->pages[i]), mask_type),
327 intel_private.registers+I810_PTE_BASE+(j*4));
328 }
329 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
330 break;
331 default:
332 goto out_err;
333 }
334
335 out:
336 ret = 0;
337 out_err:
338 mem->is_flushed = true;
339 return ret;
340 }
341
342 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
343 int type)
344 {
345 int i;
346
347 if (mem->page_count == 0)
348 return 0;
349
350 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
351 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
352 }
353 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
354
355 return 0;
356 }
357
358 /*
359 * The i810/i830 requires a physical address to program its mouse
360 * pointer into hardware.
361 * However the Xserver still writes to it through the agp aperture.
362 */
363 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
364 {
365 struct agp_memory *new;
366 struct page *page;
367
368 switch (pg_count) {
369 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
370 break;
371 case 4:
372 /* kludge to get 4 physical pages for ARGB cursor */
373 page = i8xx_alloc_pages();
374 break;
375 default:
376 return NULL;
377 }
378
379 if (page == NULL)
380 return NULL;
381
382 new = agp_create_memory(pg_count);
383 if (new == NULL)
384 return NULL;
385
386 new->pages[0] = page;
387 if (pg_count == 4) {
388 /* kludge to get 4 physical pages for ARGB cursor */
389 new->pages[1] = new->pages[0] + 1;
390 new->pages[2] = new->pages[1] + 1;
391 new->pages[3] = new->pages[2] + 1;
392 }
393 new->page_count = pg_count;
394 new->num_scratch_pages = pg_count;
395 new->type = AGP_PHYS_MEMORY;
396 new->physical = page_to_phys(new->pages[0]);
397 return new;
398 }
399
400 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
401 {
402 struct agp_memory *new;
403
404 if (type == AGP_DCACHE_MEMORY) {
405 if (pg_count != intel_private.num_dcache_entries)
406 return NULL;
407
408 new = agp_create_memory(1);
409 if (new == NULL)
410 return NULL;
411
412 new->type = AGP_DCACHE_MEMORY;
413 new->page_count = pg_count;
414 new->num_scratch_pages = 0;
415 agp_free_page_array(new);
416 return new;
417 }
418 if (type == AGP_PHYS_MEMORY)
419 return alloc_agpphysmem_i8xx(pg_count, type);
420 return NULL;
421 }
422
423 static void intel_i810_free_by_type(struct agp_memory *curr)
424 {
425 agp_free_key(curr->key);
426 if (curr->type == AGP_PHYS_MEMORY) {
427 if (curr->page_count == 4)
428 i8xx_destroy_pages(curr->pages[0]);
429 else {
430 agp_bridge->driver->agp_destroy_page(curr->pages[0],
431 AGP_PAGE_DESTROY_UNMAP);
432 agp_bridge->driver->agp_destroy_page(curr->pages[0],
433 AGP_PAGE_DESTROY_FREE);
434 }
435 agp_free_page_array(curr);
436 }
437 kfree(curr);
438 }
439
440 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
441 dma_addr_t addr, int type)
442 {
443 /* Type checking must be done elsewhere */
444 return addr | bridge->driver->masks[type].mask;
445 }
446
447 static int intel_gtt_setup_scratch_page(void)
448 {
449 struct page *page;
450 dma_addr_t dma_addr;
451
452 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
453 if (page == NULL)
454 return -ENOMEM;
455 get_page(page);
456 set_pages_uc(page, 1);
457
458 if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) {
459 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
460 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
461 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
462 return -EINVAL;
463
464 intel_private.scratch_page_dma = dma_addr;
465 } else
466 intel_private.scratch_page_dma = page_to_phys(page);
467
468 intel_private.scratch_page = page;
469
470 return 0;
471 }
472
473 static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = {
474 {128, 32768, 5},
475 /* The 64M mode still requires a 128k gatt */
476 {64, 16384, 5},
477 {256, 65536, 6},
478 {512, 131072, 7},
479 };
480
481 static unsigned int intel_gtt_stolen_entries(void)
482 {
483 u16 gmch_ctrl;
484 u8 rdct;
485 int local = 0;
486 static const int ddt[4] = { 0, 16, 32, 64 };
487 unsigned int overhead_entries, stolen_entries;
488 unsigned int stolen_size = 0;
489
490 pci_read_config_word(intel_private.bridge_dev,
491 I830_GMCH_CTRL, &gmch_ctrl);
492
493 if (INTEL_GTT_GEN > 4 || IS_PINEVIEW)
494 overhead_entries = 0;
495 else
496 overhead_entries = intel_private.base.gtt_mappable_entries
497 / 1024;
498
499 overhead_entries += 1; /* BIOS popup */
500
501 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
502 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
503 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
504 case I830_GMCH_GMS_STOLEN_512:
505 stolen_size = KB(512);
506 break;
507 case I830_GMCH_GMS_STOLEN_1024:
508 stolen_size = MB(1);
509 break;
510 case I830_GMCH_GMS_STOLEN_8192:
511 stolen_size = MB(8);
512 break;
513 case I830_GMCH_GMS_LOCAL:
514 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
515 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
516 MB(ddt[I830_RDRAM_DDT(rdct)]);
517 local = 1;
518 break;
519 default:
520 stolen_size = 0;
521 break;
522 }
523 } else if (INTEL_GTT_GEN == 6) {
524 /*
525 * SandyBridge has new memory control reg at 0x50.w
526 */
527 u16 snb_gmch_ctl;
528 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
529 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
530 case SNB_GMCH_GMS_STOLEN_32M:
531 stolen_size = MB(32);
532 break;
533 case SNB_GMCH_GMS_STOLEN_64M:
534 stolen_size = MB(64);
535 break;
536 case SNB_GMCH_GMS_STOLEN_96M:
537 stolen_size = MB(96);
538 break;
539 case SNB_GMCH_GMS_STOLEN_128M:
540 stolen_size = MB(128);
541 break;
542 case SNB_GMCH_GMS_STOLEN_160M:
543 stolen_size = MB(160);
544 break;
545 case SNB_GMCH_GMS_STOLEN_192M:
546 stolen_size = MB(192);
547 break;
548 case SNB_GMCH_GMS_STOLEN_224M:
549 stolen_size = MB(224);
550 break;
551 case SNB_GMCH_GMS_STOLEN_256M:
552 stolen_size = MB(256);
553 break;
554 case SNB_GMCH_GMS_STOLEN_288M:
555 stolen_size = MB(288);
556 break;
557 case SNB_GMCH_GMS_STOLEN_320M:
558 stolen_size = MB(320);
559 break;
560 case SNB_GMCH_GMS_STOLEN_352M:
561 stolen_size = MB(352);
562 break;
563 case SNB_GMCH_GMS_STOLEN_384M:
564 stolen_size = MB(384);
565 break;
566 case SNB_GMCH_GMS_STOLEN_416M:
567 stolen_size = MB(416);
568 break;
569 case SNB_GMCH_GMS_STOLEN_448M:
570 stolen_size = MB(448);
571 break;
572 case SNB_GMCH_GMS_STOLEN_480M:
573 stolen_size = MB(480);
574 break;
575 case SNB_GMCH_GMS_STOLEN_512M:
576 stolen_size = MB(512);
577 break;
578 }
579 } else {
580 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
581 case I855_GMCH_GMS_STOLEN_1M:
582 stolen_size = MB(1);
583 break;
584 case I855_GMCH_GMS_STOLEN_4M:
585 stolen_size = MB(4);
586 break;
587 case I855_GMCH_GMS_STOLEN_8M:
588 stolen_size = MB(8);
589 break;
590 case I855_GMCH_GMS_STOLEN_16M:
591 stolen_size = MB(16);
592 break;
593 case I855_GMCH_GMS_STOLEN_32M:
594 stolen_size = MB(32);
595 break;
596 case I915_GMCH_GMS_STOLEN_48M:
597 stolen_size = MB(48);
598 break;
599 case I915_GMCH_GMS_STOLEN_64M:
600 stolen_size = MB(64);
601 break;
602 case G33_GMCH_GMS_STOLEN_128M:
603 stolen_size = MB(128);
604 break;
605 case G33_GMCH_GMS_STOLEN_256M:
606 stolen_size = MB(256);
607 break;
608 case INTEL_GMCH_GMS_STOLEN_96M:
609 stolen_size = MB(96);
610 break;
611 case INTEL_GMCH_GMS_STOLEN_160M:
612 stolen_size = MB(160);
613 break;
614 case INTEL_GMCH_GMS_STOLEN_224M:
615 stolen_size = MB(224);
616 break;
617 case INTEL_GMCH_GMS_STOLEN_352M:
618 stolen_size = MB(352);
619 break;
620 default:
621 stolen_size = 0;
622 break;
623 }
624 }
625
626 if (!local && stolen_size > intel_max_stolen) {
627 dev_info(&intel_private.bridge_dev->dev,
628 "detected %dK stolen memory, trimming to %dK\n",
629 stolen_size / KB(1), intel_max_stolen / KB(1));
630 stolen_size = intel_max_stolen;
631 } else if (stolen_size > 0) {
632 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
633 stolen_size / KB(1), local ? "local" : "stolen");
634 } else {
635 dev_info(&intel_private.bridge_dev->dev,
636 "no pre-allocated video memory detected\n");
637 stolen_size = 0;
638 }
639
640 stolen_entries = stolen_size/KB(4) - overhead_entries;
641
642 return stolen_entries;
643 }
644
645 static void i965_adjust_pgetbl_size(unsigned int size_flag)
646 {
647 u32 pgetbl_ctl, pgetbl_ctl2;
648
649 /* ensure that ppgtt is disabled */
650 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
651 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
652 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
653
654 /* write the new ggtt size */
655 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
656 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
657 pgetbl_ctl |= size_flag;
658 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
659 }
660
661 static unsigned int i965_gtt_total_entries(void)
662 {
663 int size;
664 u32 pgetbl_ctl;
665 u16 gmch_ctl;
666
667 pci_read_config_word(intel_private.bridge_dev,
668 I830_GMCH_CTRL, &gmch_ctl);
669
670 if (INTEL_GTT_GEN == 5) {
671 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
672 case G4x_GMCH_SIZE_1M:
673 case G4x_GMCH_SIZE_VT_1M:
674 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
675 break;
676 case G4x_GMCH_SIZE_VT_1_5M:
677 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
678 break;
679 case G4x_GMCH_SIZE_2M:
680 case G4x_GMCH_SIZE_VT_2M:
681 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
682 break;
683 }
684 }
685
686 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
687
688 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
689 case I965_PGETBL_SIZE_128KB:
690 size = KB(128);
691 break;
692 case I965_PGETBL_SIZE_256KB:
693 size = KB(256);
694 break;
695 case I965_PGETBL_SIZE_512KB:
696 size = KB(512);
697 break;
698 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
699 case I965_PGETBL_SIZE_1MB:
700 size = KB(1024);
701 break;
702 case I965_PGETBL_SIZE_2MB:
703 size = KB(2048);
704 break;
705 case I965_PGETBL_SIZE_1_5MB:
706 size = KB(1024 + 512);
707 break;
708 default:
709 dev_info(&intel_private.pcidev->dev,
710 "unknown page table size, assuming 512KB\n");
711 size = KB(512);
712 }
713
714 return size/4;
715 }
716
717 static unsigned int intel_gtt_total_entries(void)
718 {
719 int size;
720
721 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
722 return i965_gtt_total_entries();
723 else if (INTEL_GTT_GEN == 6) {
724 u16 snb_gmch_ctl;
725
726 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
727 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
728 default:
729 case SNB_GTT_SIZE_0M:
730 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
731 size = MB(0);
732 break;
733 case SNB_GTT_SIZE_1M:
734 size = MB(1);
735 break;
736 case SNB_GTT_SIZE_2M:
737 size = MB(2);
738 break;
739 }
740 return size/4;
741 } else {
742 /* On previous hardware, the GTT size was just what was
743 * required to map the aperture.
744 */
745 return intel_private.base.gtt_mappable_entries;
746 }
747 }
748
749 static unsigned int intel_gtt_mappable_entries(void)
750 {
751 unsigned int aperture_size;
752
753 if (INTEL_GTT_GEN == 2) {
754 u16 gmch_ctrl;
755
756 pci_read_config_word(intel_private.bridge_dev,
757 I830_GMCH_CTRL, &gmch_ctrl);
758
759 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
760 aperture_size = MB(64);
761 else
762 aperture_size = MB(128);
763 } else {
764 /* 9xx supports large sizes, just look at the length */
765 aperture_size = pci_resource_len(intel_private.pcidev, 2);
766 }
767
768 return aperture_size >> PAGE_SHIFT;
769 }
770
771 static void intel_gtt_teardown_scratch_page(void)
772 {
773 set_pages_wb(intel_private.scratch_page, 1);
774 pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
775 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
776 put_page(intel_private.scratch_page);
777 __free_page(intel_private.scratch_page);
778 }
779
780 static void intel_gtt_cleanup(void)
781 {
782 intel_private.driver->cleanup();
783
784 iounmap(intel_private.gtt);
785 iounmap(intel_private.registers);
786
787 intel_gtt_teardown_scratch_page();
788 }
789
790 static int intel_gtt_init(void)
791 {
792 u32 gtt_map_size;
793 int ret;
794
795 ret = intel_private.driver->setup();
796 if (ret != 0)
797 return ret;
798
799 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
800 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
801
802 /* save the PGETBL reg for resume */
803 intel_private.PGETBL_save =
804 readl(intel_private.registers+I810_PGETBL_CTL)
805 & ~I810_PGETBL_ENABLED;
806
807 dev_info(&intel_private.bridge_dev->dev,
808 "detected gtt size: %dK total, %dK mappable\n",
809 intel_private.base.gtt_total_entries * 4,
810 intel_private.base.gtt_mappable_entries * 4);
811
812 gtt_map_size = intel_private.base.gtt_total_entries * 4;
813
814 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
815 gtt_map_size);
816 if (!intel_private.gtt) {
817 intel_private.driver->cleanup();
818 iounmap(intel_private.registers);
819 return -ENOMEM;
820 }
821
822 global_cache_flush(); /* FIXME: ? */
823
824 /* we have to call this as early as possible after the MMIO base address is known */
825 intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries();
826 if (intel_private.base.gtt_stolen_entries == 0) {
827 intel_private.driver->cleanup();
828 iounmap(intel_private.registers);
829 iounmap(intel_private.gtt);
830 return -ENOMEM;
831 }
832
833 ret = intel_gtt_setup_scratch_page();
834 if (ret != 0) {
835 intel_gtt_cleanup();
836 return ret;
837 }
838
839 return 0;
840 }
841
842 static int intel_fake_agp_fetch_size(void)
843 {
844 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
845 unsigned int aper_size;
846 int i;
847
848 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
849 / MB(1);
850
851 for (i = 0; i < num_sizes; i++) {
852 if (aper_size == intel_fake_agp_sizes[i].size) {
853 agp_bridge->current_size =
854 (void *) (intel_fake_agp_sizes + i);
855 return aper_size;
856 }
857 }
858
859 return 0;
860 }
861
862 static void i830_cleanup(void)
863 {
864 kunmap(intel_private.i8xx_page);
865 intel_private.i8xx_flush_page = NULL;
866
867 __free_page(intel_private.i8xx_page);
868 intel_private.i8xx_page = NULL;
869 }
870
871 static void intel_i830_setup_flush(void)
872 {
873 /* return if we've already set the flush mechanism up */
874 if (intel_private.i8xx_page)
875 return;
876
877 intel_private.i8xx_page = alloc_page(GFP_KERNEL);
878 if (!intel_private.i8xx_page)
879 return;
880
881 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
882 if (!intel_private.i8xx_flush_page)
883 i830_cleanup();
884 }
885
886 /* The chipset_flush interface needs to get data that has already been
887 * flushed out of the CPU all the way out to main memory, because the GPU
888 * doesn't snoop those buffers.
889 *
890 * The 8xx series doesn't have the same lovely interface for flushing the
891 * chipset write buffers that the later chips do. According to the 865
892 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
893 * that buffer out, we just fill 1KB and clflush it out, on the assumption
894 * that it'll push whatever was in there out. It appears to work.
895 */
896 static void i830_chipset_flush(void)
897 {
898 unsigned int *pg = intel_private.i8xx_flush_page;
899
900 memset(pg, 0, 1024);
901
902 if (cpu_has_clflush)
903 clflush_cache_range(pg, 1024);
904 else if (wbinvd_on_all_cpus() != 0)
905 printk(KERN_ERR "Timed out waiting for cache flush.\n");
906 }
907
908 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
909 unsigned int flags)
910 {
911 u32 pte_flags = I810_PTE_VALID;
912
913 switch (flags) {
914 case AGP_DCACHE_MEMORY:
915 pte_flags |= I810_PTE_LOCAL;
916 break;
917 case AGP_USER_CACHED_MEMORY:
918 pte_flags |= I830_PTE_SYSTEM_CACHED;
919 break;
920 }
921
922 writel(addr | pte_flags, intel_private.gtt + entry);
923 }
924
925 static void intel_enable_gtt(void)
926 {
927 u32 gma_addr;
928 u16 gmch_ctrl;
929
930 if (INTEL_GTT_GEN == 2)
931 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
932 &gma_addr);
933 else
934 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
935 &gma_addr);
936
937 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
938
939 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
940 gmch_ctrl |= I830_GMCH_ENABLED;
941 pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
942
943 writel(intel_private.PGETBL_save|I810_PGETBL_ENABLED,
944 intel_private.registers+I810_PGETBL_CTL);
945 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
946 }
947
948 static int i830_setup(void)
949 {
950 u32 reg_addr;
951
952 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
953 reg_addr &= 0xfff80000;
954
955 intel_private.registers = ioremap(reg_addr, KB(64));
956 if (!intel_private.registers)
957 return -ENOMEM;
958
959 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
960
961 intel_i830_setup_flush();
962
963 return 0;
964 }
965
966 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
967 {
968 agp_bridge->gatt_table_real = NULL;
969 agp_bridge->gatt_table = NULL;
970 agp_bridge->gatt_bus_addr = 0;
971
972 return 0;
973 }
974
975 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
976 {
977 return 0;
978 }
979
980 static int intel_fake_agp_configure(void)
981 {
982 int i;
983
984 intel_enable_gtt();
985
986 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
987
988 for (i = intel_private.base.gtt_stolen_entries;
989 i < intel_private.base.gtt_total_entries; i++) {
990 intel_private.driver->write_entry(intel_private.scratch_page_dma,
991 i, 0);
992 }
993 readl(intel_private.gtt+i-1); /* PCI Posting. */
994
995 global_cache_flush();
996
997 return 0;
998 }
999
1000 static bool i830_check_flags(unsigned int flags)
1001 {
1002 switch (flags) {
1003 case 0:
1004 case AGP_PHYS_MEMORY:
1005 case AGP_USER_CACHED_MEMORY:
1006 case AGP_USER_MEMORY:
1007 return true;
1008 }
1009
1010 return false;
1011 }
1012
1013 static void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
1014 unsigned int sg_len,
1015 unsigned int pg_start,
1016 unsigned int flags)
1017 {
1018 struct scatterlist *sg;
1019 unsigned int len, m;
1020 int i, j;
1021
1022 j = pg_start;
1023
1024 /* sg may merge pages, but we have to separate
1025 * per-page addr for GTT */
1026 for_each_sg(sg_list, sg, sg_len, i) {
1027 len = sg_dma_len(sg) >> PAGE_SHIFT;
1028 for (m = 0; m < len; m++) {
1029 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
1030 intel_private.driver->write_entry(addr,
1031 j, flags);
1032 j++;
1033 }
1034 }
1035 readl(intel_private.gtt+j-1);
1036 }
1037
1038 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
1039 off_t pg_start, int type)
1040 {
1041 int i, j;
1042 int ret = -EINVAL;
1043
1044 if (mem->page_count == 0)
1045 goto out;
1046
1047 if (pg_start < intel_private.base.gtt_stolen_entries) {
1048 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1049 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1050 pg_start, intel_private.base.gtt_stolen_entries);
1051
1052 dev_info(&intel_private.pcidev->dev,
1053 "trying to insert into local/stolen memory\n");
1054 goto out_err;
1055 }
1056
1057 if ((pg_start + mem->page_count) > intel_private.base.gtt_total_entries)
1058 goto out_err;
1059
1060 if (type != mem->type)
1061 goto out_err;
1062
1063 if (!intel_private.driver->check_flags(type))
1064 goto out_err;
1065
1066 if (!mem->is_flushed)
1067 global_cache_flush();
1068
1069 if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) {
1070 ret = intel_agp_map_memory(mem);
1071 if (ret != 0)
1072 return ret;
1073
1074 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg,
1075 pg_start, type);
1076 } else {
1077 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1078 dma_addr_t addr = page_to_phys(mem->pages[i]);
1079 intel_private.driver->write_entry(addr,
1080 j, type);
1081 }
1082 readl(intel_private.gtt+j-1);
1083 }
1084
1085 out:
1086 ret = 0;
1087 out_err:
1088 mem->is_flushed = true;
1089 return ret;
1090 }
1091
1092 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
1093 off_t pg_start, int type)
1094 {
1095 int i;
1096
1097 if (mem->page_count == 0)
1098 return 0;
1099
1100 if (pg_start < intel_private.base.gtt_stolen_entries) {
1101 dev_info(&intel_private.pcidev->dev,
1102 "trying to disable local/stolen memory\n");
1103 return -EINVAL;
1104 }
1105
1106 if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2)
1107 intel_agp_unmap_memory(mem);
1108
1109 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1110 intel_private.driver->write_entry(intel_private.scratch_page_dma,
1111 i, 0);
1112 }
1113 readl(intel_private.gtt+i-1);
1114
1115 return 0;
1116 }
1117
1118 static void intel_fake_agp_chipset_flush(struct agp_bridge_data *bridge)
1119 {
1120 intel_private.driver->chipset_flush();
1121 }
1122
1123 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1124 int type)
1125 {
1126 if (type == AGP_PHYS_MEMORY)
1127 return alloc_agpphysmem_i8xx(pg_count, type);
1128 /* always return NULL for other allocation types for now */
1129 return NULL;
1130 }
1131
1132 static int intel_alloc_chipset_flush_resource(void)
1133 {
1134 int ret;
1135 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1136 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1137 pcibios_align_resource, intel_private.bridge_dev);
1138
1139 return ret;
1140 }
1141
1142 static void intel_i915_setup_chipset_flush(void)
1143 {
1144 int ret;
1145 u32 temp;
1146
1147 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1148 if (!(temp & 0x1)) {
1149 intel_alloc_chipset_flush_resource();
1150 intel_private.resource_valid = 1;
1151 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1152 } else {
1153 temp &= ~1;
1154
1155 intel_private.resource_valid = 1;
1156 intel_private.ifp_resource.start = temp;
1157 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1158 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1159 /* some BIOSes reserve this area in a pnp some don't */
1160 if (ret)
1161 intel_private.resource_valid = 0;
1162 }
1163 }
1164
1165 static void intel_i965_g33_setup_chipset_flush(void)
1166 {
1167 u32 temp_hi, temp_lo;
1168 int ret;
1169
1170 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1171 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1172
1173 if (!(temp_lo & 0x1)) {
1174
1175 intel_alloc_chipset_flush_resource();
1176
1177 intel_private.resource_valid = 1;
1178 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1179 upper_32_bits(intel_private.ifp_resource.start));
1180 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1181 } else {
1182 u64 l64;
1183
1184 temp_lo &= ~0x1;
1185 l64 = ((u64)temp_hi << 32) | temp_lo;
1186
1187 intel_private.resource_valid = 1;
1188 intel_private.ifp_resource.start = l64;
1189 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1190 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1191 /* some BIOSes reserve this area in a pnp some don't */
1192 if (ret)
1193 intel_private.resource_valid = 0;
1194 }
1195 }
1196
1197 static void intel_i9xx_setup_flush(void)
1198 {
1199 /* return if already configured */
1200 if (intel_private.ifp_resource.start)
1201 return;
1202
1203 if (INTEL_GTT_GEN == 6)
1204 return;
1205
1206 /* setup a resource for this object */
1207 intel_private.ifp_resource.name = "Intel Flush Page";
1208 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1209
1210 /* Setup chipset flush for 915 */
1211 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1212 intel_i965_g33_setup_chipset_flush();
1213 } else {
1214 intel_i915_setup_chipset_flush();
1215 }
1216
1217 if (intel_private.ifp_resource.start)
1218 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1219 if (!intel_private.i9xx_flush_page)
1220 dev_err(&intel_private.pcidev->dev,
1221 "can't ioremap flush page - no chipset flushing\n");
1222 }
1223
1224 static void i9xx_cleanup(void)
1225 {
1226 if (intel_private.i9xx_flush_page)
1227 iounmap(intel_private.i9xx_flush_page);
1228 if (intel_private.resource_valid)
1229 release_resource(&intel_private.ifp_resource);
1230 intel_private.ifp_resource.start = 0;
1231 intel_private.resource_valid = 0;
1232 }
1233
1234 static void i9xx_chipset_flush(void)
1235 {
1236 if (intel_private.i9xx_flush_page)
1237 writel(1, intel_private.i9xx_flush_page);
1238 }
1239
1240 static void i965_write_entry(dma_addr_t addr, unsigned int entry,
1241 unsigned int flags)
1242 {
1243 /* Shift high bits down */
1244 addr |= (addr >> 28) & 0xf0;
1245 writel(addr | I810_PTE_VALID, intel_private.gtt + entry);
1246 }
1247
1248 static bool gen6_check_flags(unsigned int flags)
1249 {
1250 return true;
1251 }
1252
1253 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1254 unsigned int flags)
1255 {
1256 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1257 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1258 u32 pte_flags;
1259
1260 if (type_mask == AGP_USER_UNCACHED_MEMORY)
1261 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1262 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1263 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1264 if (gfdt)
1265 pte_flags |= GEN6_PTE_GFDT;
1266 } else { /* set 'normal'/'cached' to LLC by default */
1267 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1268 if (gfdt)
1269 pte_flags |= GEN6_PTE_GFDT;
1270 }
1271
1272 /* gen6 has bit11-4 for physical addr bit39-32 */
1273 addr |= (addr >> 28) & 0xff0;
1274 writel(addr | pte_flags, intel_private.gtt + entry);
1275 }
1276
1277 static void gen6_cleanup(void)
1278 {
1279 }
1280
1281 static int i9xx_setup(void)
1282 {
1283 u32 reg_addr;
1284
1285 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1286
1287 reg_addr &= 0xfff80000;
1288
1289 intel_private.registers = ioremap(reg_addr, 128 * 4096);
1290 if (!intel_private.registers)
1291 return -ENOMEM;
1292
1293 if (INTEL_GTT_GEN == 3) {
1294 u32 gtt_addr;
1295
1296 pci_read_config_dword(intel_private.pcidev,
1297 I915_PTEADDR, &gtt_addr);
1298 intel_private.gtt_bus_addr = gtt_addr;
1299 } else {
1300 u32 gtt_offset;
1301
1302 switch (INTEL_GTT_GEN) {
1303 case 5:
1304 case 6:
1305 gtt_offset = MB(2);
1306 break;
1307 case 4:
1308 default:
1309 gtt_offset = KB(512);
1310 break;
1311 }
1312 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1313 }
1314
1315 intel_i9xx_setup_flush();
1316
1317 return 0;
1318 }
1319
1320 static const struct agp_bridge_driver intel_810_driver = {
1321 .owner = THIS_MODULE,
1322 .aperture_sizes = intel_i810_sizes,
1323 .size_type = FIXED_APER_SIZE,
1324 .num_aperture_sizes = 2,
1325 .needs_scratch_page = true,
1326 .configure = intel_i810_configure,
1327 .fetch_size = intel_i810_fetch_size,
1328 .cleanup = intel_i810_cleanup,
1329 .mask_memory = intel_i810_mask_memory,
1330 .masks = intel_i810_masks,
1331 .agp_enable = intel_fake_agp_enable,
1332 .cache_flush = global_cache_flush,
1333 .create_gatt_table = agp_generic_create_gatt_table,
1334 .free_gatt_table = agp_generic_free_gatt_table,
1335 .insert_memory = intel_i810_insert_entries,
1336 .remove_memory = intel_i810_remove_entries,
1337 .alloc_by_type = intel_i810_alloc_by_type,
1338 .free_by_type = intel_i810_free_by_type,
1339 .agp_alloc_page = agp_generic_alloc_page,
1340 .agp_alloc_pages = agp_generic_alloc_pages,
1341 .agp_destroy_page = agp_generic_destroy_page,
1342 .agp_destroy_pages = agp_generic_destroy_pages,
1343 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1344 };
1345
1346 static const struct agp_bridge_driver intel_fake_agp_driver = {
1347 .owner = THIS_MODULE,
1348 .size_type = FIXED_APER_SIZE,
1349 .aperture_sizes = intel_fake_agp_sizes,
1350 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1351 .configure = intel_fake_agp_configure,
1352 .fetch_size = intel_fake_agp_fetch_size,
1353 .cleanup = intel_gtt_cleanup,
1354 .agp_enable = intel_fake_agp_enable,
1355 .cache_flush = global_cache_flush,
1356 .create_gatt_table = intel_fake_agp_create_gatt_table,
1357 .free_gatt_table = intel_fake_agp_free_gatt_table,
1358 .insert_memory = intel_fake_agp_insert_entries,
1359 .remove_memory = intel_fake_agp_remove_entries,
1360 .alloc_by_type = intel_fake_agp_alloc_by_type,
1361 .free_by_type = intel_i810_free_by_type,
1362 .agp_alloc_page = agp_generic_alloc_page,
1363 .agp_alloc_pages = agp_generic_alloc_pages,
1364 .agp_destroy_page = agp_generic_destroy_page,
1365 .agp_destroy_pages = agp_generic_destroy_pages,
1366 .chipset_flush = intel_fake_agp_chipset_flush,
1367 };
1368
1369 static const struct intel_gtt_driver i81x_gtt_driver = {
1370 .gen = 1,
1371 .dma_mask_size = 32,
1372 };
1373 static const struct intel_gtt_driver i8xx_gtt_driver = {
1374 .gen = 2,
1375 .setup = i830_setup,
1376 .cleanup = i830_cleanup,
1377 .write_entry = i830_write_entry,
1378 .dma_mask_size = 32,
1379 .check_flags = i830_check_flags,
1380 .chipset_flush = i830_chipset_flush,
1381 };
1382 static const struct intel_gtt_driver i915_gtt_driver = {
1383 .gen = 3,
1384 .setup = i9xx_setup,
1385 .cleanup = i9xx_cleanup,
1386 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1387 .write_entry = i830_write_entry,
1388 .dma_mask_size = 32,
1389 .check_flags = i830_check_flags,
1390 .chipset_flush = i9xx_chipset_flush,
1391 };
1392 static const struct intel_gtt_driver g33_gtt_driver = {
1393 .gen = 3,
1394 .is_g33 = 1,
1395 .setup = i9xx_setup,
1396 .cleanup = i9xx_cleanup,
1397 .write_entry = i965_write_entry,
1398 .dma_mask_size = 36,
1399 .check_flags = i830_check_flags,
1400 .chipset_flush = i9xx_chipset_flush,
1401 };
1402 static const struct intel_gtt_driver pineview_gtt_driver = {
1403 .gen = 3,
1404 .is_pineview = 1, .is_g33 = 1,
1405 .setup = i9xx_setup,
1406 .cleanup = i9xx_cleanup,
1407 .write_entry = i965_write_entry,
1408 .dma_mask_size = 36,
1409 .check_flags = i830_check_flags,
1410 .chipset_flush = i9xx_chipset_flush,
1411 };
1412 static const struct intel_gtt_driver i965_gtt_driver = {
1413 .gen = 4,
1414 .setup = i9xx_setup,
1415 .cleanup = i9xx_cleanup,
1416 .write_entry = i965_write_entry,
1417 .dma_mask_size = 36,
1418 .check_flags = i830_check_flags,
1419 .chipset_flush = i9xx_chipset_flush,
1420 };
1421 static const struct intel_gtt_driver g4x_gtt_driver = {
1422 .gen = 5,
1423 .setup = i9xx_setup,
1424 .cleanup = i9xx_cleanup,
1425 .write_entry = i965_write_entry,
1426 .dma_mask_size = 36,
1427 .check_flags = i830_check_flags,
1428 .chipset_flush = i9xx_chipset_flush,
1429 };
1430 static const struct intel_gtt_driver ironlake_gtt_driver = {
1431 .gen = 5,
1432 .is_ironlake = 1,
1433 .setup = i9xx_setup,
1434 .cleanup = i9xx_cleanup,
1435 .write_entry = i965_write_entry,
1436 .dma_mask_size = 36,
1437 .check_flags = i830_check_flags,
1438 .chipset_flush = i9xx_chipset_flush,
1439 };
1440 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1441 .gen = 6,
1442 .setup = i9xx_setup,
1443 .cleanup = gen6_cleanup,
1444 .write_entry = gen6_write_entry,
1445 .dma_mask_size = 40,
1446 .check_flags = gen6_check_flags,
1447 .chipset_flush = i9xx_chipset_flush,
1448 };
1449
1450 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1451 * driver and gmch_driver must be non-null, and find_gmch will determine
1452 * which one should be used if a gmch_chip_id is present.
1453 */
1454 static const struct intel_gtt_driver_description {
1455 unsigned int gmch_chip_id;
1456 char *name;
1457 const struct agp_bridge_driver *gmch_driver;
1458 const struct intel_gtt_driver *gtt_driver;
1459 } intel_gtt_chipsets[] = {
1460 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver,
1461 &i81x_gtt_driver},
1462 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver,
1463 &i81x_gtt_driver},
1464 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver,
1465 &i81x_gtt_driver},
1466 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver,
1467 &i81x_gtt_driver},
1468 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1469 &intel_fake_agp_driver, &i8xx_gtt_driver},
1470 { PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1471 &intel_fake_agp_driver, &i8xx_gtt_driver},
1472 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1473 &intel_fake_agp_driver, &i8xx_gtt_driver},
1474 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1475 &intel_fake_agp_driver, &i8xx_gtt_driver},
1476 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1477 &intel_fake_agp_driver, &i8xx_gtt_driver},
1478 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1479 &intel_fake_agp_driver, &i915_gtt_driver },
1480 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1481 &intel_fake_agp_driver, &i915_gtt_driver },
1482 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1483 &intel_fake_agp_driver, &i915_gtt_driver },
1484 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1485 &intel_fake_agp_driver, &i915_gtt_driver },
1486 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1487 &intel_fake_agp_driver, &i915_gtt_driver },
1488 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1489 &intel_fake_agp_driver, &i915_gtt_driver },
1490 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1491 &intel_fake_agp_driver, &i965_gtt_driver },
1492 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1493 &intel_fake_agp_driver, &i965_gtt_driver },
1494 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1495 &intel_fake_agp_driver, &i965_gtt_driver },
1496 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1497 &intel_fake_agp_driver, &i965_gtt_driver },
1498 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1499 &intel_fake_agp_driver, &i965_gtt_driver },
1500 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1501 &intel_fake_agp_driver, &i965_gtt_driver },
1502 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1503 &intel_fake_agp_driver, &g33_gtt_driver },
1504 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1505 &intel_fake_agp_driver, &g33_gtt_driver },
1506 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1507 &intel_fake_agp_driver, &g33_gtt_driver },
1508 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1509 &intel_fake_agp_driver, &pineview_gtt_driver },
1510 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1511 &intel_fake_agp_driver, &pineview_gtt_driver },
1512 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1513 &intel_fake_agp_driver, &g4x_gtt_driver },
1514 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1515 &intel_fake_agp_driver, &g4x_gtt_driver },
1516 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1517 &intel_fake_agp_driver, &g4x_gtt_driver },
1518 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1519 &intel_fake_agp_driver, &g4x_gtt_driver },
1520 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1521 &intel_fake_agp_driver, &g4x_gtt_driver },
1522 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1523 &intel_fake_agp_driver, &g4x_gtt_driver },
1524 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1525 &intel_fake_agp_driver, &g4x_gtt_driver },
1526 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1527 "HD Graphics", &intel_fake_agp_driver, &ironlake_gtt_driver },
1528 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1529 "HD Graphics", &intel_fake_agp_driver, &ironlake_gtt_driver },
1530 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1531 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1532 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1533 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1534 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1535 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1536 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1537 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1538 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1539 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1540 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1541 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1542 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1543 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1544 { 0, NULL, NULL }
1545 };
1546
1547 static int find_gmch(u16 device)
1548 {
1549 struct pci_dev *gmch_device;
1550
1551 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1552 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1553 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1554 device, gmch_device);
1555 }
1556
1557 if (!gmch_device)
1558 return 0;
1559
1560 intel_private.pcidev = gmch_device;
1561 return 1;
1562 }
1563
1564 int intel_gmch_probe(struct pci_dev *pdev,
1565 struct agp_bridge_data *bridge)
1566 {
1567 int i, mask;
1568 bridge->driver = NULL;
1569
1570 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1571 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1572 bridge->driver =
1573 intel_gtt_chipsets[i].gmch_driver;
1574 intel_private.driver =
1575 intel_gtt_chipsets[i].gtt_driver;
1576 break;
1577 }
1578 }
1579
1580 if (!bridge->driver)
1581 return 0;
1582
1583 bridge->dev_private_data = &intel_private;
1584 bridge->dev = pdev;
1585
1586 intel_private.bridge_dev = pci_dev_get(pdev);
1587
1588 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1589
1590 mask = intel_private.driver->dma_mask_size;
1591 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1592 dev_err(&intel_private.pcidev->dev,
1593 "set gfx device dma mask %d-bit failed!\n", mask);
1594 else
1595 pci_set_consistent_dma_mask(intel_private.pcidev,
1596 DMA_BIT_MASK(mask));
1597
1598 if (bridge->driver == &intel_810_driver)
1599 return 1;
1600
1601 if (intel_gtt_init() != 0)
1602 return 0;
1603
1604 return 1;
1605 }
1606 EXPORT_SYMBOL(intel_gmch_probe);
1607
1608 struct intel_gtt *intel_gtt_get(void)
1609 {
1610 return &intel_private.base;
1611 }
1612 EXPORT_SYMBOL(intel_gtt_get);
1613
1614 void intel_gmch_remove(struct pci_dev *pdev)
1615 {
1616 if (intel_private.pcidev)
1617 pci_dev_put(intel_private.pcidev);
1618 if (intel_private.bridge_dev)
1619 pci_dev_put(intel_private.bridge_dev);
1620 }
1621 EXPORT_SYMBOL(intel_gmch_remove);
1622
1623 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1624 MODULE_LICENSE("GPL and additional rights");
Linux with added FPC-III support