drivers/ata/pata_rdc.c

   1 /*
   2  *  pata_rdc            -       Driver for later RDC PATA controllers
   3  *
   4  *  This is actually a driver for hardware meeting
   5  *  INCITS 370-2004 (1510D): ATA Host Adapter Standards
   6  *
   7  *  Based on ata_piix.
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License as published by
  11  *  the Free Software Foundation; either version 2, or (at your option)
  12  *  any later version.
  13  *
  14  *  This program is distributed in the hope that it will be useful,
  15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *  GNU General Public License for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License
  20  *  along with this program; see the file COPYING.  If not, write to
  21  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27 #include <linux/blkdev.h>
  28 #include <linux/delay.h>
  29 #include <linux/device.h>
  30 #include <linux/gfp.h>
  31 #include <scsi/scsi_host.h>
  32 #include <linux/libata.h>
  33 #include <linux/dmi.h>
  34
  35 #define DRV_NAME        "pata_rdc"
  36 #define DRV_VERSION     "0.01"
  37
  38 struct rdc_host_priv {
  39         u32 saved_iocfg;
  40 };
  41
  42 /**
  43  *      rdc_pata_cable_detect - Probe host controller cable detect info
  44  *      @ap: Port for which cable detect info is desired
  45  *
  46  *      Read 80c cable indicator from ATA PCI device's PCI config
  47  *      register.  This register is normally set by firmware (BIOS).
  48  *
  49  *      LOCKING:
  50  *      None (inherited from caller).
  51  */
  52
  53 static int rdc_pata_cable_detect(struct ata_port *ap)
  54 {
  55         struct rdc_host_priv *hpriv = ap->host->private_data;
  56         u8 mask;
  57
  58         /* check BIOS cable detect results */
  59         mask = 0x30 << (2 * ap->port_no);
  60         if ((hpriv->saved_iocfg & mask) == 0)
  61                 return ATA_CBL_PATA40;
  62         return ATA_CBL_PATA80;
  63 }
  64
  65 /**
  66  *      rdc_pata_prereset - prereset for PATA host controller
  67  *      @link: Target link
  68  *      @deadline: deadline jiffies for the operation
  69  *
  70  *      LOCKING:
  71  *      None (inherited from caller).
  72  */
  73 static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
  74 {
  75         struct ata_port *ap = link->ap;
  76         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  77
  78         static const struct pci_bits rdc_enable_bits[] = {
  79                 { 0x41U, 1U, 0x80UL, 0x80UL },  /* port 0 */
  80                 { 0x43U, 1U, 0x80UL, 0x80UL },  /* port 1 */
  81         };
  82
  83         if (!pci_test_config_bits(pdev, &rdc_enable_bits[ap->port_no]))
  84                 return -ENOENT;
  85         return ata_sff_prereset(link, deadline);
  86 }
  87
  88 static DEFINE_SPINLOCK(rdc_lock);
  89
  90 /**
  91  *      rdc_set_piomode - Initialize host controller PATA PIO timings
  92  *      @ap: Port whose timings we are configuring
  93  *      @adev: um
  94  *
  95  *      Set PIO mode for device, in host controller PCI config space.
  96  *
  97  *      LOCKING:
  98  *      None (inherited from caller).
  99  */
 100
 101 static void rdc_set_piomode(struct ata_port *ap, struct ata_device *adev)
 102 {
 103         unsigned int pio        = adev->pio_mode - XFER_PIO_0;
 104         struct pci_dev *dev     = to_pci_dev(ap->host->dev);
 105         unsigned long flags;
 106         unsigned int is_slave   = (adev->devno != 0);
 107         unsigned int master_port= ap->port_no ? 0x42 : 0x40;
 108         unsigned int slave_port = 0x44;
 109         u16 master_data;
 110         u8 slave_data;
 111         u8 udma_enable;
 112         int control = 0;
 113
 114         static const     /* ISP  RTC */
 115         u8 timings[][2] = { { 0, 0 },
 116                             { 0, 0 },
 117                             { 1, 0 },
 118                             { 2, 1 },
 119                             { 2, 3 }, };
 120
 121         if (pio >= 2)
 122                 control |= 1;   /* TIME1 enable */
 123         if (ata_pio_need_iordy(adev))
 124                 control |= 2;   /* IE enable */
 125
 126         if (adev->class == ATA_DEV_ATA)
 127                 control |= 4;   /* PPE enable */
 128
 129         spin_lock_irqsave(&rdc_lock, flags);
 130
 131         /* PIO configuration clears DTE unconditionally.  It will be
 132          * programmed in set_dmamode which is guaranteed to be called
 133          * after set_piomode if any DMA mode is available.
 134          */
 135         pci_read_config_word(dev, master_port, &master_data);
 136         if (is_slave) {
 137                 /* clear TIME1|IE1|PPE1|DTE1 */
 138                 master_data &= 0xff0f;
 139                 /* Enable SITRE (separate slave timing register) */
 140                 master_data |= 0x4000;
 141                 /* enable PPE1, IE1 and TIME1 as needed */
 142                 master_data |= (control << 4);
 143                 pci_read_config_byte(dev, slave_port, &slave_data);
 144                 slave_data &= (ap->port_no ? 0x0f : 0xf0);
 145                 /* Load the timing nibble for this slave */
 146                 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
 147                                                 << (ap->port_no ? 4 : 0);
 148         } else {
 149                 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
 150                 master_data &= 0xccf0;
 151                 /* Enable PPE, IE and TIME as appropriate */
 152                 master_data |= control;
 153                 /* load ISP and RCT */
 154                 master_data |=
 155                         (timings[pio][0] << 12) |
 156                         (timings[pio][1] << 8);
 157         }
 158         pci_write_config_word(dev, master_port, master_data);
 159         if (is_slave)
 160                 pci_write_config_byte(dev, slave_port, slave_data);
 161
 162         /* Ensure the UDMA bit is off - it will be turned back on if
 163            UDMA is selected */
 164
 165         pci_read_config_byte(dev, 0x48, &udma_enable);
 166         udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
 167         pci_write_config_byte(dev, 0x48, udma_enable);
 168
 169         spin_unlock_irqrestore(&rdc_lock, flags);
 170 }
 171
 172 /**
 173  *      rdc_set_dmamode - Initialize host controller PATA PIO timings
 174  *      @ap: Port whose timings we are configuring
 175  *      @adev: Drive in question
 176  *
 177  *      Set UDMA mode for device, in host controller PCI config space.
 178  *
 179  *      LOCKING:
 180  *      None (inherited from caller).
 181  */
 182
 183 static void rdc_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 184 {
 185         struct pci_dev *dev     = to_pci_dev(ap->host->dev);
 186         unsigned long flags;
 187         u8 master_port          = ap->port_no ? 0x42 : 0x40;
 188         u16 master_data;
 189         u8 speed                = adev->dma_mode;
 190         int devid               = adev->devno + 2 * ap->port_no;
 191         u8 udma_enable          = 0;
 192
 193         static const     /* ISP  RTC */
 194         u8 timings[][2] = { { 0, 0 },
 195                             { 0, 0 },
 196                             { 1, 0 },
 197                             { 2, 1 },
 198                             { 2, 3 }, };
 199
 200         spin_lock_irqsave(&rdc_lock, flags);
 201
 202         pci_read_config_word(dev, master_port, &master_data);
 203         pci_read_config_byte(dev, 0x48, &udma_enable);
 204
 205         if (speed >= XFER_UDMA_0) {
 206                 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
 207                 u16 udma_timing;
 208                 u16 ideconf;
 209                 int u_clock, u_speed;
 210
 211                 /*
 212                  * UDMA is handled by a combination of clock switching and
 213                  * selection of dividers
 214                  *
 215                  * Handy rule: Odd modes are UDMATIMx 01, even are 02
 216                  *             except UDMA0 which is 00
 217                  */
 218                 u_speed = min(2 - (udma & 1), udma);
 219                 if (udma == 5)
 220                         u_clock = 0x1000;       /* 100Mhz */
 221                 else if (udma > 2)
 222                         u_clock = 1;            /* 66Mhz */
 223                 else
 224                         u_clock = 0;            /* 33Mhz */
 225
 226                 udma_enable |= (1 << devid);
 227
 228                 /* Load the CT/RP selection */
 229                 pci_read_config_word(dev, 0x4A, &udma_timing);
 230                 udma_timing &= ~(3 << (4 * devid));
 231                 udma_timing |= u_speed << (4 * devid);
 232                 pci_write_config_word(dev, 0x4A, udma_timing);
 233
 234                 /* Select a 33/66/100Mhz clock */
 235                 pci_read_config_word(dev, 0x54, &ideconf);
 236                 ideconf &= ~(0x1001 << devid);
 237                 ideconf |= u_clock << devid;
 238                 pci_write_config_word(dev, 0x54, ideconf);
 239         } else {
 240                 /*
 241                  * MWDMA is driven by the PIO timings. We must also enable
 242                  * IORDY unconditionally along with TIME1. PPE has already
 243                  * been set when the PIO timing was set.
 244                  */
 245                 unsigned int mwdma      = adev->dma_mode - XFER_MW_DMA_0;
 246                 unsigned int control;
 247                 u8 slave_data;
 248                 const unsigned int needed_pio[3] = {
 249                         XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
 250                 };
 251                 int pio = needed_pio[mwdma] - XFER_PIO_0;
 252
 253                 control = 3;    /* IORDY|TIME1 */
 254
 255                 /* If the drive MWDMA is faster than it can do PIO then
 256                    we must force PIO into PIO0 */
 257
 258                 if (adev->pio_mode < needed_pio[mwdma])
 259                         /* Enable DMA timing only */
 260                         control |= 8;   /* PIO cycles in PIO0 */
 261
 262                 if (adev->devno) {      /* Slave */
 263                         master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
 264                         master_data |= control << 4;
 265                         pci_read_config_byte(dev, 0x44, &slave_data);
 266                         slave_data &= (ap->port_no ? 0x0f : 0xf0);
 267                         /* Load the matching timing */
 268                         slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
 269                         pci_write_config_byte(dev, 0x44, slave_data);
 270                 } else {        /* Master */
 271                         master_data &= 0xCCF4;  /* Mask out IORDY|TIME1|DMAONLY
 272                                                    and master timing bits */
 273                         master_data |= control;
 274                         master_data |=
 275                                 (timings[pio][0] << 12) |
 276                                 (timings[pio][1] << 8);
 277                 }
 278
 279                 udma_enable &= ~(1 << devid);
 280                 pci_write_config_word(dev, master_port, master_data);
 281         }
 282         pci_write_config_byte(dev, 0x48, udma_enable);
 283
 284         spin_unlock_irqrestore(&rdc_lock, flags);
 285 }
 286
 287 static struct ata_port_operations rdc_pata_ops = {
 288         .inherits               = &ata_bmdma32_port_ops,
 289         .cable_detect           = rdc_pata_cable_detect,
 290         .set_piomode            = rdc_set_piomode,
 291         .set_dmamode            = rdc_set_dmamode,
 292         .prereset               = rdc_pata_prereset,
 293 };
 294
 295 static const struct ata_port_info rdc_port_info = {
 296
 297         .flags          = ATA_FLAG_SLAVE_POSS,
 298         .pio_mask       = ATA_PIO4,
 299         .mwdma_mask     = ATA_MWDMA12_ONLY,
 300         .udma_mask      = ATA_UDMA5,
 301         .port_ops       = &rdc_pata_ops,
 302 };
 303
 304 static struct scsi_host_template rdc_sht = {
 305         ATA_BMDMA_SHT(DRV_NAME),
 306 };
 307
 308 /**
 309  *      rdc_init_one - Register PIIX ATA PCI device with kernel services
 310  *      @pdev: PCI device to register
 311  *      @ent: Entry in rdc_pci_tbl matching with @pdev
 312  *
 313  *      Called from kernel PCI layer.  We probe for combined mode (sigh),
 314  *      and then hand over control to libata, for it to do the rest.
 315  *
 316  *      LOCKING:
 317  *      Inherited from PCI layer (may sleep).
 318  *
 319  *      RETURNS:
 320  *      Zero on success, or -ERRNO value.
 321  */
 322
 323 static int rdc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 324 {
 325         struct device *dev = &pdev->dev;
 326         struct ata_port_info port_info[2];
 327         const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
 328         struct ata_host *host;
 329         struct rdc_host_priv *hpriv;
 330         int rc;
 331
 332         ata_print_version_once(&pdev->dev, DRV_VERSION);
 333
 334         port_info[0] = rdc_port_info;
 335         port_info[1] = rdc_port_info;
 336
 337         /* enable device and prepare host */
 338         rc = pcim_enable_device(pdev);
 339         if (rc)
 340                 return rc;
 341
 342         hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
 343         if (!hpriv)
 344                 return -ENOMEM;
 345
 346         /* Save IOCFG, this will be used for cable detection, quirk
 347          * detection and restoration on detach.
 348          */
 349         pci_read_config_dword(pdev, 0x54, &hpriv->saved_iocfg);
 350
 351         rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
 352         if (rc)
 353                 return rc;
 354         host->private_data = hpriv;
 355
 356         pci_intx(pdev, 1);
 357
 358         host->flags |= ATA_HOST_PARALLEL_SCAN;
 359
 360         pci_set_master(pdev);
 361         return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &rdc_sht);
 362 }
 363
 364 static void rdc_remove_one(struct pci_dev *pdev)
 365 {
 366         struct ata_host *host = pci_get_drvdata(pdev);
 367         struct rdc_host_priv *hpriv = host->private_data;
 368
 369         pci_write_config_dword(pdev, 0x54, hpriv->saved_iocfg);
 370
 371         ata_pci_remove_one(pdev);
 372 }
 373
 374 static const struct pci_device_id rdc_pci_tbl[] = {
 375         { PCI_DEVICE(0x17F3, 0x1011), },
 376         { PCI_DEVICE(0x17F3, 0x1012), },
 377         { }     /* terminate list */
 378 };
 379
 380 static struct pci_driver rdc_pci_driver = {
 381         .name                   = DRV_NAME,
 382         .id_table               = rdc_pci_tbl,
 383         .probe                  = rdc_init_one,
 384         .remove                 = rdc_remove_one,
 385 #ifdef CONFIG_PM_SLEEP
 386         .suspend                = ata_pci_device_suspend,
 387         .resume                 = ata_pci_device_resume,
 388 #endif
 389 };
 390
 391
 392 module_pci_driver(rdc_pci_driver);
 393
 394 MODULE_AUTHOR("Alan Cox (based on ata_piix)");
 395 MODULE_DESCRIPTION("SCSI low-level driver for RDC PATA controllers");
 396 MODULE_LICENSE("GPL");
 397 MODULE_DEVICE_TABLE(pci, rdc_pci_tbl);
 398 MODULE_VERSION(DRV_VERSION);