drivers/clk/at91/clk-pll.c

   1 /*
   2  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  */
  10
  11 #include <linux/clk-provider.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/clk/at91_pmc.h>
  14 #include <linux/of.h>
  15 #include <linux/mfd/syscon.h>
  16 #include <linux/regmap.h>
  17
  18 #include "pmc.h"
  19
  20 #define PLL_STATUS_MASK(id)     (1 << (1 + (id)))
  21 #define PLL_REG(id)             (AT91_CKGR_PLLAR + ((id) * 4))
  22 #define PLL_DIV_MASK            0xff
  23 #define PLL_DIV_MAX             PLL_DIV_MASK
  24 #define PLL_DIV(reg)            ((reg) & PLL_DIV_MASK)
  25 #define PLL_MUL(reg, layout)    (((reg) >> (layout)->mul_shift) & \
  26                                  (layout)->mul_mask)
  27 #define PLL_MUL_MIN             2
  28 #define PLL_MUL_MASK(layout)    ((layout)->mul_mask)
  29 #define PLL_MUL_MAX(layout)     (PLL_MUL_MASK(layout) + 1)
  30 #define PLL_ICPR_SHIFT(id)      ((id) * 16)
  31 #define PLL_ICPR_MASK(id)       (0xffff << PLL_ICPR_SHIFT(id))
  32 #define PLL_MAX_COUNT           0x3f
  33 #define PLL_COUNT_SHIFT         8
  34 #define PLL_OUT_SHIFT           14
  35 #define PLL_MAX_ID              1
  36
  37 struct clk_pll_characteristics {
  38         struct clk_range input;
  39         int num_output;
  40         struct clk_range *output;
  41         u16 *icpll;
  42         u8 *out;
  43 };
  44
  45 struct clk_pll_layout {
  46         u32 pllr_mask;
  47         u16 mul_mask;
  48         u8 mul_shift;
  49 };
  50
  51 #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
  52
  53 struct clk_pll {
  54         struct clk_hw hw;
  55         struct regmap *regmap;
  56         u8 id;
  57         u8 div;
  58         u8 range;
  59         u16 mul;
  60         const struct clk_pll_layout *layout;
  61         const struct clk_pll_characteristics *characteristics;
  62 };
  63
  64 static inline bool clk_pll_ready(struct regmap *regmap, int id)
  65 {
  66         unsigned int status;
  67
  68         regmap_read(regmap, AT91_PMC_SR, &status);
  69
  70         return status & PLL_STATUS_MASK(id) ? 1 : 0;
  71 }
  72
  73 static int clk_pll_prepare(struct clk_hw *hw)
  74 {
  75         struct clk_pll *pll = to_clk_pll(hw);
  76         struct regmap *regmap = pll->regmap;
  77         const struct clk_pll_layout *layout = pll->layout;
  78         const struct clk_pll_characteristics *characteristics =
  79                                                         pll->characteristics;
  80         u8 id = pll->id;
  81         u32 mask = PLL_STATUS_MASK(id);
  82         int offset = PLL_REG(id);
  83         u8 out = 0;
  84         unsigned int pllr;
  85         unsigned int status;
  86         u8 div;
  87         u16 mul;
  88
  89         regmap_read(regmap, offset, &pllr);
  90         div = PLL_DIV(pllr);
  91         mul = PLL_MUL(pllr, layout);
  92
  93         regmap_read(regmap, AT91_PMC_SR, &status);
  94         if ((status & mask) &&
  95             (div == pll->div && mul == pll->mul))
  96                 return 0;
  97
  98         if (characteristics->out)
  99                 out = characteristics->out[pll->range];
 100
 101         if (characteristics->icpll)
 102                 regmap_update_bits(regmap, AT91_PMC_PLLICPR, PLL_ICPR_MASK(id),
 103                         characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id));
 104
 105         regmap_update_bits(regmap, offset, layout->pllr_mask,
 106                         pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
 107                         (out << PLL_OUT_SHIFT) |
 108                         ((pll->mul & layout->mul_mask) << layout->mul_shift));
 109
 110         while (!clk_pll_ready(regmap, pll->id))
 111                 cpu_relax();
 112
 113         return 0;
 114 }
 115
 116 static int clk_pll_is_prepared(struct clk_hw *hw)
 117 {
 118         struct clk_pll *pll = to_clk_pll(hw);
 119
 120         return clk_pll_ready(pll->regmap, pll->id);
 121 }
 122
 123 static void clk_pll_unprepare(struct clk_hw *hw)
 124 {
 125         struct clk_pll *pll = to_clk_pll(hw);
 126         unsigned int mask = pll->layout->pllr_mask;
 127
 128         regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask);
 129 }
 130
 131 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 132                                          unsigned long parent_rate)
 133 {
 134         struct clk_pll *pll = to_clk_pll(hw);
 135         unsigned int pllr;
 136         u16 mul;
 137         u8 div;
 138
 139         regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
 140
 141         div = PLL_DIV(pllr);
 142         mul = PLL_MUL(pllr, pll->layout);
 143
 144         if (!div || !mul)
 145                 return 0;
 146
 147         return (parent_rate / div) * (mul + 1);
 148 }
 149
 150 static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
 151                                      unsigned long parent_rate,
 152                                      u32 *div, u32 *mul,
 153                                      u32 *index) {
 154         const struct clk_pll_layout *layout = pll->layout;
 155         const struct clk_pll_characteristics *characteristics =
 156                                                         pll->characteristics;
 157         unsigned long bestremainder = ULONG_MAX;
 158         unsigned long maxdiv, mindiv, tmpdiv;
 159         long bestrate = -ERANGE;
 160         unsigned long bestdiv;
 161         unsigned long bestmul;
 162         int i = 0;
 163
 164         /* Check if parent_rate is a valid input rate */
 165         if (parent_rate < characteristics->input.min)
 166                 return -ERANGE;
 167
 168         /*
 169          * Calculate minimum divider based on the minimum multiplier, the
 170          * parent_rate and the requested rate.
 171          * Should always be 2 according to the input and output characteristics
 172          * of the PLL blocks.
 173          */
 174         mindiv = (parent_rate * PLL_MUL_MIN) / rate;
 175         if (!mindiv)
 176                 mindiv = 1;
 177
 178         if (parent_rate > characteristics->input.max) {
 179                 tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
 180                 if (tmpdiv > PLL_DIV_MAX)
 181                         return -ERANGE;
 182
 183                 if (tmpdiv > mindiv)
 184                         mindiv = tmpdiv;
 185         }
 186
 187         /*
 188          * Calculate the maximum divider which is limited by PLL register
 189          * layout (limited by the MUL or DIV field size).
 190          */
 191         maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate);
 192         if (maxdiv > PLL_DIV_MAX)
 193                 maxdiv = PLL_DIV_MAX;
 194
 195         /*
 196          * Iterate over the acceptable divider values to find the best
 197          * divider/multiplier pair (the one that generates the closest
 198          * rate to the requested one).
 199          */
 200         for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
 201                 unsigned long remainder;
 202                 unsigned long tmprate;
 203                 unsigned long tmpmul;
 204
 205                 /*
 206                  * Calculate the multiplier associated with the current
 207                  * divider that provide the closest rate to the requested one.
 208                  */
 209                 tmpmul = DIV_ROUND_CLOSEST(rate, parent_rate / tmpdiv);
 210                 tmprate = (parent_rate / tmpdiv) * tmpmul;
 211                 if (tmprate > rate)
 212                         remainder = tmprate - rate;
 213                 else
 214                         remainder = rate - tmprate;
 215
 216                 /*
 217                  * Compare the remainder with the best remainder found until
 218                  * now and elect a new best multiplier/divider pair if the
 219                  * current remainder is smaller than the best one.
 220                  */
 221                 if (remainder < bestremainder) {
 222                         bestremainder = remainder;
 223                         bestdiv = tmpdiv;
 224                         bestmul = tmpmul;
 225                         bestrate = tmprate;
 226                 }
 227
 228                 /*
 229                  * We've found a perfect match!
 230                  * Stop searching now and use this multiplier/divider pair.
 231                  */
 232                 if (!remainder)
 233                         break;
 234         }
 235
 236         /* We haven't found any multiplier/divider pair => return -ERANGE */
 237         if (bestrate < 0)
 238                 return bestrate;
 239
 240         /* Check if bestrate is a valid output rate  */
 241         for (i = 0; i < characteristics->num_output; i++) {
 242                 if (bestrate >= characteristics->output[i].min &&
 243                     bestrate <= characteristics->output[i].max)
 244                         break;
 245         }
 246
 247         if (i >= characteristics->num_output)
 248                 return -ERANGE;
 249
 250         if (div)
 251                 *div = bestdiv;
 252         if (mul)
 253                 *mul = bestmul - 1;
 254         if (index)
 255                 *index = i;
 256
 257         return bestrate;
 258 }
 259
 260 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 261                                         unsigned long *parent_rate)
 262 {
 263         struct clk_pll *pll = to_clk_pll(hw);
 264
 265         return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
 266                                         NULL, NULL, NULL);
 267 }
 268
 269 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 270                             unsigned long parent_rate)
 271 {
 272         struct clk_pll *pll = to_clk_pll(hw);
 273         long ret;
 274         u32 div;
 275         u32 mul;
 276         u32 index;
 277
 278         ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
 279                                        &div, &mul, &index);
 280         if (ret < 0)
 281                 return ret;
 282
 283         pll->range = index;
 284         pll->div = div;
 285         pll->mul = mul;
 286
 287         return 0;
 288 }
 289
 290 static const struct clk_ops pll_ops = {
 291         .prepare = clk_pll_prepare,
 292         .unprepare = clk_pll_unprepare,
 293         .is_prepared = clk_pll_is_prepared,
 294         .recalc_rate = clk_pll_recalc_rate,
 295         .round_rate = clk_pll_round_rate,
 296         .set_rate = clk_pll_set_rate,
 297 };
 298
 299 static struct clk_hw * __init
 300 at91_clk_register_pll(struct regmap *regmap, const char *name,
 301                       const char *parent_name, u8 id,
 302                       const struct clk_pll_layout *layout,
 303                       const struct clk_pll_characteristics *characteristics)
 304 {
 305         struct clk_pll *pll;
 306         struct clk_hw *hw;
 307         struct clk_init_data init;
 308         int offset = PLL_REG(id);
 309         unsigned int pllr;
 310         int ret;
 311
 312         if (id > PLL_MAX_ID)
 313                 return ERR_PTR(-EINVAL);
 314
 315         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 316         if (!pll)
 317                 return ERR_PTR(-ENOMEM);
 318
 319         init.name = name;
 320         init.ops = &pll_ops;
 321         init.parent_names = &parent_name;
 322         init.num_parents = 1;
 323         init.flags = CLK_SET_RATE_GATE;
 324
 325         pll->id = id;
 326         pll->hw.init = &init;
 327         pll->layout = layout;
 328         pll->characteristics = characteristics;
 329         pll->regmap = regmap;
 330         regmap_read(regmap, offset, &pllr);
 331         pll->div = PLL_DIV(pllr);
 332         pll->mul = PLL_MUL(pllr, layout);
 333
 334         hw = &pll->hw;
 335         ret = clk_hw_register(NULL, &pll->hw);
 336         if (ret) {
 337                 kfree(pll);
 338                 hw = ERR_PTR(ret);
 339         }
 340
 341         return hw;
 342 }
 343
 344
 345 static const struct clk_pll_layout at91rm9200_pll_layout = {
 346         .pllr_mask = 0x7FFFFFF,
 347         .mul_shift = 16,
 348         .mul_mask = 0x7FF,
 349 };
 350
 351 static const struct clk_pll_layout at91sam9g45_pll_layout = {
 352         .pllr_mask = 0xFFFFFF,
 353         .mul_shift = 16,
 354         .mul_mask = 0xFF,
 355 };
 356
 357 static const struct clk_pll_layout at91sam9g20_pllb_layout = {
 358         .pllr_mask = 0x3FFFFF,
 359         .mul_shift = 16,
 360         .mul_mask = 0x3F,
 361 };
 362
 363 static const struct clk_pll_layout sama5d3_pll_layout = {
 364         .pllr_mask = 0x1FFFFFF,
 365         .mul_shift = 18,
 366         .mul_mask = 0x7F,
 367 };
 368
 369
 370 static struct clk_pll_characteristics * __init
 371 of_at91_clk_pll_get_characteristics(struct device_node *np)
 372 {
 373         int i;
 374         int offset;
 375         u32 tmp;
 376         int num_output;
 377         u32 num_cells;
 378         struct clk_range input;
 379         struct clk_range *output;
 380         u8 *out = NULL;
 381         u16 *icpll = NULL;
 382         struct clk_pll_characteristics *characteristics;
 383
 384         if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
 385                 return NULL;
 386
 387         if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
 388                                  &num_cells))
 389                 return NULL;
 390
 391         if (num_cells < 2 || num_cells > 4)
 392                 return NULL;
 393
 394         if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
 395                 return NULL;
 396         num_output = tmp / (sizeof(u32) * num_cells);
 397
 398         characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
 399         if (!characteristics)
 400                 return NULL;
 401
 402         output = kcalloc(num_output, sizeof(*output), GFP_KERNEL);
 403         if (!output)
 404                 goto out_free_characteristics;
 405
 406         if (num_cells > 2) {
 407                 out = kcalloc(num_output, sizeof(*out), GFP_KERNEL);
 408                 if (!out)
 409                         goto out_free_output;
 410         }
 411
 412         if (num_cells > 3) {
 413                 icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL);
 414                 if (!icpll)
 415                         goto out_free_output;
 416         }
 417
 418         for (i = 0; i < num_output; i++) {
 419                 offset = i * num_cells;
 420                 if (of_property_read_u32_index(np,
 421                                                "atmel,pll-clk-output-ranges",
 422                                                offset, &tmp))
 423                         goto out_free_output;
 424                 output[i].min = tmp;
 425                 if (of_property_read_u32_index(np,
 426                                                "atmel,pll-clk-output-ranges",
 427                                                offset + 1, &tmp))
 428                         goto out_free_output;
 429                 output[i].max = tmp;
 430
 431                 if (num_cells == 2)
 432                         continue;
 433
 434                 if (of_property_read_u32_index(np,
 435                                                "atmel,pll-clk-output-ranges",
 436                                                offset + 2, &tmp))
 437                         goto out_free_output;
 438                 out[i] = tmp;
 439
 440                 if (num_cells == 3)
 441                         continue;
 442
 443                 if (of_property_read_u32_index(np,
 444                                                "atmel,pll-clk-output-ranges",
 445                                                offset + 3, &tmp))
 446                         goto out_free_output;
 447                 icpll[i] = tmp;
 448         }
 449
 450         characteristics->input = input;
 451         characteristics->num_output = num_output;
 452         characteristics->output = output;
 453         characteristics->out = out;
 454         characteristics->icpll = icpll;
 455         return characteristics;
 456
 457 out_free_output:
 458         kfree(icpll);
 459         kfree(out);
 460         kfree(output);
 461 out_free_characteristics:
 462         kfree(characteristics);
 463         return NULL;
 464 }
 465
 466 static void __init
 467 of_at91_clk_pll_setup(struct device_node *np,
 468                       const struct clk_pll_layout *layout)
 469 {
 470         u32 id;
 471         struct clk_hw *hw;
 472         struct regmap *regmap;
 473         const char *parent_name;
 474         const char *name = np->name;
 475         struct clk_pll_characteristics *characteristics;
 476
 477         if (of_property_read_u32(np, "reg", &id))
 478                 return;
 479
 480         parent_name = of_clk_get_parent_name(np, 0);
 481
 482         of_property_read_string(np, "clock-output-names", &name);
 483
 484         regmap = syscon_node_to_regmap(of_get_parent(np));
 485         if (IS_ERR(regmap))
 486                 return;
 487
 488         characteristics = of_at91_clk_pll_get_characteristics(np);
 489         if (!characteristics)
 490                 return;
 491
 492         hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
 493                                     characteristics);
 494         if (IS_ERR(hw))
 495                 goto out_free_characteristics;
 496
 497         of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
 498         return;
 499
 500 out_free_characteristics:
 501         kfree(characteristics);
 502 }
 503
 504 static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
 505 {
 506         of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
 507 }
 508 CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
 509                of_at91rm9200_clk_pll_setup);
 510
 511 static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
 512 {
 513         of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
 514 }
 515 CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
 516                of_at91sam9g45_clk_pll_setup);
 517
 518 static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
 519 {
 520         of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
 521 }
 522 CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
 523                of_at91sam9g20_clk_pllb_setup);
 524
 525 static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
 526 {
 527         of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
 528 }
 529 CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
 530                of_sama5d3_clk_pll_setup);