drivers/clk/clk-divider.c

   1 /*
   2  * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   3  * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
   4  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Adjustable divider clock implementation
  11  */
  12
  13 #include <linux/clk-provider.h>
  14 #include <linux/module.h>
  15 #include <linux/slab.h>
  16 #include <linux/io.h>
  17 #include <linux/err.h>
  18 #include <linux/string.h>
  19 #include <linux/log2.h>
  20
  21 /*
  22  * DOC: basic adjustable divider clock that cannot gate
  23  *
  24  * Traits of this clock:
  25  * prepare - clk_prepare only ensures that parents are prepared
  26  * enable - clk_enable only ensures that parents are enabled
  27  * rate - rate is adjustable.  clk->rate = ceiling(parent->rate / divisor)
  28  * parent - fixed parent.  No clk_set_parent support
  29  */
  30
  31 #define div_mask(width) ((1 << (width)) - 1)
  32
  33 static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
  34                                       u8 width)
  35 {
  36         unsigned int maxdiv = 0, mask = div_mask(width);
  37         const struct clk_div_table *clkt;
  38
  39         for (clkt = table; clkt->div; clkt++)
  40                 if (clkt->div > maxdiv && clkt->val <= mask)
  41                         maxdiv = clkt->div;
  42         return maxdiv;
  43 }
  44
  45 static unsigned int _get_table_mindiv(const struct clk_div_table *table)
  46 {
  47         unsigned int mindiv = UINT_MAX;
  48         const struct clk_div_table *clkt;
  49
  50         for (clkt = table; clkt->div; clkt++)
  51                 if (clkt->div < mindiv)
  52                         mindiv = clkt->div;
  53         return mindiv;
  54 }
  55
  56 static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
  57                                 unsigned long flags)
  58 {
  59         if (flags & CLK_DIVIDER_ONE_BASED)
  60                 return div_mask(width);
  61         if (flags & CLK_DIVIDER_POWER_OF_TWO)
  62                 return 1 << div_mask(width);
  63         if (table)
  64                 return _get_table_maxdiv(table, width);
  65         return div_mask(width) + 1;
  66 }
  67
  68 static unsigned int _get_table_div(const struct clk_div_table *table,
  69                                                         unsigned int val)
  70 {
  71         const struct clk_div_table *clkt;
  72
  73         for (clkt = table; clkt->div; clkt++)
  74                 if (clkt->val == val)
  75                         return clkt->div;
  76         return 0;
  77 }
  78
  79 static unsigned int _get_div(const struct clk_div_table *table,
  80                              unsigned int val, unsigned long flags, u8 width)
  81 {
  82         if (flags & CLK_DIVIDER_ONE_BASED)
  83                 return val;
  84         if (flags & CLK_DIVIDER_POWER_OF_TWO)
  85                 return 1 << val;
  86         if (flags & CLK_DIVIDER_MAX_AT_ZERO)
  87                 return val ? val : div_mask(width) + 1;
  88         if (table)
  89                 return _get_table_div(table, val);
  90         return val + 1;
  91 }
  92
  93 static unsigned int _get_table_val(const struct clk_div_table *table,
  94                                                         unsigned int div)
  95 {
  96         const struct clk_div_table *clkt;
  97
  98         for (clkt = table; clkt->div; clkt++)
  99                 if (clkt->div == div)
 100                         return clkt->val;
 101         return 0;
 102 }
 103
 104 static unsigned int _get_val(const struct clk_div_table *table,
 105                              unsigned int div, unsigned long flags, u8 width)
 106 {
 107         if (flags & CLK_DIVIDER_ONE_BASED)
 108                 return div;
 109         if (flags & CLK_DIVIDER_POWER_OF_TWO)
 110                 return __ffs(div);
 111         if (flags & CLK_DIVIDER_MAX_AT_ZERO)
 112                 return (div == div_mask(width) + 1) ? 0 : div;
 113         if (table)
 114                 return  _get_table_val(table, div);
 115         return div - 1;
 116 }
 117
 118 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
 119                                   unsigned int val,
 120                                   const struct clk_div_table *table,
 121                                   unsigned long flags, unsigned long width)
 122 {
 123         unsigned int div;
 124
 125         div = _get_div(table, val, flags, width);
 126         if (!div) {
 127                 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
 128                         "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
 129                         clk_hw_get_name(hw));
 130                 return parent_rate;
 131         }
 132
 133         return DIV_ROUND_UP_ULL((u64)parent_rate, div);
 134 }
 135 EXPORT_SYMBOL_GPL(divider_recalc_rate);
 136
 137 static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
 138                 unsigned long parent_rate)
 139 {
 140         struct clk_divider *divider = to_clk_divider(hw);
 141         unsigned int val;
 142
 143         val = clk_readl(divider->reg) >> divider->shift;
 144         val &= div_mask(divider->width);
 145
 146         return divider_recalc_rate(hw, parent_rate, val, divider->table,
 147                                    divider->flags, divider->width);
 148 }
 149
 150 static bool _is_valid_table_div(const struct clk_div_table *table,
 151                                                          unsigned int div)
 152 {
 153         const struct clk_div_table *clkt;
 154
 155         for (clkt = table; clkt->div; clkt++)
 156                 if (clkt->div == div)
 157                         return true;
 158         return false;
 159 }
 160
 161 static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
 162                           unsigned long flags)
 163 {
 164         if (flags & CLK_DIVIDER_POWER_OF_TWO)
 165                 return is_power_of_2(div);
 166         if (table)
 167                 return _is_valid_table_div(table, div);
 168         return true;
 169 }
 170
 171 static int _round_up_table(const struct clk_div_table *table, int div)
 172 {
 173         const struct clk_div_table *clkt;
 174         int up = INT_MAX;
 175
 176         for (clkt = table; clkt->div; clkt++) {
 177                 if (clkt->div == div)
 178                         return clkt->div;
 179                 else if (clkt->div < div)
 180                         continue;
 181
 182                 if ((clkt->div - div) < (up - div))
 183                         up = clkt->div;
 184         }
 185
 186         return up;
 187 }
 188
 189 static int _round_down_table(const struct clk_div_table *table, int div)
 190 {
 191         const struct clk_div_table *clkt;
 192         int down = _get_table_mindiv(table);
 193
 194         for (clkt = table; clkt->div; clkt++) {
 195                 if (clkt->div == div)
 196                         return clkt->div;
 197                 else if (clkt->div > div)
 198                         continue;
 199
 200                 if ((div - clkt->div) < (div - down))
 201                         down = clkt->div;
 202         }
 203
 204         return down;
 205 }
 206
 207 static int _div_round_up(const struct clk_div_table *table,
 208                          unsigned long parent_rate, unsigned long rate,
 209                          unsigned long flags)
 210 {
 211         int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
 212
 213         if (flags & CLK_DIVIDER_POWER_OF_TWO)
 214                 div = __roundup_pow_of_two(div);
 215         if (table)
 216                 div = _round_up_table(table, div);
 217
 218         return div;
 219 }
 220
 221 static int _div_round_closest(const struct clk_div_table *table,
 222                               unsigned long parent_rate, unsigned long rate,
 223                               unsigned long flags)
 224 {
 225         int up, down;
 226         unsigned long up_rate, down_rate;
 227
 228         up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
 229         down = parent_rate / rate;
 230
 231         if (flags & CLK_DIVIDER_POWER_OF_TWO) {
 232                 up = __roundup_pow_of_two(up);
 233                 down = __rounddown_pow_of_two(down);
 234         } else if (table) {
 235                 up = _round_up_table(table, up);
 236                 down = _round_down_table(table, down);
 237         }
 238
 239         up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
 240         down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
 241
 242         return (rate - up_rate) <= (down_rate - rate) ? up : down;
 243 }
 244
 245 static int _div_round(const struct clk_div_table *table,
 246                       unsigned long parent_rate, unsigned long rate,
 247                       unsigned long flags)
 248 {
 249         if (flags & CLK_DIVIDER_ROUND_CLOSEST)
 250                 return _div_round_closest(table, parent_rate, rate, flags);
 251
 252         return _div_round_up(table, parent_rate, rate, flags);
 253 }
 254
 255 static bool _is_best_div(unsigned long rate, unsigned long now,
 256                          unsigned long best, unsigned long flags)
 257 {
 258         if (flags & CLK_DIVIDER_ROUND_CLOSEST)
 259                 return abs(rate - now) < abs(rate - best);
 260
 261         return now <= rate && now > best;
 262 }
 263
 264 static int _next_div(const struct clk_div_table *table, int div,
 265                      unsigned long flags)
 266 {
 267         div++;
 268
 269         if (flags & CLK_DIVIDER_POWER_OF_TWO)
 270                 return __roundup_pow_of_two(div);
 271         if (table)
 272                 return _round_up_table(table, div);
 273
 274         return div;
 275 }
 276
 277 static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
 278                                unsigned long rate,
 279                                unsigned long *best_parent_rate,
 280                                const struct clk_div_table *table, u8 width,
 281                                unsigned long flags)
 282 {
 283         int i, bestdiv = 0;
 284         unsigned long parent_rate, best = 0, now, maxdiv;
 285         unsigned long parent_rate_saved = *best_parent_rate;
 286
 287         if (!rate)
 288                 rate = 1;
 289
 290         maxdiv = _get_maxdiv(table, width, flags);
 291
 292         if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
 293                 parent_rate = *best_parent_rate;
 294                 bestdiv = _div_round(table, parent_rate, rate, flags);
 295                 bestdiv = bestdiv == 0 ? 1 : bestdiv;
 296                 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
 297                 return bestdiv;
 298         }
 299
 300         /*
 301          * The maximum divider we can use without overflowing
 302          * unsigned long in rate * i below
 303          */
 304         maxdiv = min(ULONG_MAX / rate, maxdiv);
 305
 306         for (i = _next_div(table, 0, flags); i <= maxdiv;
 307                                              i = _next_div(table, i, flags)) {
 308                 if (rate * i == parent_rate_saved) {
 309                         /*
 310                          * It's the most ideal case if the requested rate can be
 311                          * divided from parent clock without needing to change
 312                          * parent rate, so return the divider immediately.
 313                          */
 314                         *best_parent_rate = parent_rate_saved;
 315                         return i;
 316                 }
 317                 parent_rate = clk_hw_round_rate(parent, rate * i);
 318                 now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
 319                 if (_is_best_div(rate, now, best, flags)) {
 320                         bestdiv = i;
 321                         best = now;
 322                         *best_parent_rate = parent_rate;
 323                 }
 324         }
 325
 326         if (!bestdiv) {
 327                 bestdiv = _get_maxdiv(table, width, flags);
 328                 *best_parent_rate = clk_hw_round_rate(parent, 1);
 329         }
 330
 331         return bestdiv;
 332 }
 333
 334 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
 335                                unsigned long rate, unsigned long *prate,
 336                                const struct clk_div_table *table,
 337                                u8 width, unsigned long flags)
 338 {
 339         int div;
 340
 341         div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags);
 342
 343         return DIV_ROUND_UP_ULL((u64)*prate, div);
 344 }
 345 EXPORT_SYMBOL_GPL(divider_round_rate_parent);
 346
 347 static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
 348                                 unsigned long *prate)
 349 {
 350         struct clk_divider *divider = to_clk_divider(hw);
 351         int bestdiv;
 352
 353         /* if read only, just return current value */
 354         if (divider->flags & CLK_DIVIDER_READ_ONLY) {
 355                 bestdiv = clk_readl(divider->reg) >> divider->shift;
 356                 bestdiv &= div_mask(divider->width);
 357                 bestdiv = _get_div(divider->table, bestdiv, divider->flags,
 358                         divider->width);
 359                 return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
 360         }
 361
 362         return divider_round_rate(hw, rate, prate, divider->table,
 363                                   divider->width, divider->flags);
 364 }
 365
 366 int divider_get_val(unsigned long rate, unsigned long parent_rate,
 367                     const struct clk_div_table *table, u8 width,
 368                     unsigned long flags)
 369 {
 370         unsigned int div, value;
 371
 372         div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
 373
 374         if (!_is_valid_div(table, div, flags))
 375                 return -EINVAL;
 376
 377         value = _get_val(table, div, flags, width);
 378
 379         return min_t(unsigned int, value, div_mask(width));
 380 }
 381 EXPORT_SYMBOL_GPL(divider_get_val);
 382
 383 static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 384                                 unsigned long parent_rate)
 385 {
 386         struct clk_divider *divider = to_clk_divider(hw);
 387         int value;
 388         unsigned long flags = 0;
 389         u32 val;
 390
 391         value = divider_get_val(rate, parent_rate, divider->table,
 392                                 divider->width, divider->flags);
 393         if (value < 0)
 394                 return value;
 395
 396         if (divider->lock)
 397                 spin_lock_irqsave(divider->lock, flags);
 398         else
 399                 __acquire(divider->lock);
 400
 401         if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
 402                 val = div_mask(divider->width) << (divider->shift + 16);
 403         } else {
 404                 val = clk_readl(divider->reg);
 405                 val &= ~(div_mask(divider->width) << divider->shift);
 406         }
 407         val |= (u32)value << divider->shift;
 408         clk_writel(val, divider->reg);
 409
 410         if (divider->lock)
 411                 spin_unlock_irqrestore(divider->lock, flags);
 412         else
 413                 __release(divider->lock);
 414
 415         return 0;
 416 }
 417
 418 const struct clk_ops clk_divider_ops = {
 419         .recalc_rate = clk_divider_recalc_rate,
 420         .round_rate = clk_divider_round_rate,
 421         .set_rate = clk_divider_set_rate,
 422 };
 423 EXPORT_SYMBOL_GPL(clk_divider_ops);
 424
 425 const struct clk_ops clk_divider_ro_ops = {
 426         .recalc_rate = clk_divider_recalc_rate,
 427         .round_rate = clk_divider_round_rate,
 428 };
 429 EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
 430
 431 static struct clk_hw *_register_divider(struct device *dev, const char *name,
 432                 const char *parent_name, unsigned long flags,
 433                 void __iomem *reg, u8 shift, u8 width,
 434                 u8 clk_divider_flags, const struct clk_div_table *table,
 435                 spinlock_t *lock)
 436 {
 437         struct clk_divider *div;
 438         struct clk_hw *hw;
 439         struct clk_init_data init;
 440         int ret;
 441
 442         if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
 443                 if (width + shift > 16) {
 444                         pr_warn("divider value exceeds LOWORD field\n");
 445                         return ERR_PTR(-EINVAL);
 446                 }
 447         }
 448
 449         /* allocate the divider */
 450         div = kzalloc(sizeof(*div), GFP_KERNEL);
 451         if (!div)
 452                 return ERR_PTR(-ENOMEM);
 453
 454         init.name = name;
 455         if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
 456                 init.ops = &clk_divider_ro_ops;
 457         else
 458                 init.ops = &clk_divider_ops;
 459         init.flags = flags | CLK_IS_BASIC;
 460         init.parent_names = (parent_name ? &parent_name: NULL);
 461         init.num_parents = (parent_name ? 1 : 0);
 462
 463         /* struct clk_divider assignments */
 464         div->reg = reg;
 465         div->shift = shift;
 466         div->width = width;
 467         div->flags = clk_divider_flags;
 468         div->lock = lock;
 469         div->hw.init = &init;
 470         div->table = table;
 471
 472         /* register the clock */
 473         hw = &div->hw;
 474         ret = clk_hw_register(dev, hw);
 475         if (ret) {
 476                 kfree(div);
 477                 hw = ERR_PTR(ret);
 478         }
 479
 480         return hw;
 481 }
 482
 483 /**
 484  * clk_register_divider - register a divider clock with the clock framework
 485  * @dev: device registering this clock
 486  * @name: name of this clock
 487  * @parent_name: name of clock's parent
 488  * @flags: framework-specific flags
 489  * @reg: register address to adjust divider
 490  * @shift: number of bits to shift the bitfield
 491  * @width: width of the bitfield
 492  * @clk_divider_flags: divider-specific flags for this clock
 493  * @lock: shared register lock for this clock
 494  */
 495 struct clk *clk_register_divider(struct device *dev, const char *name,
 496                 const char *parent_name, unsigned long flags,
 497                 void __iomem *reg, u8 shift, u8 width,
 498                 u8 clk_divider_flags, spinlock_t *lock)
 499 {
 500         struct clk_hw *hw;
 501
 502         hw =  _register_divider(dev, name, parent_name, flags, reg, shift,
 503                         width, clk_divider_flags, NULL, lock);
 504         if (IS_ERR(hw))
 505                 return ERR_CAST(hw);
 506         return hw->clk;
 507 }
 508 EXPORT_SYMBOL_GPL(clk_register_divider);
 509
 510 /**
 511  * clk_hw_register_divider - register a divider clock with the clock framework
 512  * @dev: device registering this clock
 513  * @name: name of this clock
 514  * @parent_name: name of clock's parent
 515  * @flags: framework-specific flags
 516  * @reg: register address to adjust divider
 517  * @shift: number of bits to shift the bitfield
 518  * @width: width of the bitfield
 519  * @clk_divider_flags: divider-specific flags for this clock
 520  * @lock: shared register lock for this clock
 521  */
 522 struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
 523                 const char *parent_name, unsigned long flags,
 524                 void __iomem *reg, u8 shift, u8 width,
 525                 u8 clk_divider_flags, spinlock_t *lock)
 526 {
 527         return _register_divider(dev, name, parent_name, flags, reg, shift,
 528                         width, clk_divider_flags, NULL, lock);
 529 }
 530 EXPORT_SYMBOL_GPL(clk_hw_register_divider);
 531
 532 /**
 533  * clk_register_divider_table - register a table based divider clock with
 534  * the clock framework
 535  * @dev: device registering this clock
 536  * @name: name of this clock
 537  * @parent_name: name of clock's parent
 538  * @flags: framework-specific flags
 539  * @reg: register address to adjust divider
 540  * @shift: number of bits to shift the bitfield
 541  * @width: width of the bitfield
 542  * @clk_divider_flags: divider-specific flags for this clock
 543  * @table: array of divider/value pairs ending with a div set to 0
 544  * @lock: shared register lock for this clock
 545  */
 546 struct clk *clk_register_divider_table(struct device *dev, const char *name,
 547                 const char *parent_name, unsigned long flags,
 548                 void __iomem *reg, u8 shift, u8 width,
 549                 u8 clk_divider_flags, const struct clk_div_table *table,
 550                 spinlock_t *lock)
 551 {
 552         struct clk_hw *hw;
 553
 554         hw =  _register_divider(dev, name, parent_name, flags, reg, shift,
 555                         width, clk_divider_flags, table, lock);
 556         if (IS_ERR(hw))
 557                 return ERR_CAST(hw);
 558         return hw->clk;
 559 }
 560 EXPORT_SYMBOL_GPL(clk_register_divider_table);
 561
 562 /**
 563  * clk_hw_register_divider_table - register a table based divider clock with
 564  * the clock framework
 565  * @dev: device registering this clock
 566  * @name: name of this clock
 567  * @parent_name: name of clock's parent
 568  * @flags: framework-specific flags
 569  * @reg: register address to adjust divider
 570  * @shift: number of bits to shift the bitfield
 571  * @width: width of the bitfield
 572  * @clk_divider_flags: divider-specific flags for this clock
 573  * @table: array of divider/value pairs ending with a div set to 0
 574  * @lock: shared register lock for this clock
 575  */
 576 struct clk_hw *clk_hw_register_divider_table(struct device *dev,
 577                 const char *name, const char *parent_name, unsigned long flags,
 578                 void __iomem *reg, u8 shift, u8 width,
 579                 u8 clk_divider_flags, const struct clk_div_table *table,
 580                 spinlock_t *lock)
 581 {
 582         return _register_divider(dev, name, parent_name, flags, reg, shift,
 583                         width, clk_divider_flags, table, lock);
 584 }
 585 EXPORT_SYMBOL_GPL(clk_hw_register_divider_table);
 586
 587 void clk_unregister_divider(struct clk *clk)
 588 {
 589         struct clk_divider *div;
 590         struct clk_hw *hw;
 591
 592         hw = __clk_get_hw(clk);
 593         if (!hw)
 594                 return;
 595
 596         div = to_clk_divider(hw);
 597
 598         clk_unregister(clk);
 599         kfree(div);
 600 }
 601 EXPORT_SYMBOL_GPL(clk_unregister_divider);
 602
 603 /**
 604  * clk_hw_unregister_divider - unregister a clk divider
 605  * @hw: hardware-specific clock data to unregister
 606  */
 607 void clk_hw_unregister_divider(struct clk_hw *hw)
 608 {
 609         struct clk_divider *div;
 610
 611         div = to_clk_divider(hw);
 612
 613         clk_hw_unregister(hw);
 614         kfree(div);
 615 }
 616 EXPORT_SYMBOL_GPL(clk_hw_unregister_divider);