2 * Hisilicon clock separated gate driver
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
26 #include <linux/kernel.h>
27 #include <linux/clk-provider.h>
29 #include <linux/slab.h>
33 /* clock separated gate register offset */
34 #define CLKGATE_SEPERATED_ENABLE 0x0
35 #define CLKGATE_SEPERATED_DISABLE 0x4
36 #define CLKGATE_SEPERATED_STATUS 0x8
38 struct clkgate_separated
{
40 void __iomem
*enable
; /* enable register */
41 u8 bit_idx
; /* bits in enable/disable register */
46 static int clkgate_separated_enable(struct clk_hw
*hw
)
48 struct clkgate_separated
*sclk
;
49 unsigned long flags
= 0;
52 sclk
= container_of(hw
, struct clkgate_separated
, hw
);
54 spin_lock_irqsave(sclk
->lock
, flags
);
55 reg
= BIT(sclk
->bit_idx
);
56 writel_relaxed(reg
, sclk
->enable
);
57 readl_relaxed(sclk
->enable
+ CLKGATE_SEPERATED_STATUS
);
59 spin_unlock_irqrestore(sclk
->lock
, flags
);
63 static void clkgate_separated_disable(struct clk_hw
*hw
)
65 struct clkgate_separated
*sclk
;
66 unsigned long flags
= 0;
69 sclk
= container_of(hw
, struct clkgate_separated
, hw
);
71 spin_lock_irqsave(sclk
->lock
, flags
);
72 reg
= BIT(sclk
->bit_idx
);
73 writel_relaxed(reg
, sclk
->enable
+ CLKGATE_SEPERATED_DISABLE
);
74 readl_relaxed(sclk
->enable
+ CLKGATE_SEPERATED_STATUS
);
76 spin_unlock_irqrestore(sclk
->lock
, flags
);
79 static int clkgate_separated_is_enabled(struct clk_hw
*hw
)
81 struct clkgate_separated
*sclk
;
84 sclk
= container_of(hw
, struct clkgate_separated
, hw
);
85 reg
= readl_relaxed(sclk
->enable
+ CLKGATE_SEPERATED_STATUS
);
86 reg
&= BIT(sclk
->bit_idx
);
91 static const struct clk_ops clkgate_separated_ops
= {
92 .enable
= clkgate_separated_enable
,
93 .disable
= clkgate_separated_disable
,
94 .is_enabled
= clkgate_separated_is_enabled
,
97 struct clk
*hisi_register_clkgate_sep(struct device
*dev
, const char *name
,
98 const char *parent_name
,
100 void __iomem
*reg
, u8 bit_idx
,
101 u8 clk_gate_flags
, spinlock_t
*lock
)
103 struct clkgate_separated
*sclk
;
105 struct clk_init_data init
;
107 sclk
= kzalloc(sizeof(*sclk
), GFP_KERNEL
);
109 return ERR_PTR(-ENOMEM
);
112 init
.ops
= &clkgate_separated_ops
;
113 init
.flags
= flags
| CLK_IS_BASIC
;
114 init
.parent_names
= (parent_name
? &parent_name
: NULL
);
115 init
.num_parents
= (parent_name
? 1 : 0);
117 sclk
->enable
= reg
+ CLKGATE_SEPERATED_ENABLE
;
118 sclk
->bit_idx
= bit_idx
;
119 sclk
->flags
= clk_gate_flags
;
120 sclk
->hw
.init
= &init
;
123 clk
= clk_register(dev
, &sclk
->hw
);