drivers/clk/imx/clk.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __MACH_IMX_CLK_H
   3 #define __MACH_IMX_CLK_H
   4
   5 #include <linux/spinlock.h>
   6 #include <linux/clk-provider.h>
   7
   8 extern spinlock_t imx_ccm_lock;
   9
  10 void imx_check_clocks(struct clk *clks[], unsigned int count);
  11 void imx_register_uart_clocks(struct clk ** const clks[]);
  12
  13 extern void imx_cscmr1_fixup(u32 *val);
  14
  15 enum imx_pllv1_type {
  16         IMX_PLLV1_IMX1,
  17         IMX_PLLV1_IMX21,
  18         IMX_PLLV1_IMX25,
  19         IMX_PLLV1_IMX27,
  20         IMX_PLLV1_IMX31,
  21         IMX_PLLV1_IMX35,
  22 };
  23
  24 struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
  25                 const char *parent, void __iomem *base);
  26
  27 struct clk *imx_clk_pllv2(const char *name, const char *parent,
  28                 void __iomem *base);
  29
  30 enum imx_pllv3_type {
  31         IMX_PLLV3_GENERIC,
  32         IMX_PLLV3_SYS,
  33         IMX_PLLV3_USB,
  34         IMX_PLLV3_USB_VF610,
  35         IMX_PLLV3_AV,
  36         IMX_PLLV3_ENET,
  37         IMX_PLLV3_ENET_IMX7,
  38         IMX_PLLV3_SYS_VF610,
  39         IMX_PLLV3_DDR_IMX7,
  40 };
  41
  42 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
  43                 const char *parent_name, void __iomem *base, u32 div_mask);
  44
  45 struct clk *clk_register_gate2(struct device *dev, const char *name,
  46                 const char *parent_name, unsigned long flags,
  47                 void __iomem *reg, u8 bit_idx, u8 cgr_val,
  48                 u8 clk_gate_flags, spinlock_t *lock,
  49                 unsigned int *share_count);
  50
  51 struct clk * imx_obtain_fixed_clock(
  52                         const char *name, unsigned long rate);
  53
  54 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
  55          void __iomem *reg, u8 shift, u32 exclusive_mask);
  56
  57 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
  58                 void __iomem *reg, u8 idx);
  59
  60 struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
  61                                  void __iomem *reg, u8 shift, u8 width,
  62                                  void __iomem *busy_reg, u8 busy_shift);
  63
  64 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
  65                              u8 width, void __iomem *busy_reg, u8 busy_shift,
  66                              const char **parent_names, int num_parents);
  67
  68 struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
  69                                   void __iomem *reg, u8 shift, u8 width,
  70                                   void (*fixup)(u32 *val));
  71
  72 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
  73                               u8 shift, u8 width, const char **parents,
  74                               int num_parents, void (*fixup)(u32 *val));
  75
  76 static inline struct clk *imx_clk_fixed(const char *name, int rate)
  77 {
  78         return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
  79 }
  80
  81 static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
  82                 u8 shift, u8 width, const char **parents, int num_parents)
  83 {
  84         return clk_register_mux(NULL, name, parents, num_parents,
  85                         CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
  86                         shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
  87 }
  88
  89 static inline struct clk *imx_clk_fixed_factor(const char *name,
  90                 const char *parent, unsigned int mult, unsigned int div)
  91 {
  92         return clk_register_fixed_factor(NULL, name, parent,
  93                         CLK_SET_RATE_PARENT, mult, div);
  94 }
  95
  96 static inline struct clk *imx_clk_divider(const char *name, const char *parent,
  97                 void __iomem *reg, u8 shift, u8 width)
  98 {
  99         return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
 100                         reg, shift, width, 0, &imx_ccm_lock);
 101 }
 102
 103 static inline struct clk *imx_clk_divider_flags(const char *name,
 104                 const char *parent, void __iomem *reg, u8 shift, u8 width,
 105                 unsigned long flags)
 106 {
 107         return clk_register_divider(NULL, name, parent, flags,
 108                         reg, shift, width, 0, &imx_ccm_lock);
 109 }
 110
 111 static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
 112                 void __iomem *reg, u8 shift, u8 width)
 113 {
 114         return clk_register_divider(NULL, name, parent,
 115                         CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 116                         reg, shift, width, 0, &imx_ccm_lock);
 117 }
 118
 119 static inline struct clk *imx_clk_gate(const char *name, const char *parent,
 120                 void __iomem *reg, u8 shift)
 121 {
 122         return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
 123                         shift, 0, &imx_ccm_lock);
 124 }
 125
 126 static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
 127                 void __iomem *reg, u8 shift)
 128 {
 129         return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
 130                         shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
 131 }
 132
 133 static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
 134                 void __iomem *reg, u8 shift)
 135 {
 136         return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
 137                         shift, 0x3, 0, &imx_ccm_lock, NULL);
 138 }
 139
 140 static inline struct clk *imx_clk_gate2_shared(const char *name,
 141                 const char *parent, void __iomem *reg, u8 shift,
 142                 unsigned int *share_count)
 143 {
 144         return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
 145                         shift, 0x3, 0, &imx_ccm_lock, share_count);
 146 }
 147
 148 static inline struct clk *imx_clk_gate2_shared2(const char *name,
 149                 const char *parent, void __iomem *reg, u8 shift,
 150                 unsigned int *share_count)
 151 {
 152         return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
 153                                   CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
 154                                   &imx_ccm_lock, share_count);
 155 }
 156
 157 static inline struct clk *imx_clk_gate2_cgr(const char *name,
 158                 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
 159 {
 160         return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
 161                         shift, cgr_val, 0, &imx_ccm_lock, NULL);
 162 }
 163
 164 static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
 165                 void __iomem *reg, u8 shift)
 166 {
 167         return clk_register_gate(NULL, name, parent,
 168                         CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 169                         reg, shift, 0, &imx_ccm_lock);
 170 }
 171
 172 static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
 173                 void __iomem *reg, u8 shift)
 174 {
 175         return clk_register_gate2(NULL, name, parent,
 176                         CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 177                         reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
 178 }
 179
 180 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 181                 u8 shift, u8 width, const char **parents, int num_parents)
 182 {
 183         return clk_register_mux(NULL, name, parents, num_parents,
 184                         CLK_SET_RATE_NO_REPARENT, reg, shift,
 185                         width, 0, &imx_ccm_lock);
 186 }
 187
 188 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
 189                 u8 shift, u8 width, const char **parents, int num_parents)
 190 {
 191         return clk_register_mux(NULL, name, parents, num_parents,
 192                         CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
 193                         reg, shift, width, 0, &imx_ccm_lock);
 194 }
 195
 196 static inline struct clk *imx_clk_mux_flags(const char *name,
 197                 void __iomem *reg, u8 shift, u8 width, const char **parents,
 198                 int num_parents, unsigned long flags)
 199 {
 200         return clk_register_mux(NULL, name, parents, num_parents,
 201                         flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
 202                         &imx_ccm_lock);
 203 }
 204
 205 struct clk *imx_clk_cpu(const char *name, const char *parent_name,
 206                 struct clk *div, struct clk *mux, struct clk *pll,
 207                 struct clk *step);
 208
 209 #endif