2 * AmLogic S905 / GXBB Clock Controller Driver
4 * Copyright (c) 2016 AmLogic, Inc.
5 * Michael Turquette <mturquette@baylibre.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/clk.h>
21 #include <linux/clk-provider.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/init.h>
30 static DEFINE_SPINLOCK(meson_clk_lock
);
32 static const struct pll_rate_table sys_pll_rate_table
[] = {
33 PLL_RATE(24000000, 56, 1, 2),
34 PLL_RATE(48000000, 64, 1, 2),
35 PLL_RATE(72000000, 72, 1, 2),
36 PLL_RATE(96000000, 64, 1, 2),
37 PLL_RATE(120000000, 80, 1, 2),
38 PLL_RATE(144000000, 96, 1, 2),
39 PLL_RATE(168000000, 56, 1, 1),
40 PLL_RATE(192000000, 64, 1, 1),
41 PLL_RATE(216000000, 72, 1, 1),
42 PLL_RATE(240000000, 80, 1, 1),
43 PLL_RATE(264000000, 88, 1, 1),
44 PLL_RATE(288000000, 96, 1, 1),
45 PLL_RATE(312000000, 52, 1, 2),
46 PLL_RATE(336000000, 56, 1, 2),
47 PLL_RATE(360000000, 60, 1, 2),
48 PLL_RATE(384000000, 64, 1, 2),
49 PLL_RATE(408000000, 68, 1, 2),
50 PLL_RATE(432000000, 72, 1, 2),
51 PLL_RATE(456000000, 76, 1, 2),
52 PLL_RATE(480000000, 80, 1, 2),
53 PLL_RATE(504000000, 84, 1, 2),
54 PLL_RATE(528000000, 88, 1, 2),
55 PLL_RATE(552000000, 92, 1, 2),
56 PLL_RATE(576000000, 96, 1, 2),
57 PLL_RATE(600000000, 50, 1, 1),
58 PLL_RATE(624000000, 52, 1, 1),
59 PLL_RATE(648000000, 54, 1, 1),
60 PLL_RATE(672000000, 56, 1, 1),
61 PLL_RATE(696000000, 58, 1, 1),
62 PLL_RATE(720000000, 60, 1, 1),
63 PLL_RATE(744000000, 62, 1, 1),
64 PLL_RATE(768000000, 64, 1, 1),
65 PLL_RATE(792000000, 66, 1, 1),
66 PLL_RATE(816000000, 68, 1, 1),
67 PLL_RATE(840000000, 70, 1, 1),
68 PLL_RATE(864000000, 72, 1, 1),
69 PLL_RATE(888000000, 74, 1, 1),
70 PLL_RATE(912000000, 76, 1, 1),
71 PLL_RATE(936000000, 78, 1, 1),
72 PLL_RATE(960000000, 80, 1, 1),
73 PLL_RATE(984000000, 82, 1, 1),
74 PLL_RATE(1008000000, 84, 1, 1),
75 PLL_RATE(1032000000, 86, 1, 1),
76 PLL_RATE(1056000000, 88, 1, 1),
77 PLL_RATE(1080000000, 90, 1, 1),
78 PLL_RATE(1104000000, 92, 1, 1),
79 PLL_RATE(1128000000, 94, 1, 1),
80 PLL_RATE(1152000000, 96, 1, 1),
81 PLL_RATE(1176000000, 98, 1, 1),
82 PLL_RATE(1200000000, 50, 1, 0),
83 PLL_RATE(1224000000, 51, 1, 0),
84 PLL_RATE(1248000000, 52, 1, 0),
85 PLL_RATE(1272000000, 53, 1, 0),
86 PLL_RATE(1296000000, 54, 1, 0),
87 PLL_RATE(1320000000, 55, 1, 0),
88 PLL_RATE(1344000000, 56, 1, 0),
89 PLL_RATE(1368000000, 57, 1, 0),
90 PLL_RATE(1392000000, 58, 1, 0),
91 PLL_RATE(1416000000, 59, 1, 0),
92 PLL_RATE(1440000000, 60, 1, 0),
93 PLL_RATE(1464000000, 61, 1, 0),
94 PLL_RATE(1488000000, 62, 1, 0),
95 PLL_RATE(1512000000, 63, 1, 0),
96 PLL_RATE(1536000000, 64, 1, 0),
97 PLL_RATE(1560000000, 65, 1, 0),
98 PLL_RATE(1584000000, 66, 1, 0),
99 PLL_RATE(1608000000, 67, 1, 0),
100 PLL_RATE(1632000000, 68, 1, 0),
101 PLL_RATE(1656000000, 68, 1, 0),
102 PLL_RATE(1680000000, 68, 1, 0),
103 PLL_RATE(1704000000, 68, 1, 0),
104 PLL_RATE(1728000000, 69, 1, 0),
105 PLL_RATE(1752000000, 69, 1, 0),
106 PLL_RATE(1776000000, 69, 1, 0),
107 PLL_RATE(1800000000, 69, 1, 0),
108 PLL_RATE(1824000000, 70, 1, 0),
109 PLL_RATE(1848000000, 70, 1, 0),
110 PLL_RATE(1872000000, 70, 1, 0),
111 PLL_RATE(1896000000, 70, 1, 0),
112 PLL_RATE(1920000000, 71, 1, 0),
113 PLL_RATE(1944000000, 71, 1, 0),
114 PLL_RATE(1968000000, 71, 1, 0),
115 PLL_RATE(1992000000, 71, 1, 0),
116 PLL_RATE(2016000000, 72, 1, 0),
117 PLL_RATE(2040000000, 72, 1, 0),
118 PLL_RATE(2064000000, 72, 1, 0),
119 PLL_RATE(2088000000, 72, 1, 0),
120 PLL_RATE(2112000000, 73, 1, 0),
124 static const struct pll_rate_table gxbb_gp0_pll_rate_table
[] = {
125 PLL_RATE(96000000, 32, 1, 3),
126 PLL_RATE(99000000, 33, 1, 3),
127 PLL_RATE(102000000, 34, 1, 3),
128 PLL_RATE(105000000, 35, 1, 3),
129 PLL_RATE(108000000, 36, 1, 3),
130 PLL_RATE(111000000, 37, 1, 3),
131 PLL_RATE(114000000, 38, 1, 3),
132 PLL_RATE(117000000, 39, 1, 3),
133 PLL_RATE(120000000, 40, 1, 3),
134 PLL_RATE(123000000, 41, 1, 3),
135 PLL_RATE(126000000, 42, 1, 3),
136 PLL_RATE(129000000, 43, 1, 3),
137 PLL_RATE(132000000, 44, 1, 3),
138 PLL_RATE(135000000, 45, 1, 3),
139 PLL_RATE(138000000, 46, 1, 3),
140 PLL_RATE(141000000, 47, 1, 3),
141 PLL_RATE(144000000, 48, 1, 3),
142 PLL_RATE(147000000, 49, 1, 3),
143 PLL_RATE(150000000, 50, 1, 3),
144 PLL_RATE(153000000, 51, 1, 3),
145 PLL_RATE(156000000, 52, 1, 3),
146 PLL_RATE(159000000, 53, 1, 3),
147 PLL_RATE(162000000, 54, 1, 3),
148 PLL_RATE(165000000, 55, 1, 3),
149 PLL_RATE(168000000, 56, 1, 3),
150 PLL_RATE(171000000, 57, 1, 3),
151 PLL_RATE(174000000, 58, 1, 3),
152 PLL_RATE(177000000, 59, 1, 3),
153 PLL_RATE(180000000, 60, 1, 3),
154 PLL_RATE(183000000, 61, 1, 3),
155 PLL_RATE(186000000, 62, 1, 3),
156 PLL_RATE(192000000, 32, 1, 2),
157 PLL_RATE(198000000, 33, 1, 2),
158 PLL_RATE(204000000, 34, 1, 2),
159 PLL_RATE(210000000, 35, 1, 2),
160 PLL_RATE(216000000, 36, 1, 2),
161 PLL_RATE(222000000, 37, 1, 2),
162 PLL_RATE(228000000, 38, 1, 2),
163 PLL_RATE(234000000, 39, 1, 2),
164 PLL_RATE(240000000, 40, 1, 2),
165 PLL_RATE(246000000, 41, 1, 2),
166 PLL_RATE(252000000, 42, 1, 2),
167 PLL_RATE(258000000, 43, 1, 2),
168 PLL_RATE(264000000, 44, 1, 2),
169 PLL_RATE(270000000, 45, 1, 2),
170 PLL_RATE(276000000, 46, 1, 2),
171 PLL_RATE(282000000, 47, 1, 2),
172 PLL_RATE(288000000, 48, 1, 2),
173 PLL_RATE(294000000, 49, 1, 2),
174 PLL_RATE(300000000, 50, 1, 2),
175 PLL_RATE(306000000, 51, 1, 2),
176 PLL_RATE(312000000, 52, 1, 2),
177 PLL_RATE(318000000, 53, 1, 2),
178 PLL_RATE(324000000, 54, 1, 2),
179 PLL_RATE(330000000, 55, 1, 2),
180 PLL_RATE(336000000, 56, 1, 2),
181 PLL_RATE(342000000, 57, 1, 2),
182 PLL_RATE(348000000, 58, 1, 2),
183 PLL_RATE(354000000, 59, 1, 2),
184 PLL_RATE(360000000, 60, 1, 2),
185 PLL_RATE(366000000, 61, 1, 2),
186 PLL_RATE(372000000, 62, 1, 2),
187 PLL_RATE(384000000, 32, 1, 1),
188 PLL_RATE(396000000, 33, 1, 1),
189 PLL_RATE(408000000, 34, 1, 1),
190 PLL_RATE(420000000, 35, 1, 1),
191 PLL_RATE(432000000, 36, 1, 1),
192 PLL_RATE(444000000, 37, 1, 1),
193 PLL_RATE(456000000, 38, 1, 1),
194 PLL_RATE(468000000, 39, 1, 1),
195 PLL_RATE(480000000, 40, 1, 1),
196 PLL_RATE(492000000, 41, 1, 1),
197 PLL_RATE(504000000, 42, 1, 1),
198 PLL_RATE(516000000, 43, 1, 1),
199 PLL_RATE(528000000, 44, 1, 1),
200 PLL_RATE(540000000, 45, 1, 1),
201 PLL_RATE(552000000, 46, 1, 1),
202 PLL_RATE(564000000, 47, 1, 1),
203 PLL_RATE(576000000, 48, 1, 1),
204 PLL_RATE(588000000, 49, 1, 1),
205 PLL_RATE(600000000, 50, 1, 1),
206 PLL_RATE(612000000, 51, 1, 1),
207 PLL_RATE(624000000, 52, 1, 1),
208 PLL_RATE(636000000, 53, 1, 1),
209 PLL_RATE(648000000, 54, 1, 1),
210 PLL_RATE(660000000, 55, 1, 1),
211 PLL_RATE(672000000, 56, 1, 1),
212 PLL_RATE(684000000, 57, 1, 1),
213 PLL_RATE(696000000, 58, 1, 1),
214 PLL_RATE(708000000, 59, 1, 1),
215 PLL_RATE(720000000, 60, 1, 1),
216 PLL_RATE(732000000, 61, 1, 1),
217 PLL_RATE(744000000, 62, 1, 1),
218 PLL_RATE(768000000, 32, 1, 0),
219 PLL_RATE(792000000, 33, 1, 0),
220 PLL_RATE(816000000, 34, 1, 0),
221 PLL_RATE(840000000, 35, 1, 0),
222 PLL_RATE(864000000, 36, 1, 0),
223 PLL_RATE(888000000, 37, 1, 0),
224 PLL_RATE(912000000, 38, 1, 0),
225 PLL_RATE(936000000, 39, 1, 0),
226 PLL_RATE(960000000, 40, 1, 0),
227 PLL_RATE(984000000, 41, 1, 0),
228 PLL_RATE(1008000000, 42, 1, 0),
229 PLL_RATE(1032000000, 43, 1, 0),
230 PLL_RATE(1056000000, 44, 1, 0),
231 PLL_RATE(1080000000, 45, 1, 0),
232 PLL_RATE(1104000000, 46, 1, 0),
233 PLL_RATE(1128000000, 47, 1, 0),
234 PLL_RATE(1152000000, 48, 1, 0),
235 PLL_RATE(1176000000, 49, 1, 0),
236 PLL_RATE(1200000000, 50, 1, 0),
237 PLL_RATE(1224000000, 51, 1, 0),
238 PLL_RATE(1248000000, 52, 1, 0),
239 PLL_RATE(1272000000, 53, 1, 0),
240 PLL_RATE(1296000000, 54, 1, 0),
241 PLL_RATE(1320000000, 55, 1, 0),
242 PLL_RATE(1344000000, 56, 1, 0),
243 PLL_RATE(1368000000, 57, 1, 0),
244 PLL_RATE(1392000000, 58, 1, 0),
245 PLL_RATE(1416000000, 59, 1, 0),
246 PLL_RATE(1440000000, 60, 1, 0),
247 PLL_RATE(1464000000, 61, 1, 0),
248 PLL_RATE(1488000000, 62, 1, 0),
252 static const struct pll_rate_table gxl_gp0_pll_rate_table
[] = {
253 PLL_RATE(504000000, 42, 1, 1),
254 PLL_RATE(516000000, 43, 1, 1),
255 PLL_RATE(528000000, 44, 1, 1),
256 PLL_RATE(540000000, 45, 1, 1),
257 PLL_RATE(552000000, 46, 1, 1),
258 PLL_RATE(564000000, 47, 1, 1),
259 PLL_RATE(576000000, 48, 1, 1),
260 PLL_RATE(588000000, 49, 1, 1),
261 PLL_RATE(600000000, 50, 1, 1),
262 PLL_RATE(612000000, 51, 1, 1),
263 PLL_RATE(624000000, 52, 1, 1),
264 PLL_RATE(636000000, 53, 1, 1),
265 PLL_RATE(648000000, 54, 1, 1),
266 PLL_RATE(660000000, 55, 1, 1),
267 PLL_RATE(672000000, 56, 1, 1),
268 PLL_RATE(684000000, 57, 1, 1),
269 PLL_RATE(696000000, 58, 1, 1),
270 PLL_RATE(708000000, 59, 1, 1),
271 PLL_RATE(720000000, 60, 1, 1),
272 PLL_RATE(732000000, 61, 1, 1),
273 PLL_RATE(744000000, 62, 1, 1),
274 PLL_RATE(756000000, 63, 1, 1),
275 PLL_RATE(768000000, 64, 1, 1),
276 PLL_RATE(780000000, 65, 1, 1),
277 PLL_RATE(792000000, 66, 1, 1),
281 static struct meson_clk_pll gxbb_fixed_pll
= {
283 .reg_off
= HHI_MPLL_CNTL
,
288 .reg_off
= HHI_MPLL_CNTL
,
293 .reg_off
= HHI_MPLL_CNTL
,
297 .lock
= &meson_clk_lock
,
298 .hw
.init
= &(struct clk_init_data
){
300 .ops
= &meson_clk_pll_ro_ops
,
301 .parent_names
= (const char *[]){ "xtal" },
303 .flags
= CLK_GET_RATE_NOCACHE
,
307 static struct meson_clk_pll gxbb_hdmi_pll
= {
309 .reg_off
= HHI_HDMI_PLL_CNTL
,
314 .reg_off
= HHI_HDMI_PLL_CNTL
,
319 .reg_off
= HHI_HDMI_PLL_CNTL2
,
324 .reg_off
= HHI_HDMI_PLL_CNTL2
,
329 .reg_off
= HHI_HDMI_PLL_CNTL2
,
333 .lock
= &meson_clk_lock
,
334 .hw
.init
= &(struct clk_init_data
){
336 .ops
= &meson_clk_pll_ro_ops
,
337 .parent_names
= (const char *[]){ "xtal" },
339 .flags
= CLK_GET_RATE_NOCACHE
,
343 static struct meson_clk_pll gxbb_sys_pll
= {
345 .reg_off
= HHI_SYS_PLL_CNTL
,
350 .reg_off
= HHI_SYS_PLL_CNTL
,
355 .reg_off
= HHI_SYS_PLL_CNTL
,
359 .rate_table
= sys_pll_rate_table
,
360 .rate_count
= ARRAY_SIZE(sys_pll_rate_table
),
361 .lock
= &meson_clk_lock
,
362 .hw
.init
= &(struct clk_init_data
){
364 .ops
= &meson_clk_pll_ro_ops
,
365 .parent_names
= (const char *[]){ "xtal" },
367 .flags
= CLK_GET_RATE_NOCACHE
,
371 struct pll_params_table gxbb_gp0_params_table
[] = {
372 PLL_PARAM(HHI_GP0_PLL_CNTL
, 0x6a000228),
373 PLL_PARAM(HHI_GP0_PLL_CNTL2
, 0x69c80000),
374 PLL_PARAM(HHI_GP0_PLL_CNTL3
, 0x0a5590c4),
375 PLL_PARAM(HHI_GP0_PLL_CNTL4
, 0x0000500d),
378 static struct meson_clk_pll gxbb_gp0_pll
= {
380 .reg_off
= HHI_GP0_PLL_CNTL
,
385 .reg_off
= HHI_GP0_PLL_CNTL
,
390 .reg_off
= HHI_GP0_PLL_CNTL
,
395 .params_table
= gxbb_gp0_params_table
,
396 .params_count
= ARRAY_SIZE(gxbb_gp0_params_table
),
397 .no_init_reset
= true,
398 .clear_reset_for_lock
= true,
400 .rate_table
= gxbb_gp0_pll_rate_table
,
401 .rate_count
= ARRAY_SIZE(gxbb_gp0_pll_rate_table
),
402 .lock
= &meson_clk_lock
,
403 .hw
.init
= &(struct clk_init_data
){
405 .ops
= &meson_clk_pll_ops
,
406 .parent_names
= (const char *[]){ "xtal" },
408 .flags
= CLK_GET_RATE_NOCACHE
,
412 struct pll_params_table gxl_gp0_params_table
[] = {
413 PLL_PARAM(HHI_GP0_PLL_CNTL
, 0x40010250),
414 PLL_PARAM(HHI_GP0_PLL_CNTL1
, 0xc084a000),
415 PLL_PARAM(HHI_GP0_PLL_CNTL2
, 0xb75020be),
416 PLL_PARAM(HHI_GP0_PLL_CNTL3
, 0x0a59a288),
417 PLL_PARAM(HHI_GP0_PLL_CNTL4
, 0xc000004d),
418 PLL_PARAM(HHI_GP0_PLL_CNTL5
, 0x00078000),
421 static struct meson_clk_pll gxl_gp0_pll
= {
423 .reg_off
= HHI_GP0_PLL_CNTL
,
428 .reg_off
= HHI_GP0_PLL_CNTL
,
433 .reg_off
= HHI_GP0_PLL_CNTL
,
438 .params_table
= gxl_gp0_params_table
,
439 .params_count
= ARRAY_SIZE(gxl_gp0_params_table
),
440 .no_init_reset
= true,
441 .reset_lock_loop
= true,
443 .rate_table
= gxl_gp0_pll_rate_table
,
444 .rate_count
= ARRAY_SIZE(gxl_gp0_pll_rate_table
),
445 .lock
= &meson_clk_lock
,
446 .hw
.init
= &(struct clk_init_data
){
448 .ops
= &meson_clk_pll_ops
,
449 .parent_names
= (const char *[]){ "xtal" },
451 .flags
= CLK_GET_RATE_NOCACHE
,
455 static struct clk_fixed_factor gxbb_fclk_div2
= {
458 .hw
.init
= &(struct clk_init_data
){
460 .ops
= &clk_fixed_factor_ops
,
461 .parent_names
= (const char *[]){ "fixed_pll" },
466 static struct clk_fixed_factor gxbb_fclk_div3
= {
469 .hw
.init
= &(struct clk_init_data
){
471 .ops
= &clk_fixed_factor_ops
,
472 .parent_names
= (const char *[]){ "fixed_pll" },
477 static struct clk_fixed_factor gxbb_fclk_div4
= {
480 .hw
.init
= &(struct clk_init_data
){
482 .ops
= &clk_fixed_factor_ops
,
483 .parent_names
= (const char *[]){ "fixed_pll" },
488 static struct clk_fixed_factor gxbb_fclk_div5
= {
491 .hw
.init
= &(struct clk_init_data
){
493 .ops
= &clk_fixed_factor_ops
,
494 .parent_names
= (const char *[]){ "fixed_pll" },
499 static struct clk_fixed_factor gxbb_fclk_div7
= {
502 .hw
.init
= &(struct clk_init_data
){
504 .ops
= &clk_fixed_factor_ops
,
505 .parent_names
= (const char *[]){ "fixed_pll" },
510 static struct meson_clk_mpll gxbb_mpll0
= {
512 .reg_off
= HHI_MPLL_CNTL7
,
517 .reg_off
= HHI_MPLL_CNTL7
,
522 .reg_off
= HHI_MPLL_CNTL7
,
527 .reg_off
= HHI_MPLL_CNTL7
,
532 .reg_off
= HHI_MPLL_CNTL
,
536 .lock
= &meson_clk_lock
,
537 .hw
.init
= &(struct clk_init_data
){
539 .ops
= &meson_clk_mpll_ops
,
540 .parent_names
= (const char *[]){ "fixed_pll" },
545 static struct meson_clk_mpll gxbb_mpll1
= {
547 .reg_off
= HHI_MPLL_CNTL8
,
552 .reg_off
= HHI_MPLL_CNTL8
,
557 .reg_off
= HHI_MPLL_CNTL8
,
562 .reg_off
= HHI_MPLL_CNTL8
,
566 .lock
= &meson_clk_lock
,
567 .hw
.init
= &(struct clk_init_data
){
569 .ops
= &meson_clk_mpll_ops
,
570 .parent_names
= (const char *[]){ "fixed_pll" },
575 static struct meson_clk_mpll gxbb_mpll2
= {
577 .reg_off
= HHI_MPLL_CNTL9
,
582 .reg_off
= HHI_MPLL_CNTL9
,
587 .reg_off
= HHI_MPLL_CNTL9
,
592 .reg_off
= HHI_MPLL_CNTL9
,
596 .lock
= &meson_clk_lock
,
597 .hw
.init
= &(struct clk_init_data
){
599 .ops
= &meson_clk_mpll_ops
,
600 .parent_names
= (const char *[]){ "fixed_pll" },
606 * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers
607 * and should be modeled with their respective PLLs via the forthcoming
608 * coordinated clock rates feature
611 static u32 mux_table_clk81
[] = { 0, 2, 3, 4, 5, 6, 7 };
612 static const char * const clk81_parent_names
[] = {
613 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
614 "fclk_div3", "fclk_div5"
617 static struct clk_mux gxbb_mpeg_clk_sel
= {
618 .reg
= (void *)HHI_MPEG_CLK_CNTL
,
621 .flags
= CLK_MUX_READ_ONLY
,
622 .table
= mux_table_clk81
,
623 .lock
= &meson_clk_lock
,
624 .hw
.init
= &(struct clk_init_data
){
625 .name
= "mpeg_clk_sel",
626 .ops
= &clk_mux_ro_ops
,
628 * bits 14:12 selects from 8 possible parents:
629 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
630 * fclk_div4, fclk_div3, fclk_div5
632 .parent_names
= clk81_parent_names
,
633 .num_parents
= ARRAY_SIZE(clk81_parent_names
),
634 .flags
= (CLK_SET_RATE_NO_REPARENT
| CLK_IGNORE_UNUSED
),
638 static struct clk_divider gxbb_mpeg_clk_div
= {
639 .reg
= (void *)HHI_MPEG_CLK_CNTL
,
642 .lock
= &meson_clk_lock
,
643 .hw
.init
= &(struct clk_init_data
){
644 .name
= "mpeg_clk_div",
645 .ops
= &clk_divider_ops
,
646 .parent_names
= (const char *[]){ "mpeg_clk_sel" },
648 .flags
= (CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
),
652 /* the mother of dragons^W gates */
653 static struct clk_gate gxbb_clk81
= {
654 .reg
= (void *)HHI_MPEG_CLK_CNTL
,
656 .lock
= &meson_clk_lock
,
657 .hw
.init
= &(struct clk_init_data
){
659 .ops
= &clk_gate_ops
,
660 .parent_names
= (const char *[]){ "mpeg_clk_div" },
662 .flags
= (CLK_SET_RATE_PARENT
| CLK_IS_CRITICAL
),
666 static struct clk_mux gxbb_sar_adc_clk_sel
= {
667 .reg
= (void *)HHI_SAR_CLK_CNTL
,
670 .lock
= &meson_clk_lock
,
671 .hw
.init
= &(struct clk_init_data
){
672 .name
= "sar_adc_clk_sel",
674 /* NOTE: The datasheet doesn't list the parents for bit 10 */
675 .parent_names
= (const char *[]){ "xtal", "clk81", },
680 static struct clk_divider gxbb_sar_adc_clk_div
= {
681 .reg
= (void *)HHI_SAR_CLK_CNTL
,
684 .lock
= &meson_clk_lock
,
685 .hw
.init
= &(struct clk_init_data
){
686 .name
= "sar_adc_clk_div",
687 .ops
= &clk_divider_ops
,
688 .parent_names
= (const char *[]){ "sar_adc_clk_sel" },
693 static struct clk_gate gxbb_sar_adc_clk
= {
694 .reg
= (void *)HHI_SAR_CLK_CNTL
,
696 .lock
= &meson_clk_lock
,
697 .hw
.init
= &(struct clk_init_data
){
698 .name
= "sar_adc_clk",
699 .ops
= &clk_gate_ops
,
700 .parent_names
= (const char *[]){ "sar_adc_clk_div" },
702 .flags
= CLK_SET_RATE_PARENT
,
707 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
708 * muxed by a glitch-free switch.
711 static u32 mux_table_mali_0_1
[] = {0, 1, 2, 3, 4, 5, 6, 7};
712 static const char * const gxbb_mali_0_1_parent_names
[] = {
713 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
714 "fclk_div4", "fclk_div3", "fclk_div5"
717 static struct clk_mux gxbb_mali_0_sel
= {
718 .reg
= (void *)HHI_MALI_CLK_CNTL
,
721 .table
= mux_table_mali_0_1
,
722 .lock
= &meson_clk_lock
,
723 .hw
.init
= &(struct clk_init_data
){
724 .name
= "mali_0_sel",
727 * bits 10:9 selects from 8 possible parents:
728 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
729 * fclk_div4, fclk_div3, fclk_div5
731 .parent_names
= gxbb_mali_0_1_parent_names
,
733 .flags
= CLK_SET_RATE_NO_REPARENT
,
737 static struct clk_divider gxbb_mali_0_div
= {
738 .reg
= (void *)HHI_MALI_CLK_CNTL
,
741 .lock
= &meson_clk_lock
,
742 .hw
.init
= &(struct clk_init_data
){
743 .name
= "mali_0_div",
744 .ops
= &clk_divider_ops
,
745 .parent_names
= (const char *[]){ "mali_0_sel" },
747 .flags
= CLK_SET_RATE_NO_REPARENT
,
751 static struct clk_gate gxbb_mali_0
= {
752 .reg
= (void *)HHI_MALI_CLK_CNTL
,
754 .lock
= &meson_clk_lock
,
755 .hw
.init
= &(struct clk_init_data
){
757 .ops
= &clk_gate_ops
,
758 .parent_names
= (const char *[]){ "mali_0_div" },
760 .flags
= CLK_SET_RATE_PARENT
,
764 static struct clk_mux gxbb_mali_1_sel
= {
765 .reg
= (void *)HHI_MALI_CLK_CNTL
,
768 .table
= mux_table_mali_0_1
,
769 .lock
= &meson_clk_lock
,
770 .hw
.init
= &(struct clk_init_data
){
771 .name
= "mali_1_sel",
774 * bits 10:9 selects from 8 possible parents:
775 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
776 * fclk_div4, fclk_div3, fclk_div5
778 .parent_names
= gxbb_mali_0_1_parent_names
,
780 .flags
= CLK_SET_RATE_NO_REPARENT
,
784 static struct clk_divider gxbb_mali_1_div
= {
785 .reg
= (void *)HHI_MALI_CLK_CNTL
,
788 .lock
= &meson_clk_lock
,
789 .hw
.init
= &(struct clk_init_data
){
790 .name
= "mali_1_div",
791 .ops
= &clk_divider_ops
,
792 .parent_names
= (const char *[]){ "mali_1_sel" },
794 .flags
= CLK_SET_RATE_NO_REPARENT
,
798 static struct clk_gate gxbb_mali_1
= {
799 .reg
= (void *)HHI_MALI_CLK_CNTL
,
801 .lock
= &meson_clk_lock
,
802 .hw
.init
= &(struct clk_init_data
){
804 .ops
= &clk_gate_ops
,
805 .parent_names
= (const char *[]){ "mali_1_div" },
807 .flags
= CLK_SET_RATE_PARENT
,
811 static u32 mux_table_mali
[] = {0, 1};
812 static const char * const gxbb_mali_parent_names
[] = {
816 static struct clk_mux gxbb_mali
= {
817 .reg
= (void *)HHI_MALI_CLK_CNTL
,
820 .table
= mux_table_mali
,
821 .lock
= &meson_clk_lock
,
822 .hw
.init
= &(struct clk_init_data
){
825 .parent_names
= gxbb_mali_parent_names
,
827 .flags
= CLK_SET_RATE_NO_REPARENT
,
831 static struct clk_mux gxbb_cts_amclk_sel
= {
832 .reg
= (void *) HHI_AUD_CLK_CNTL
,
835 /* Default parent unknown (register reset value: 0) */
836 .table
= (u32
[]){ 1, 2, 3 },
837 .lock
= &meson_clk_lock
,
838 .hw
.init
= &(struct clk_init_data
){
839 .name
= "cts_amclk_sel",
841 .parent_names
= (const char *[]){ "mpll0", "mpll1", "mpll2" },
843 .flags
= CLK_SET_RATE_PARENT
,
847 static struct meson_clk_audio_divider gxbb_cts_amclk_div
= {
849 .reg_off
= HHI_AUD_CLK_CNTL
,
853 .flags
= CLK_DIVIDER_ROUND_CLOSEST
,
854 .lock
= &meson_clk_lock
,
855 .hw
.init
= &(struct clk_init_data
){
856 .name
= "cts_amclk_div",
857 .ops
= &meson_clk_audio_divider_ops
,
858 .parent_names
= (const char *[]){ "cts_amclk_sel" },
860 .flags
= CLK_SET_RATE_PARENT
,
864 static struct clk_gate gxbb_cts_amclk
= {
865 .reg
= (void *) HHI_AUD_CLK_CNTL
,
867 .lock
= &meson_clk_lock
,
868 .hw
.init
= &(struct clk_init_data
){
870 .ops
= &clk_gate_ops
,
871 .parent_names
= (const char *[]){ "cts_amclk_div" },
873 .flags
= CLK_SET_RATE_PARENT
,
877 static struct clk_mux gxbb_cts_mclk_i958_sel
= {
878 .reg
= (void *)HHI_AUD_CLK_CNTL2
,
881 /* Default parent unknown (register reset value: 0) */
882 .table
= (u32
[]){ 1, 2, 3 },
883 .lock
= &meson_clk_lock
,
884 .hw
.init
= &(struct clk_init_data
) {
885 .name
= "cts_mclk_i958_sel",
887 .parent_names
= (const char *[]){ "mpll0", "mpll1", "mpll2" },
889 .flags
= CLK_SET_RATE_PARENT
,
893 static struct clk_divider gxbb_cts_mclk_i958_div
= {
894 .reg
= (void *)HHI_AUD_CLK_CNTL2
,
897 .lock
= &meson_clk_lock
,
898 .flags
= CLK_DIVIDER_ROUND_CLOSEST
,
899 .hw
.init
= &(struct clk_init_data
) {
900 .name
= "cts_mclk_i958_div",
901 .ops
= &clk_divider_ops
,
902 .parent_names
= (const char *[]){ "cts_mclk_i958_sel" },
904 .flags
= CLK_SET_RATE_PARENT
,
908 static struct clk_gate gxbb_cts_mclk_i958
= {
909 .reg
= (void *)HHI_AUD_CLK_CNTL2
,
911 .lock
= &meson_clk_lock
,
912 .hw
.init
= &(struct clk_init_data
){
913 .name
= "cts_mclk_i958",
914 .ops
= &clk_gate_ops
,
915 .parent_names
= (const char *[]){ "cts_mclk_i958_div" },
917 .flags
= CLK_SET_RATE_PARENT
,
921 static struct clk_mux gxbb_cts_i958
= {
922 .reg
= (void *)HHI_AUD_CLK_CNTL2
,
925 .lock
= &meson_clk_lock
,
926 .hw
.init
= &(struct clk_init_data
){
929 .parent_names
= (const char *[]){ "cts_amclk", "cts_mclk_i958" },
932 *The parent is specific to origin of the audio data. Let the
933 * consumer choose the appropriate parent
935 .flags
= CLK_SET_RATE_PARENT
| CLK_SET_RATE_NO_REPARENT
,
939 static struct clk_divider gxbb_32k_clk_div
= {
940 .reg
= (void *)HHI_32K_CLK_CNTL
,
943 .lock
= &meson_clk_lock
,
944 .hw
.init
= &(struct clk_init_data
){
945 .name
= "32k_clk_div",
946 .ops
= &clk_divider_ops
,
947 .parent_names
= (const char *[]){ "32k_clk_sel" },
949 .flags
= CLK_SET_RATE_PARENT
| CLK_DIVIDER_ROUND_CLOSEST
,
953 static struct clk_gate gxbb_32k_clk
= {
954 .reg
= (void *)HHI_32K_CLK_CNTL
,
956 .lock
= &meson_clk_lock
,
957 .hw
.init
= &(struct clk_init_data
){
959 .ops
= &clk_gate_ops
,
960 .parent_names
= (const char *[]){ "32k_clk_div" },
962 .flags
= CLK_SET_RATE_PARENT
,
966 static const char * const gxbb_32k_clk_parent_names
[] = {
967 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
970 static struct clk_mux gxbb_32k_clk_sel
= {
971 .reg
= (void *)HHI_32K_CLK_CNTL
,
974 .lock
= &meson_clk_lock
,
975 .hw
.init
= &(struct clk_init_data
){
976 .name
= "32k_clk_sel",
978 .parent_names
= gxbb_32k_clk_parent_names
,
980 .flags
= CLK_SET_RATE_PARENT
,
984 static const char * const gxbb_sd_emmc_clk0_parent_names
[] = {
985 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
988 * Following these parent clocks, we should also have had mpll2, mpll3
989 * and gp0_pll but these clocks are too precious to be used here. All
990 * the necessary rates for MMC and NAND operation can be acheived using
991 * xtal or fclk_div clocks
996 static struct clk_mux gxbb_sd_emmc_a_clk0_sel
= {
997 .reg
= (void *)HHI_SD_EMMC_CLK_CNTL
,
1000 .lock
= &meson_clk_lock
,
1001 .hw
.init
= &(struct clk_init_data
) {
1002 .name
= "sd_emmc_a_clk0_sel",
1003 .ops
= &clk_mux_ops
,
1004 .parent_names
= gxbb_sd_emmc_clk0_parent_names
,
1005 .num_parents
= ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names
),
1006 .flags
= CLK_SET_RATE_PARENT
,
1010 static struct clk_divider gxbb_sd_emmc_a_clk0_div
= {
1011 .reg
= (void *)HHI_SD_EMMC_CLK_CNTL
,
1014 .lock
= &meson_clk_lock
,
1015 .flags
= CLK_DIVIDER_ROUND_CLOSEST
,
1016 .hw
.init
= &(struct clk_init_data
) {
1017 .name
= "sd_emmc_a_clk0_div",
1018 .ops
= &clk_divider_ops
,
1019 .parent_names
= (const char *[]){ "sd_emmc_a_clk0_sel" },
1021 .flags
= CLK_SET_RATE_PARENT
,
1025 static struct clk_gate gxbb_sd_emmc_a_clk0
= {
1026 .reg
= (void *)HHI_SD_EMMC_CLK_CNTL
,
1028 .lock
= &meson_clk_lock
,
1029 .hw
.init
= &(struct clk_init_data
){
1030 .name
= "sd_emmc_a_clk0",
1031 .ops
= &clk_gate_ops
,
1032 .parent_names
= (const char *[]){ "sd_emmc_a_clk0_div" },
1034 .flags
= CLK_SET_RATE_PARENT
,
1039 static struct clk_mux gxbb_sd_emmc_b_clk0_sel
= {
1040 .reg
= (void *)HHI_SD_EMMC_CLK_CNTL
,
1043 .lock
= &meson_clk_lock
,
1044 .hw
.init
= &(struct clk_init_data
) {
1045 .name
= "sd_emmc_b_clk0_sel",
1046 .ops
= &clk_mux_ops
,
1047 .parent_names
= gxbb_sd_emmc_clk0_parent_names
,
1048 .num_parents
= ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names
),
1049 .flags
= CLK_SET_RATE_PARENT
,
1053 static struct clk_divider gxbb_sd_emmc_b_clk0_div
= {
1054 .reg
= (void *)HHI_SD_EMMC_CLK_CNTL
,
1057 .lock
= &meson_clk_lock
,
1058 .flags
= CLK_DIVIDER_ROUND_CLOSEST
,
1059 .hw
.init
= &(struct clk_init_data
) {
1060 .name
= "sd_emmc_b_clk0_div",
1061 .ops
= &clk_divider_ops
,
1062 .parent_names
= (const char *[]){ "sd_emmc_b_clk0_sel" },
1064 .flags
= CLK_SET_RATE_PARENT
,
1068 static struct clk_gate gxbb_sd_emmc_b_clk0
= {
1069 .reg
= (void *)HHI_SD_EMMC_CLK_CNTL
,
1071 .lock
= &meson_clk_lock
,
1072 .hw
.init
= &(struct clk_init_data
){
1073 .name
= "sd_emmc_b_clk0",
1074 .ops
= &clk_gate_ops
,
1075 .parent_names
= (const char *[]){ "sd_emmc_b_clk0_div" },
1077 .flags
= CLK_SET_RATE_PARENT
,
1081 /* EMMC/NAND clock */
1082 static struct clk_mux gxbb_sd_emmc_c_clk0_sel
= {
1083 .reg
= (void *)HHI_NAND_CLK_CNTL
,
1086 .lock
= &meson_clk_lock
,
1087 .hw
.init
= &(struct clk_init_data
) {
1088 .name
= "sd_emmc_c_clk0_sel",
1089 .ops
= &clk_mux_ops
,
1090 .parent_names
= gxbb_sd_emmc_clk0_parent_names
,
1091 .num_parents
= ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names
),
1092 .flags
= CLK_SET_RATE_PARENT
,
1096 static struct clk_divider gxbb_sd_emmc_c_clk0_div
= {
1097 .reg
= (void *)HHI_NAND_CLK_CNTL
,
1100 .lock
= &meson_clk_lock
,
1101 .flags
= CLK_DIVIDER_ROUND_CLOSEST
,
1102 .hw
.init
= &(struct clk_init_data
) {
1103 .name
= "sd_emmc_c_clk0_div",
1104 .ops
= &clk_divider_ops
,
1105 .parent_names
= (const char *[]){ "sd_emmc_c_clk0_sel" },
1107 .flags
= CLK_SET_RATE_PARENT
,
1111 static struct clk_gate gxbb_sd_emmc_c_clk0
= {
1112 .reg
= (void *)HHI_NAND_CLK_CNTL
,
1114 .lock
= &meson_clk_lock
,
1115 .hw
.init
= &(struct clk_init_data
){
1116 .name
= "sd_emmc_c_clk0",
1117 .ops
= &clk_gate_ops
,
1118 .parent_names
= (const char *[]){ "sd_emmc_c_clk0_div" },
1120 .flags
= CLK_SET_RATE_PARENT
,
1126 static u32 mux_table_vpu
[] = {0, 1, 2, 3};
1127 static const char * const gxbb_vpu_parent_names
[] = {
1128 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1131 static struct clk_mux gxbb_vpu_0_sel
= {
1132 .reg
= (void *)HHI_VPU_CLK_CNTL
,
1135 .lock
= &meson_clk_lock
,
1136 .table
= mux_table_vpu
,
1137 .hw
.init
= &(struct clk_init_data
){
1138 .name
= "vpu_0_sel",
1139 .ops
= &clk_mux_ops
,
1141 * bits 9:10 selects from 4 possible parents:
1142 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1144 .parent_names
= gxbb_vpu_parent_names
,
1145 .num_parents
= ARRAY_SIZE(gxbb_vpu_parent_names
),
1146 .flags
= CLK_SET_RATE_NO_REPARENT
,
1150 static struct clk_divider gxbb_vpu_0_div
= {
1151 .reg
= (void *)HHI_VPU_CLK_CNTL
,
1154 .lock
= &meson_clk_lock
,
1155 .hw
.init
= &(struct clk_init_data
){
1156 .name
= "vpu_0_div",
1157 .ops
= &clk_divider_ops
,
1158 .parent_names
= (const char *[]){ "vpu_0_sel" },
1160 .flags
= CLK_SET_RATE_PARENT
,
1164 static struct clk_gate gxbb_vpu_0
= {
1165 .reg
= (void *)HHI_VPU_CLK_CNTL
,
1167 .lock
= &meson_clk_lock
,
1168 .hw
.init
= &(struct clk_init_data
) {
1170 .ops
= &clk_gate_ops
,
1171 .parent_names
= (const char *[]){ "vpu_0_div" },
1173 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1177 static struct clk_mux gxbb_vpu_1_sel
= {
1178 .reg
= (void *)HHI_VPU_CLK_CNTL
,
1181 .lock
= &meson_clk_lock
,
1182 .table
= mux_table_vpu
,
1183 .hw
.init
= &(struct clk_init_data
){
1184 .name
= "vpu_1_sel",
1185 .ops
= &clk_mux_ops
,
1187 * bits 25:26 selects from 4 possible parents:
1188 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1190 .parent_names
= gxbb_vpu_parent_names
,
1191 .num_parents
= ARRAY_SIZE(gxbb_vpu_parent_names
),
1192 .flags
= CLK_SET_RATE_NO_REPARENT
,
1196 static struct clk_divider gxbb_vpu_1_div
= {
1197 .reg
= (void *)HHI_VPU_CLK_CNTL
,
1200 .lock
= &meson_clk_lock
,
1201 .hw
.init
= &(struct clk_init_data
){
1202 .name
= "vpu_1_div",
1203 .ops
= &clk_divider_ops
,
1204 .parent_names
= (const char *[]){ "vpu_1_sel" },
1206 .flags
= CLK_SET_RATE_PARENT
,
1210 static struct clk_gate gxbb_vpu_1
= {
1211 .reg
= (void *)HHI_VPU_CLK_CNTL
,
1213 .lock
= &meson_clk_lock
,
1214 .hw
.init
= &(struct clk_init_data
) {
1216 .ops
= &clk_gate_ops
,
1217 .parent_names
= (const char *[]){ "vpu_1_div" },
1219 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1223 static struct clk_mux gxbb_vpu
= {
1224 .reg
= (void *)HHI_VPU_CLK_CNTL
,
1227 .lock
= &meson_clk_lock
,
1228 .hw
.init
= &(struct clk_init_data
){
1230 .ops
= &clk_mux_ops
,
1232 * bit 31 selects from 2 possible parents:
1235 .parent_names
= (const char *[]){ "vpu_0", "vpu_1" },
1237 .flags
= CLK_SET_RATE_NO_REPARENT
,
1243 static u32 mux_table_vapb
[] = {0, 1, 2, 3};
1244 static const char * const gxbb_vapb_parent_names
[] = {
1245 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1248 static struct clk_mux gxbb_vapb_0_sel
= {
1249 .reg
= (void *)HHI_VAPBCLK_CNTL
,
1252 .lock
= &meson_clk_lock
,
1253 .table
= mux_table_vapb
,
1254 .hw
.init
= &(struct clk_init_data
){
1255 .name
= "vapb_0_sel",
1256 .ops
= &clk_mux_ops
,
1258 * bits 9:10 selects from 4 possible parents:
1259 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1261 .parent_names
= gxbb_vapb_parent_names
,
1262 .num_parents
= ARRAY_SIZE(gxbb_vapb_parent_names
),
1263 .flags
= CLK_SET_RATE_NO_REPARENT
,
1267 static struct clk_divider gxbb_vapb_0_div
= {
1268 .reg
= (void *)HHI_VAPBCLK_CNTL
,
1271 .lock
= &meson_clk_lock
,
1272 .hw
.init
= &(struct clk_init_data
){
1273 .name
= "vapb_0_div",
1274 .ops
= &clk_divider_ops
,
1275 .parent_names
= (const char *[]){ "vapb_0_sel" },
1277 .flags
= CLK_SET_RATE_PARENT
,
1281 static struct clk_gate gxbb_vapb_0
= {
1282 .reg
= (void *)HHI_VAPBCLK_CNTL
,
1284 .lock
= &meson_clk_lock
,
1285 .hw
.init
= &(struct clk_init_data
) {
1287 .ops
= &clk_gate_ops
,
1288 .parent_names
= (const char *[]){ "vapb_0_div" },
1290 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1294 static struct clk_mux gxbb_vapb_1_sel
= {
1295 .reg
= (void *)HHI_VAPBCLK_CNTL
,
1298 .lock
= &meson_clk_lock
,
1299 .table
= mux_table_vapb
,
1300 .hw
.init
= &(struct clk_init_data
){
1301 .name
= "vapb_1_sel",
1302 .ops
= &clk_mux_ops
,
1304 * bits 25:26 selects from 4 possible parents:
1305 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1307 .parent_names
= gxbb_vapb_parent_names
,
1308 .num_parents
= ARRAY_SIZE(gxbb_vapb_parent_names
),
1309 .flags
= CLK_SET_RATE_NO_REPARENT
,
1313 static struct clk_divider gxbb_vapb_1_div
= {
1314 .reg
= (void *)HHI_VAPBCLK_CNTL
,
1317 .lock
= &meson_clk_lock
,
1318 .hw
.init
= &(struct clk_init_data
){
1319 .name
= "vapb_1_div",
1320 .ops
= &clk_divider_ops
,
1321 .parent_names
= (const char *[]){ "vapb_1_sel" },
1323 .flags
= CLK_SET_RATE_PARENT
,
1327 static struct clk_gate gxbb_vapb_1
= {
1328 .reg
= (void *)HHI_VAPBCLK_CNTL
,
1330 .lock
= &meson_clk_lock
,
1331 .hw
.init
= &(struct clk_init_data
) {
1333 .ops
= &clk_gate_ops
,
1334 .parent_names
= (const char *[]){ "vapb_1_div" },
1336 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1340 static struct clk_mux gxbb_vapb_sel
= {
1341 .reg
= (void *)HHI_VAPBCLK_CNTL
,
1344 .lock
= &meson_clk_lock
,
1345 .hw
.init
= &(struct clk_init_data
){
1347 .ops
= &clk_mux_ops
,
1349 * bit 31 selects from 2 possible parents:
1352 .parent_names
= (const char *[]){ "vapb_0", "vapb_1" },
1354 .flags
= CLK_SET_RATE_NO_REPARENT
,
1358 static struct clk_gate gxbb_vapb
= {
1359 .reg
= (void *)HHI_VAPBCLK_CNTL
,
1361 .lock
= &meson_clk_lock
,
1362 .hw
.init
= &(struct clk_init_data
) {
1364 .ops
= &clk_gate_ops
,
1365 .parent_names
= (const char *[]){ "vapb_sel" },
1367 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1371 /* Everything Else (EE) domain gates */
1372 static MESON_GATE(gxbb_ddr
, HHI_GCLK_MPEG0
, 0);
1373 static MESON_GATE(gxbb_dos
, HHI_GCLK_MPEG0
, 1);
1374 static MESON_GATE(gxbb_isa
, HHI_GCLK_MPEG0
, 5);
1375 static MESON_GATE(gxbb_pl301
, HHI_GCLK_MPEG0
, 6);
1376 static MESON_GATE(gxbb_periphs
, HHI_GCLK_MPEG0
, 7);
1377 static MESON_GATE(gxbb_spicc
, HHI_GCLK_MPEG0
, 8);
1378 static MESON_GATE(gxbb_i2c
, HHI_GCLK_MPEG0
, 9);
1379 static MESON_GATE(gxbb_sana
, HHI_GCLK_MPEG0
, 10);
1380 static MESON_GATE(gxbb_smart_card
, HHI_GCLK_MPEG0
, 11);
1381 static MESON_GATE(gxbb_rng0
, HHI_GCLK_MPEG0
, 12);
1382 static MESON_GATE(gxbb_uart0
, HHI_GCLK_MPEG0
, 13);
1383 static MESON_GATE(gxbb_sdhc
, HHI_GCLK_MPEG0
, 14);
1384 static MESON_GATE(gxbb_stream
, HHI_GCLK_MPEG0
, 15);
1385 static MESON_GATE(gxbb_async_fifo
, HHI_GCLK_MPEG0
, 16);
1386 static MESON_GATE(gxbb_sdio
, HHI_GCLK_MPEG0
, 17);
1387 static MESON_GATE(gxbb_abuf
, HHI_GCLK_MPEG0
, 18);
1388 static MESON_GATE(gxbb_hiu_iface
, HHI_GCLK_MPEG0
, 19);
1389 static MESON_GATE(gxbb_assist_misc
, HHI_GCLK_MPEG0
, 23);
1390 static MESON_GATE(gxbb_emmc_a
, HHI_GCLK_MPEG0
, 24);
1391 static MESON_GATE(gxbb_emmc_b
, HHI_GCLK_MPEG0
, 25);
1392 static MESON_GATE(gxbb_emmc_c
, HHI_GCLK_MPEG0
, 26);
1393 static MESON_GATE(gxbb_spi
, HHI_GCLK_MPEG0
, 30);
1395 static MESON_GATE(gxbb_i2s_spdif
, HHI_GCLK_MPEG1
, 2);
1396 static MESON_GATE(gxbb_eth
, HHI_GCLK_MPEG1
, 3);
1397 static MESON_GATE(gxbb_demux
, HHI_GCLK_MPEG1
, 4);
1398 static MESON_GATE(gxbb_aiu_glue
, HHI_GCLK_MPEG1
, 6);
1399 static MESON_GATE(gxbb_iec958
, HHI_GCLK_MPEG1
, 7);
1400 static MESON_GATE(gxbb_i2s_out
, HHI_GCLK_MPEG1
, 8);
1401 static MESON_GATE(gxbb_amclk
, HHI_GCLK_MPEG1
, 9);
1402 static MESON_GATE(gxbb_aififo2
, HHI_GCLK_MPEG1
, 10);
1403 static MESON_GATE(gxbb_mixer
, HHI_GCLK_MPEG1
, 11);
1404 static MESON_GATE(gxbb_mixer_iface
, HHI_GCLK_MPEG1
, 12);
1405 static MESON_GATE(gxbb_adc
, HHI_GCLK_MPEG1
, 13);
1406 static MESON_GATE(gxbb_blkmv
, HHI_GCLK_MPEG1
, 14);
1407 static MESON_GATE(gxbb_aiu
, HHI_GCLK_MPEG1
, 15);
1408 static MESON_GATE(gxbb_uart1
, HHI_GCLK_MPEG1
, 16);
1409 static MESON_GATE(gxbb_g2d
, HHI_GCLK_MPEG1
, 20);
1410 static MESON_GATE(gxbb_usb0
, HHI_GCLK_MPEG1
, 21);
1411 static MESON_GATE(gxbb_usb1
, HHI_GCLK_MPEG1
, 22);
1412 static MESON_GATE(gxbb_reset
, HHI_GCLK_MPEG1
, 23);
1413 static MESON_GATE(gxbb_nand
, HHI_GCLK_MPEG1
, 24);
1414 static MESON_GATE(gxbb_dos_parser
, HHI_GCLK_MPEG1
, 25);
1415 static MESON_GATE(gxbb_usb
, HHI_GCLK_MPEG1
, 26);
1416 static MESON_GATE(gxbb_vdin1
, HHI_GCLK_MPEG1
, 28);
1417 static MESON_GATE(gxbb_ahb_arb0
, HHI_GCLK_MPEG1
, 29);
1418 static MESON_GATE(gxbb_efuse
, HHI_GCLK_MPEG1
, 30);
1419 static MESON_GATE(gxbb_boot_rom
, HHI_GCLK_MPEG1
, 31);
1421 static MESON_GATE(gxbb_ahb_data_bus
, HHI_GCLK_MPEG2
, 1);
1422 static MESON_GATE(gxbb_ahb_ctrl_bus
, HHI_GCLK_MPEG2
, 2);
1423 static MESON_GATE(gxbb_hdmi_intr_sync
, HHI_GCLK_MPEG2
, 3);
1424 static MESON_GATE(gxbb_hdmi_pclk
, HHI_GCLK_MPEG2
, 4);
1425 static MESON_GATE(gxbb_usb1_ddr_bridge
, HHI_GCLK_MPEG2
, 8);
1426 static MESON_GATE(gxbb_usb0_ddr_bridge
, HHI_GCLK_MPEG2
, 9);
1427 static MESON_GATE(gxbb_mmc_pclk
, HHI_GCLK_MPEG2
, 11);
1428 static MESON_GATE(gxbb_dvin
, HHI_GCLK_MPEG2
, 12);
1429 static MESON_GATE(gxbb_uart2
, HHI_GCLK_MPEG2
, 15);
1430 static MESON_GATE(gxbb_sar_adc
, HHI_GCLK_MPEG2
, 22);
1431 static MESON_GATE(gxbb_vpu_intr
, HHI_GCLK_MPEG2
, 25);
1432 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge
, HHI_GCLK_MPEG2
, 26);
1433 static MESON_GATE(gxbb_clk81_a53
, HHI_GCLK_MPEG2
, 29);
1435 static MESON_GATE(gxbb_vclk2_venci0
, HHI_GCLK_OTHER
, 1);
1436 static MESON_GATE(gxbb_vclk2_venci1
, HHI_GCLK_OTHER
, 2);
1437 static MESON_GATE(gxbb_vclk2_vencp0
, HHI_GCLK_OTHER
, 3);
1438 static MESON_GATE(gxbb_vclk2_vencp1
, HHI_GCLK_OTHER
, 4);
1439 static MESON_GATE(gxbb_gclk_venci_int0
, HHI_GCLK_OTHER
, 8);
1440 static MESON_GATE(gxbb_gclk_vencp_int
, HHI_GCLK_OTHER
, 9);
1441 static MESON_GATE(gxbb_dac_clk
, HHI_GCLK_OTHER
, 10);
1442 static MESON_GATE(gxbb_aoclk_gate
, HHI_GCLK_OTHER
, 14);
1443 static MESON_GATE(gxbb_iec958_gate
, HHI_GCLK_OTHER
, 16);
1444 static MESON_GATE(gxbb_enc480p
, HHI_GCLK_OTHER
, 20);
1445 static MESON_GATE(gxbb_rng1
, HHI_GCLK_OTHER
, 21);
1446 static MESON_GATE(gxbb_gclk_venci_int1
, HHI_GCLK_OTHER
, 22);
1447 static MESON_GATE(gxbb_vclk2_venclmcc
, HHI_GCLK_OTHER
, 24);
1448 static MESON_GATE(gxbb_vclk2_vencl
, HHI_GCLK_OTHER
, 25);
1449 static MESON_GATE(gxbb_vclk_other
, HHI_GCLK_OTHER
, 26);
1450 static MESON_GATE(gxbb_edp
, HHI_GCLK_OTHER
, 31);
1452 /* Always On (AO) domain gates */
1454 static MESON_GATE(gxbb_ao_media_cpu
, HHI_GCLK_AO
, 0);
1455 static MESON_GATE(gxbb_ao_ahb_sram
, HHI_GCLK_AO
, 1);
1456 static MESON_GATE(gxbb_ao_ahb_bus
, HHI_GCLK_AO
, 2);
1457 static MESON_GATE(gxbb_ao_iface
, HHI_GCLK_AO
, 3);
1458 static MESON_GATE(gxbb_ao_i2c
, HHI_GCLK_AO
, 4);
1460 /* Array of all clocks provided by this provider */
1462 static struct clk_hw_onecell_data gxbb_hw_onecell_data
= {
1464 [CLKID_SYS_PLL
] = &gxbb_sys_pll
.hw
,
1465 [CLKID_HDMI_PLL
] = &gxbb_hdmi_pll
.hw
,
1466 [CLKID_FIXED_PLL
] = &gxbb_fixed_pll
.hw
,
1467 [CLKID_FCLK_DIV2
] = &gxbb_fclk_div2
.hw
,
1468 [CLKID_FCLK_DIV3
] = &gxbb_fclk_div3
.hw
,
1469 [CLKID_FCLK_DIV4
] = &gxbb_fclk_div4
.hw
,
1470 [CLKID_FCLK_DIV5
] = &gxbb_fclk_div5
.hw
,
1471 [CLKID_FCLK_DIV7
] = &gxbb_fclk_div7
.hw
,
1472 [CLKID_GP0_PLL
] = &gxbb_gp0_pll
.hw
,
1473 [CLKID_MPEG_SEL
] = &gxbb_mpeg_clk_sel
.hw
,
1474 [CLKID_MPEG_DIV
] = &gxbb_mpeg_clk_div
.hw
,
1475 [CLKID_CLK81
] = &gxbb_clk81
.hw
,
1476 [CLKID_MPLL0
] = &gxbb_mpll0
.hw
,
1477 [CLKID_MPLL1
] = &gxbb_mpll1
.hw
,
1478 [CLKID_MPLL2
] = &gxbb_mpll2
.hw
,
1479 [CLKID_DDR
] = &gxbb_ddr
.hw
,
1480 [CLKID_DOS
] = &gxbb_dos
.hw
,
1481 [CLKID_ISA
] = &gxbb_isa
.hw
,
1482 [CLKID_PL301
] = &gxbb_pl301
.hw
,
1483 [CLKID_PERIPHS
] = &gxbb_periphs
.hw
,
1484 [CLKID_SPICC
] = &gxbb_spicc
.hw
,
1485 [CLKID_I2C
] = &gxbb_i2c
.hw
,
1486 [CLKID_SAR_ADC
] = &gxbb_sar_adc
.hw
,
1487 [CLKID_SMART_CARD
] = &gxbb_smart_card
.hw
,
1488 [CLKID_RNG0
] = &gxbb_rng0
.hw
,
1489 [CLKID_UART0
] = &gxbb_uart0
.hw
,
1490 [CLKID_SDHC
] = &gxbb_sdhc
.hw
,
1491 [CLKID_STREAM
] = &gxbb_stream
.hw
,
1492 [CLKID_ASYNC_FIFO
] = &gxbb_async_fifo
.hw
,
1493 [CLKID_SDIO
] = &gxbb_sdio
.hw
,
1494 [CLKID_ABUF
] = &gxbb_abuf
.hw
,
1495 [CLKID_HIU_IFACE
] = &gxbb_hiu_iface
.hw
,
1496 [CLKID_ASSIST_MISC
] = &gxbb_assist_misc
.hw
,
1497 [CLKID_SPI
] = &gxbb_spi
.hw
,
1498 [CLKID_I2S_SPDIF
] = &gxbb_i2s_spdif
.hw
,
1499 [CLKID_ETH
] = &gxbb_eth
.hw
,
1500 [CLKID_DEMUX
] = &gxbb_demux
.hw
,
1501 [CLKID_AIU_GLUE
] = &gxbb_aiu_glue
.hw
,
1502 [CLKID_IEC958
] = &gxbb_iec958
.hw
,
1503 [CLKID_I2S_OUT
] = &gxbb_i2s_out
.hw
,
1504 [CLKID_AMCLK
] = &gxbb_amclk
.hw
,
1505 [CLKID_AIFIFO2
] = &gxbb_aififo2
.hw
,
1506 [CLKID_MIXER
] = &gxbb_mixer
.hw
,
1507 [CLKID_MIXER_IFACE
] = &gxbb_mixer_iface
.hw
,
1508 [CLKID_ADC
] = &gxbb_adc
.hw
,
1509 [CLKID_BLKMV
] = &gxbb_blkmv
.hw
,
1510 [CLKID_AIU
] = &gxbb_aiu
.hw
,
1511 [CLKID_UART1
] = &gxbb_uart1
.hw
,
1512 [CLKID_G2D
] = &gxbb_g2d
.hw
,
1513 [CLKID_USB0
] = &gxbb_usb0
.hw
,
1514 [CLKID_USB1
] = &gxbb_usb1
.hw
,
1515 [CLKID_RESET
] = &gxbb_reset
.hw
,
1516 [CLKID_NAND
] = &gxbb_nand
.hw
,
1517 [CLKID_DOS_PARSER
] = &gxbb_dos_parser
.hw
,
1518 [CLKID_USB
] = &gxbb_usb
.hw
,
1519 [CLKID_VDIN1
] = &gxbb_vdin1
.hw
,
1520 [CLKID_AHB_ARB0
] = &gxbb_ahb_arb0
.hw
,
1521 [CLKID_EFUSE
] = &gxbb_efuse
.hw
,
1522 [CLKID_BOOT_ROM
] = &gxbb_boot_rom
.hw
,
1523 [CLKID_AHB_DATA_BUS
] = &gxbb_ahb_data_bus
.hw
,
1524 [CLKID_AHB_CTRL_BUS
] = &gxbb_ahb_ctrl_bus
.hw
,
1525 [CLKID_HDMI_INTR_SYNC
] = &gxbb_hdmi_intr_sync
.hw
,
1526 [CLKID_HDMI_PCLK
] = &gxbb_hdmi_pclk
.hw
,
1527 [CLKID_USB1_DDR_BRIDGE
] = &gxbb_usb1_ddr_bridge
.hw
,
1528 [CLKID_USB0_DDR_BRIDGE
] = &gxbb_usb0_ddr_bridge
.hw
,
1529 [CLKID_MMC_PCLK
] = &gxbb_mmc_pclk
.hw
,
1530 [CLKID_DVIN
] = &gxbb_dvin
.hw
,
1531 [CLKID_UART2
] = &gxbb_uart2
.hw
,
1532 [CLKID_SANA
] = &gxbb_sana
.hw
,
1533 [CLKID_VPU_INTR
] = &gxbb_vpu_intr
.hw
,
1534 [CLKID_SEC_AHB_AHB3_BRIDGE
] = &gxbb_sec_ahb_ahb3_bridge
.hw
,
1535 [CLKID_CLK81_A53
] = &gxbb_clk81_a53
.hw
,
1536 [CLKID_VCLK2_VENCI0
] = &gxbb_vclk2_venci0
.hw
,
1537 [CLKID_VCLK2_VENCI1
] = &gxbb_vclk2_venci1
.hw
,
1538 [CLKID_VCLK2_VENCP0
] = &gxbb_vclk2_vencp0
.hw
,
1539 [CLKID_VCLK2_VENCP1
] = &gxbb_vclk2_vencp1
.hw
,
1540 [CLKID_GCLK_VENCI_INT0
] = &gxbb_gclk_venci_int0
.hw
,
1541 [CLKID_GCLK_VENCI_INT
] = &gxbb_gclk_vencp_int
.hw
,
1542 [CLKID_DAC_CLK
] = &gxbb_dac_clk
.hw
,
1543 [CLKID_AOCLK_GATE
] = &gxbb_aoclk_gate
.hw
,
1544 [CLKID_IEC958_GATE
] = &gxbb_iec958_gate
.hw
,
1545 [CLKID_ENC480P
] = &gxbb_enc480p
.hw
,
1546 [CLKID_RNG1
] = &gxbb_rng1
.hw
,
1547 [CLKID_GCLK_VENCI_INT1
] = &gxbb_gclk_venci_int1
.hw
,
1548 [CLKID_VCLK2_VENCLMCC
] = &gxbb_vclk2_venclmcc
.hw
,
1549 [CLKID_VCLK2_VENCL
] = &gxbb_vclk2_vencl
.hw
,
1550 [CLKID_VCLK_OTHER
] = &gxbb_vclk_other
.hw
,
1551 [CLKID_EDP
] = &gxbb_edp
.hw
,
1552 [CLKID_AO_MEDIA_CPU
] = &gxbb_ao_media_cpu
.hw
,
1553 [CLKID_AO_AHB_SRAM
] = &gxbb_ao_ahb_sram
.hw
,
1554 [CLKID_AO_AHB_BUS
] = &gxbb_ao_ahb_bus
.hw
,
1555 [CLKID_AO_IFACE
] = &gxbb_ao_iface
.hw
,
1556 [CLKID_AO_I2C
] = &gxbb_ao_i2c
.hw
,
1557 [CLKID_SD_EMMC_A
] = &gxbb_emmc_a
.hw
,
1558 [CLKID_SD_EMMC_B
] = &gxbb_emmc_b
.hw
,
1559 [CLKID_SD_EMMC_C
] = &gxbb_emmc_c
.hw
,
1560 [CLKID_SAR_ADC_CLK
] = &gxbb_sar_adc_clk
.hw
,
1561 [CLKID_SAR_ADC_SEL
] = &gxbb_sar_adc_clk_sel
.hw
,
1562 [CLKID_SAR_ADC_DIV
] = &gxbb_sar_adc_clk_div
.hw
,
1563 [CLKID_MALI_0_SEL
] = &gxbb_mali_0_sel
.hw
,
1564 [CLKID_MALI_0_DIV
] = &gxbb_mali_0_div
.hw
,
1565 [CLKID_MALI_0
] = &gxbb_mali_0
.hw
,
1566 [CLKID_MALI_1_SEL
] = &gxbb_mali_1_sel
.hw
,
1567 [CLKID_MALI_1_DIV
] = &gxbb_mali_1_div
.hw
,
1568 [CLKID_MALI_1
] = &gxbb_mali_1
.hw
,
1569 [CLKID_MALI
] = &gxbb_mali
.hw
,
1570 [CLKID_CTS_AMCLK
] = &gxbb_cts_amclk
.hw
,
1571 [CLKID_CTS_AMCLK_SEL
] = &gxbb_cts_amclk_sel
.hw
,
1572 [CLKID_CTS_AMCLK_DIV
] = &gxbb_cts_amclk_div
.hw
,
1573 [CLKID_CTS_MCLK_I958
] = &gxbb_cts_mclk_i958
.hw
,
1574 [CLKID_CTS_MCLK_I958_SEL
] = &gxbb_cts_mclk_i958_sel
.hw
,
1575 [CLKID_CTS_MCLK_I958_DIV
] = &gxbb_cts_mclk_i958_div
.hw
,
1576 [CLKID_CTS_I958
] = &gxbb_cts_i958
.hw
,
1577 [CLKID_32K_CLK
] = &gxbb_32k_clk
.hw
,
1578 [CLKID_32K_CLK_SEL
] = &gxbb_32k_clk_sel
.hw
,
1579 [CLKID_32K_CLK_DIV
] = &gxbb_32k_clk_div
.hw
,
1580 [CLKID_SD_EMMC_A_CLK0_SEL
] = &gxbb_sd_emmc_a_clk0_sel
.hw
,
1581 [CLKID_SD_EMMC_A_CLK0_DIV
] = &gxbb_sd_emmc_a_clk0_div
.hw
,
1582 [CLKID_SD_EMMC_A_CLK0
] = &gxbb_sd_emmc_a_clk0
.hw
,
1583 [CLKID_SD_EMMC_B_CLK0_SEL
] = &gxbb_sd_emmc_b_clk0_sel
.hw
,
1584 [CLKID_SD_EMMC_B_CLK0_DIV
] = &gxbb_sd_emmc_b_clk0_div
.hw
,
1585 [CLKID_SD_EMMC_B_CLK0
] = &gxbb_sd_emmc_b_clk0
.hw
,
1586 [CLKID_SD_EMMC_C_CLK0_SEL
] = &gxbb_sd_emmc_c_clk0_sel
.hw
,
1587 [CLKID_SD_EMMC_C_CLK0_DIV
] = &gxbb_sd_emmc_c_clk0_div
.hw
,
1588 [CLKID_SD_EMMC_C_CLK0
] = &gxbb_sd_emmc_c_clk0
.hw
,
1589 [CLKID_VPU_0_SEL
] = &gxbb_vpu_0_sel
.hw
,
1590 [CLKID_VPU_0_DIV
] = &gxbb_vpu_0_div
.hw
,
1591 [CLKID_VPU_0
] = &gxbb_vpu_0
.hw
,
1592 [CLKID_VPU_1_SEL
] = &gxbb_vpu_1_sel
.hw
,
1593 [CLKID_VPU_1_DIV
] = &gxbb_vpu_1_div
.hw
,
1594 [CLKID_VPU_1
] = &gxbb_vpu_1
.hw
,
1595 [CLKID_VPU
] = &gxbb_vpu
.hw
,
1596 [CLKID_VAPB_0_SEL
] = &gxbb_vapb_0_sel
.hw
,
1597 [CLKID_VAPB_0_DIV
] = &gxbb_vapb_0_div
.hw
,
1598 [CLKID_VAPB_0
] = &gxbb_vapb_0
.hw
,
1599 [CLKID_VAPB_1_SEL
] = &gxbb_vapb_1_sel
.hw
,
1600 [CLKID_VAPB_1_DIV
] = &gxbb_vapb_1_div
.hw
,
1601 [CLKID_VAPB_1
] = &gxbb_vapb_1
.hw
,
1602 [CLKID_VAPB_SEL
] = &gxbb_vapb_sel
.hw
,
1603 [CLKID_VAPB
] = &gxbb_vapb
.hw
,
1609 static struct clk_hw_onecell_data gxl_hw_onecell_data
= {
1611 [CLKID_SYS_PLL
] = &gxbb_sys_pll
.hw
,
1612 [CLKID_HDMI_PLL
] = &gxbb_hdmi_pll
.hw
,
1613 [CLKID_FIXED_PLL
] = &gxbb_fixed_pll
.hw
,
1614 [CLKID_FCLK_DIV2
] = &gxbb_fclk_div2
.hw
,
1615 [CLKID_FCLK_DIV3
] = &gxbb_fclk_div3
.hw
,
1616 [CLKID_FCLK_DIV4
] = &gxbb_fclk_div4
.hw
,
1617 [CLKID_FCLK_DIV5
] = &gxbb_fclk_div5
.hw
,
1618 [CLKID_FCLK_DIV7
] = &gxbb_fclk_div7
.hw
,
1619 [CLKID_GP0_PLL
] = &gxl_gp0_pll
.hw
,
1620 [CLKID_MPEG_SEL
] = &gxbb_mpeg_clk_sel
.hw
,
1621 [CLKID_MPEG_DIV
] = &gxbb_mpeg_clk_div
.hw
,
1622 [CLKID_CLK81
] = &gxbb_clk81
.hw
,
1623 [CLKID_MPLL0
] = &gxbb_mpll0
.hw
,
1624 [CLKID_MPLL1
] = &gxbb_mpll1
.hw
,
1625 [CLKID_MPLL2
] = &gxbb_mpll2
.hw
,
1626 [CLKID_DDR
] = &gxbb_ddr
.hw
,
1627 [CLKID_DOS
] = &gxbb_dos
.hw
,
1628 [CLKID_ISA
] = &gxbb_isa
.hw
,
1629 [CLKID_PL301
] = &gxbb_pl301
.hw
,
1630 [CLKID_PERIPHS
] = &gxbb_periphs
.hw
,
1631 [CLKID_SPICC
] = &gxbb_spicc
.hw
,
1632 [CLKID_I2C
] = &gxbb_i2c
.hw
,
1633 [CLKID_SAR_ADC
] = &gxbb_sar_adc
.hw
,
1634 [CLKID_SMART_CARD
] = &gxbb_smart_card
.hw
,
1635 [CLKID_RNG0
] = &gxbb_rng0
.hw
,
1636 [CLKID_UART0
] = &gxbb_uart0
.hw
,
1637 [CLKID_SDHC
] = &gxbb_sdhc
.hw
,
1638 [CLKID_STREAM
] = &gxbb_stream
.hw
,
1639 [CLKID_ASYNC_FIFO
] = &gxbb_async_fifo
.hw
,
1640 [CLKID_SDIO
] = &gxbb_sdio
.hw
,
1641 [CLKID_ABUF
] = &gxbb_abuf
.hw
,
1642 [CLKID_HIU_IFACE
] = &gxbb_hiu_iface
.hw
,
1643 [CLKID_ASSIST_MISC
] = &gxbb_assist_misc
.hw
,
1644 [CLKID_SPI
] = &gxbb_spi
.hw
,
1645 [CLKID_I2S_SPDIF
] = &gxbb_i2s_spdif
.hw
,
1646 [CLKID_ETH
] = &gxbb_eth
.hw
,
1647 [CLKID_DEMUX
] = &gxbb_demux
.hw
,
1648 [CLKID_AIU_GLUE
] = &gxbb_aiu_glue
.hw
,
1649 [CLKID_IEC958
] = &gxbb_iec958
.hw
,
1650 [CLKID_I2S_OUT
] = &gxbb_i2s_out
.hw
,
1651 [CLKID_AMCLK
] = &gxbb_amclk
.hw
,
1652 [CLKID_AIFIFO2
] = &gxbb_aififo2
.hw
,
1653 [CLKID_MIXER
] = &gxbb_mixer
.hw
,
1654 [CLKID_MIXER_IFACE
] = &gxbb_mixer_iface
.hw
,
1655 [CLKID_ADC
] = &gxbb_adc
.hw
,
1656 [CLKID_BLKMV
] = &gxbb_blkmv
.hw
,
1657 [CLKID_AIU
] = &gxbb_aiu
.hw
,
1658 [CLKID_UART1
] = &gxbb_uart1
.hw
,
1659 [CLKID_G2D
] = &gxbb_g2d
.hw
,
1660 [CLKID_USB0
] = &gxbb_usb0
.hw
,
1661 [CLKID_USB1
] = &gxbb_usb1
.hw
,
1662 [CLKID_RESET
] = &gxbb_reset
.hw
,
1663 [CLKID_NAND
] = &gxbb_nand
.hw
,
1664 [CLKID_DOS_PARSER
] = &gxbb_dos_parser
.hw
,
1665 [CLKID_USB
] = &gxbb_usb
.hw
,
1666 [CLKID_VDIN1
] = &gxbb_vdin1
.hw
,
1667 [CLKID_AHB_ARB0
] = &gxbb_ahb_arb0
.hw
,
1668 [CLKID_EFUSE
] = &gxbb_efuse
.hw
,
1669 [CLKID_BOOT_ROM
] = &gxbb_boot_rom
.hw
,
1670 [CLKID_AHB_DATA_BUS
] = &gxbb_ahb_data_bus
.hw
,
1671 [CLKID_AHB_CTRL_BUS
] = &gxbb_ahb_ctrl_bus
.hw
,
1672 [CLKID_HDMI_INTR_SYNC
] = &gxbb_hdmi_intr_sync
.hw
,
1673 [CLKID_HDMI_PCLK
] = &gxbb_hdmi_pclk
.hw
,
1674 [CLKID_USB1_DDR_BRIDGE
] = &gxbb_usb1_ddr_bridge
.hw
,
1675 [CLKID_USB0_DDR_BRIDGE
] = &gxbb_usb0_ddr_bridge
.hw
,
1676 [CLKID_MMC_PCLK
] = &gxbb_mmc_pclk
.hw
,
1677 [CLKID_DVIN
] = &gxbb_dvin
.hw
,
1678 [CLKID_UART2
] = &gxbb_uart2
.hw
,
1679 [CLKID_SANA
] = &gxbb_sana
.hw
,
1680 [CLKID_VPU_INTR
] = &gxbb_vpu_intr
.hw
,
1681 [CLKID_SEC_AHB_AHB3_BRIDGE
] = &gxbb_sec_ahb_ahb3_bridge
.hw
,
1682 [CLKID_CLK81_A53
] = &gxbb_clk81_a53
.hw
,
1683 [CLKID_VCLK2_VENCI0
] = &gxbb_vclk2_venci0
.hw
,
1684 [CLKID_VCLK2_VENCI1
] = &gxbb_vclk2_venci1
.hw
,
1685 [CLKID_VCLK2_VENCP0
] = &gxbb_vclk2_vencp0
.hw
,
1686 [CLKID_VCLK2_VENCP1
] = &gxbb_vclk2_vencp1
.hw
,
1687 [CLKID_GCLK_VENCI_INT0
] = &gxbb_gclk_venci_int0
.hw
,
1688 [CLKID_GCLK_VENCI_INT
] = &gxbb_gclk_vencp_int
.hw
,
1689 [CLKID_DAC_CLK
] = &gxbb_dac_clk
.hw
,
1690 [CLKID_AOCLK_GATE
] = &gxbb_aoclk_gate
.hw
,
1691 [CLKID_IEC958_GATE
] = &gxbb_iec958_gate
.hw
,
1692 [CLKID_ENC480P
] = &gxbb_enc480p
.hw
,
1693 [CLKID_RNG1
] = &gxbb_rng1
.hw
,
1694 [CLKID_GCLK_VENCI_INT1
] = &gxbb_gclk_venci_int1
.hw
,
1695 [CLKID_VCLK2_VENCLMCC
] = &gxbb_vclk2_venclmcc
.hw
,
1696 [CLKID_VCLK2_VENCL
] = &gxbb_vclk2_vencl
.hw
,
1697 [CLKID_VCLK_OTHER
] = &gxbb_vclk_other
.hw
,
1698 [CLKID_EDP
] = &gxbb_edp
.hw
,
1699 [CLKID_AO_MEDIA_CPU
] = &gxbb_ao_media_cpu
.hw
,
1700 [CLKID_AO_AHB_SRAM
] = &gxbb_ao_ahb_sram
.hw
,
1701 [CLKID_AO_AHB_BUS
] = &gxbb_ao_ahb_bus
.hw
,
1702 [CLKID_AO_IFACE
] = &gxbb_ao_iface
.hw
,
1703 [CLKID_AO_I2C
] = &gxbb_ao_i2c
.hw
,
1704 [CLKID_SD_EMMC_A
] = &gxbb_emmc_a
.hw
,
1705 [CLKID_SD_EMMC_B
] = &gxbb_emmc_b
.hw
,
1706 [CLKID_SD_EMMC_C
] = &gxbb_emmc_c
.hw
,
1707 [CLKID_SAR_ADC_CLK
] = &gxbb_sar_adc_clk
.hw
,
1708 [CLKID_SAR_ADC_SEL
] = &gxbb_sar_adc_clk_sel
.hw
,
1709 [CLKID_SAR_ADC_DIV
] = &gxbb_sar_adc_clk_div
.hw
,
1710 [CLKID_MALI_0_SEL
] = &gxbb_mali_0_sel
.hw
,
1711 [CLKID_MALI_0_DIV
] = &gxbb_mali_0_div
.hw
,
1712 [CLKID_MALI_0
] = &gxbb_mali_0
.hw
,
1713 [CLKID_MALI_1_SEL
] = &gxbb_mali_1_sel
.hw
,
1714 [CLKID_MALI_1_DIV
] = &gxbb_mali_1_div
.hw
,
1715 [CLKID_MALI_1
] = &gxbb_mali_1
.hw
,
1716 [CLKID_MALI
] = &gxbb_mali
.hw
,
1717 [CLKID_CTS_AMCLK
] = &gxbb_cts_amclk
.hw
,
1718 [CLKID_CTS_AMCLK_SEL
] = &gxbb_cts_amclk_sel
.hw
,
1719 [CLKID_CTS_AMCLK_DIV
] = &gxbb_cts_amclk_div
.hw
,
1720 [CLKID_CTS_MCLK_I958
] = &gxbb_cts_mclk_i958
.hw
,
1721 [CLKID_CTS_MCLK_I958_SEL
] = &gxbb_cts_mclk_i958_sel
.hw
,
1722 [CLKID_CTS_MCLK_I958_DIV
] = &gxbb_cts_mclk_i958_div
.hw
,
1723 [CLKID_CTS_I958
] = &gxbb_cts_i958
.hw
,
1724 [CLKID_32K_CLK
] = &gxbb_32k_clk
.hw
,
1725 [CLKID_32K_CLK_SEL
] = &gxbb_32k_clk_sel
.hw
,
1726 [CLKID_32K_CLK_DIV
] = &gxbb_32k_clk_div
.hw
,
1727 [CLKID_SD_EMMC_A_CLK0_SEL
] = &gxbb_sd_emmc_a_clk0_sel
.hw
,
1728 [CLKID_SD_EMMC_A_CLK0_DIV
] = &gxbb_sd_emmc_a_clk0_div
.hw
,
1729 [CLKID_SD_EMMC_A_CLK0
] = &gxbb_sd_emmc_a_clk0
.hw
,
1730 [CLKID_SD_EMMC_B_CLK0_SEL
] = &gxbb_sd_emmc_b_clk0_sel
.hw
,
1731 [CLKID_SD_EMMC_B_CLK0_DIV
] = &gxbb_sd_emmc_b_clk0_div
.hw
,
1732 [CLKID_SD_EMMC_B_CLK0
] = &gxbb_sd_emmc_b_clk0
.hw
,
1733 [CLKID_SD_EMMC_C_CLK0_SEL
] = &gxbb_sd_emmc_c_clk0_sel
.hw
,
1734 [CLKID_SD_EMMC_C_CLK0_DIV
] = &gxbb_sd_emmc_c_clk0_div
.hw
,
1735 [CLKID_SD_EMMC_C_CLK0
] = &gxbb_sd_emmc_c_clk0
.hw
,
1736 [CLKID_VPU_0_SEL
] = &gxbb_vpu_0_sel
.hw
,
1737 [CLKID_VPU_0_DIV
] = &gxbb_vpu_0_div
.hw
,
1738 [CLKID_VPU_0
] = &gxbb_vpu_0
.hw
,
1739 [CLKID_VPU_1_SEL
] = &gxbb_vpu_1_sel
.hw
,
1740 [CLKID_VPU_1_DIV
] = &gxbb_vpu_1_div
.hw
,
1741 [CLKID_VPU_1
] = &gxbb_vpu_1
.hw
,
1742 [CLKID_VPU
] = &gxbb_vpu
.hw
,
1743 [CLKID_VAPB_0_SEL
] = &gxbb_vapb_0_sel
.hw
,
1744 [CLKID_VAPB_0_DIV
] = &gxbb_vapb_0_div
.hw
,
1745 [CLKID_VAPB_0
] = &gxbb_vapb_0
.hw
,
1746 [CLKID_VAPB_1_SEL
] = &gxbb_vapb_1_sel
.hw
,
1747 [CLKID_VAPB_1_DIV
] = &gxbb_vapb_1_div
.hw
,
1748 [CLKID_VAPB_1
] = &gxbb_vapb_1
.hw
,
1749 [CLKID_VAPB_SEL
] = &gxbb_vapb_sel
.hw
,
1750 [CLKID_VAPB
] = &gxbb_vapb
.hw
,
1756 /* Convenience tables to populate base addresses in .probe */
1758 static struct meson_clk_pll
*const gxbb_clk_plls
[] = {
1765 static struct meson_clk_pll
*const gxl_clk_plls
[] = {
1772 static struct meson_clk_mpll
*const gxbb_clk_mplls
[] = {
1778 static struct clk_gate
*const gxbb_clk_gates
[] = {
1826 &gxbb_hdmi_intr_sync
,
1828 &gxbb_usb1_ddr_bridge
,
1829 &gxbb_usb0_ddr_bridge
,
1835 &gxbb_sec_ahb_ahb3_bridge
,
1841 &gxbb_gclk_venci_int0
,
1842 &gxbb_gclk_vencp_int
,
1848 &gxbb_gclk_venci_int1
,
1849 &gxbb_vclk2_venclmcc
,
1865 &gxbb_cts_mclk_i958
,
1867 &gxbb_sd_emmc_a_clk0
,
1868 &gxbb_sd_emmc_b_clk0
,
1869 &gxbb_sd_emmc_c_clk0
,
1877 static struct clk_mux
*const gxbb_clk_muxes
[] = {
1879 &gxbb_sar_adc_clk_sel
,
1883 &gxbb_cts_amclk_sel
,
1884 &gxbb_cts_mclk_i958_sel
,
1887 &gxbb_sd_emmc_a_clk0_sel
,
1888 &gxbb_sd_emmc_b_clk0_sel
,
1889 &gxbb_sd_emmc_c_clk0_sel
,
1898 static struct clk_divider
*const gxbb_clk_dividers
[] = {
1900 &gxbb_sar_adc_clk_div
,
1903 &gxbb_cts_mclk_i958_div
,
1905 &gxbb_sd_emmc_a_clk0_div
,
1906 &gxbb_sd_emmc_b_clk0_div
,
1907 &gxbb_sd_emmc_c_clk0_div
,
1914 static struct meson_clk_audio_divider
*const gxbb_audio_dividers
[] = {
1915 &gxbb_cts_amclk_div
,
1919 struct clk_gate
*const *clk_gates
;
1920 unsigned int clk_gates_count
;
1921 struct meson_clk_mpll
*const *clk_mplls
;
1922 unsigned int clk_mplls_count
;
1923 struct meson_clk_pll
*const *clk_plls
;
1924 unsigned int clk_plls_count
;
1925 struct clk_mux
*const *clk_muxes
;
1926 unsigned int clk_muxes_count
;
1927 struct clk_divider
*const *clk_dividers
;
1928 unsigned int clk_dividers_count
;
1929 struct meson_clk_audio_divider
*const *clk_audio_dividers
;
1930 unsigned int clk_audio_dividers_count
;
1931 struct clk_hw_onecell_data
*hw_onecell_data
;
1934 static const struct clkc_data gxbb_clkc_data
= {
1935 .clk_gates
= gxbb_clk_gates
,
1936 .clk_gates_count
= ARRAY_SIZE(gxbb_clk_gates
),
1937 .clk_mplls
= gxbb_clk_mplls
,
1938 .clk_mplls_count
= ARRAY_SIZE(gxbb_clk_mplls
),
1939 .clk_plls
= gxbb_clk_plls
,
1940 .clk_plls_count
= ARRAY_SIZE(gxbb_clk_plls
),
1941 .clk_muxes
= gxbb_clk_muxes
,
1942 .clk_muxes_count
= ARRAY_SIZE(gxbb_clk_muxes
),
1943 .clk_dividers
= gxbb_clk_dividers
,
1944 .clk_dividers_count
= ARRAY_SIZE(gxbb_clk_dividers
),
1945 .clk_audio_dividers
= gxbb_audio_dividers
,
1946 .clk_audio_dividers_count
= ARRAY_SIZE(gxbb_audio_dividers
),
1947 .hw_onecell_data
= &gxbb_hw_onecell_data
,
1950 static const struct clkc_data gxl_clkc_data
= {
1951 .clk_gates
= gxbb_clk_gates
,
1952 .clk_gates_count
= ARRAY_SIZE(gxbb_clk_gates
),
1953 .clk_mplls
= gxbb_clk_mplls
,
1954 .clk_mplls_count
= ARRAY_SIZE(gxbb_clk_mplls
),
1955 .clk_plls
= gxl_clk_plls
,
1956 .clk_plls_count
= ARRAY_SIZE(gxl_clk_plls
),
1957 .clk_muxes
= gxbb_clk_muxes
,
1958 .clk_muxes_count
= ARRAY_SIZE(gxbb_clk_muxes
),
1959 .clk_dividers
= gxbb_clk_dividers
,
1960 .clk_dividers_count
= ARRAY_SIZE(gxbb_clk_dividers
),
1961 .clk_audio_dividers
= gxbb_audio_dividers
,
1962 .clk_audio_dividers_count
= ARRAY_SIZE(gxbb_audio_dividers
),
1963 .hw_onecell_data
= &gxl_hw_onecell_data
,
1966 static const struct of_device_id clkc_match_table
[] = {
1967 { .compatible
= "amlogic,gxbb-clkc", .data
= &gxbb_clkc_data
},
1968 { .compatible
= "amlogic,gxl-clkc", .data
= &gxl_clkc_data
},
1972 static int gxbb_clkc_probe(struct platform_device
*pdev
)
1974 const struct clkc_data
*clkc_data
;
1975 void __iomem
*clk_base
;
1977 struct device
*dev
= &pdev
->dev
;
1979 clkc_data
= of_device_get_match_data(&pdev
->dev
);
1983 /* Generic clocks and PLLs */
1984 clk_base
= of_iomap(dev
->of_node
, 0);
1986 pr_err("%s: Unable to map clk base\n", __func__
);
1990 /* Populate base address for PLLs */
1991 for (i
= 0; i
< clkc_data
->clk_plls_count
; i
++)
1992 clkc_data
->clk_plls
[i
]->base
= clk_base
;
1994 /* Populate base address for MPLLs */
1995 for (i
= 0; i
< clkc_data
->clk_mplls_count
; i
++)
1996 clkc_data
->clk_mplls
[i
]->base
= clk_base
;
1998 /* Populate base address for gates */
1999 for (i
= 0; i
< clkc_data
->clk_gates_count
; i
++)
2000 clkc_data
->clk_gates
[i
]->reg
= clk_base
+
2001 (u64
)clkc_data
->clk_gates
[i
]->reg
;
2003 /* Populate base address for muxes */
2004 for (i
= 0; i
< clkc_data
->clk_muxes_count
; i
++)
2005 clkc_data
->clk_muxes
[i
]->reg
= clk_base
+
2006 (u64
)clkc_data
->clk_muxes
[i
]->reg
;
2008 /* Populate base address for dividers */
2009 for (i
= 0; i
< clkc_data
->clk_dividers_count
; i
++)
2010 clkc_data
->clk_dividers
[i
]->reg
= clk_base
+
2011 (u64
)clkc_data
->clk_dividers
[i
]->reg
;
2013 /* Populate base address for the audio dividers */
2014 for (i
= 0; i
< clkc_data
->clk_audio_dividers_count
; i
++)
2015 clkc_data
->clk_audio_dividers
[i
]->base
= clk_base
;
2020 for (clkid
= 0; clkid
< clkc_data
->hw_onecell_data
->num
; clkid
++) {
2021 /* array might be sparse */
2022 if (!clkc_data
->hw_onecell_data
->hws
[clkid
])
2025 ret
= devm_clk_hw_register(dev
,
2026 clkc_data
->hw_onecell_data
->hws
[clkid
]);
2031 return of_clk_add_hw_provider(dev
->of_node
, of_clk_hw_onecell_get
,
2032 clkc_data
->hw_onecell_data
);
2039 static struct platform_driver gxbb_driver
= {
2040 .probe
= gxbb_clkc_probe
,
2042 .name
= "gxbb-clkc",
2043 .of_match_table
= clkc_match_table
,
2047 builtin_platform_driver(gxbb_driver
);