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Linux 4.16.11
[linux/fpc-iii.git] / drivers / clk / mvebu / armada-37xx-periph.c
blob87213ea7fc84f32690d0849c6006b86882636a27
1 /*
2 * Marvell Armada 37xx SoC Peripheral clocks
3 *
4 * Copyright (C) 2016 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
11 *
12 * Most of the peripheral clocks can be modelled like this:
13 * _____ _______ _______
14 * TBG-A-P --| | | | | | ______
15 * TBG-B-P --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk
16 * TBG-A-S --| | | | | | |______|
17 * TBG-B-S --|_____| |_______| |_______|
18 *
19 * However some clocks may use only one or two block or and use the
20 * xtal clock as parent.
21 */
22
23 #include <linux/clk-provider.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/regmap.h>
29 #include <linux/slab.h>
30
31 #define TBG_SEL 0x0
32 #define DIV_SEL0 0x4
33 #define DIV_SEL1 0x8
34 #define DIV_SEL2 0xC
35 #define CLK_SEL 0x10
36 #define CLK_DIS 0x14
37
38 #define LOAD_LEVEL_NR 4
39
40 #define ARMADA_37XX_NB_L0L1 0x18
41 #define ARMADA_37XX_NB_L2L3 0x1C
42 #define ARMADA_37XX_NB_TBG_DIV_OFF 13
43 #define ARMADA_37XX_NB_TBG_DIV_MASK 0x7
44 #define ARMADA_37XX_NB_CLK_SEL_OFF 11
45 #define ARMADA_37XX_NB_CLK_SEL_MASK 0x1
46 #define ARMADA_37XX_NB_TBG_SEL_OFF 9
47 #define ARMADA_37XX_NB_TBG_SEL_MASK 0x3
48 #define ARMADA_37XX_NB_CONFIG_SHIFT 16
49 #define ARMADA_37XX_NB_DYN_MOD 0x24
50 #define ARMADA_37XX_NB_DFS_EN 31
51 #define ARMADA_37XX_NB_CPU_LOAD 0x30
52 #define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3
53 #define ARMADA_37XX_DVFS_LOAD_0 0
54 #define ARMADA_37XX_DVFS_LOAD_1 1
55 #define ARMADA_37XX_DVFS_LOAD_2 2
56 #define ARMADA_37XX_DVFS_LOAD_3 3
57
58 struct clk_periph_driver_data {
59 struct clk_hw_onecell_data *hw_data;
60 spinlock_t lock;
61 };
62
63 struct clk_double_div {
64 struct clk_hw hw;
65 void __iomem *reg1;
66 u8 shift1;
67 void __iomem *reg2;
68 u8 shift2;
69 };
70
71 struct clk_pm_cpu {
72 struct clk_hw hw;
73 void __iomem *reg_mux;
74 u8 shift_mux;
75 u32 mask_mux;
76 void __iomem *reg_div;
77 u8 shift_div;
78 struct regmap *nb_pm_base;
79 };
80
81 #define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw)
82 #define to_clk_pm_cpu(_hw) container_of(_hw, struct clk_pm_cpu, hw)
83
84 struct clk_periph_data {
85 const char *name;
86 const char * const *parent_names;
87 int num_parents;
88 struct clk_hw *mux_hw;
89 struct clk_hw *rate_hw;
90 struct clk_hw *gate_hw;
91 struct clk_hw *muxrate_hw;
92 bool is_double_div;
93 };
94
95 static const struct clk_div_table clk_table6[] = {
96 { .val = 1, .div = 1, },
97 { .val = 2, .div = 2, },
98 { .val = 3, .div = 3, },
99 { .val = 4, .div = 4, },
100 { .val = 5, .div = 5, },
101 { .val = 6, .div = 6, },
102 { .val = 0, .div = 0, }, /* last entry */
103 };
104
105 static const struct clk_div_table clk_table1[] = {
106 { .val = 0, .div = 1, },
107 { .val = 1, .div = 2, },
108 { .val = 0, .div = 0, }, /* last entry */
109 };
110
111 static const struct clk_div_table clk_table2[] = {
112 { .val = 0, .div = 2, },
113 { .val = 1, .div = 4, },
114 { .val = 0, .div = 0, }, /* last entry */
115 };
116
117 static const struct clk_ops clk_double_div_ops;
118 static const struct clk_ops clk_pm_cpu_ops;
119
120 #define PERIPH_GATE(_name, _bit) \
121 struct clk_gate gate_##_name = { \
122 .reg = (void *)CLK_DIS, \
123 .bit_idx = _bit, \
124 .hw.init = &(struct clk_init_data){ \
125 .ops = &clk_gate_ops, \
126 } \
127 };
128
129 #define PERIPH_MUX(_name, _shift) \
130 struct clk_mux mux_##_name = { \
131 .reg = (void *)TBG_SEL, \
132 .shift = _shift, \
133 .mask = 3, \
134 .hw.init = &(struct clk_init_data){ \
135 .ops = &clk_mux_ro_ops, \
136 } \
137 };
138
139 #define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \
140 struct clk_double_div rate_##_name = { \
141 .reg1 = (void *)_reg1, \
142 .reg2 = (void *)_reg2, \
143 .shift1 = _shift1, \
144 .shift2 = _shift2, \
145 .hw.init = &(struct clk_init_data){ \
146 .ops = &clk_double_div_ops, \
147 } \
148 };
149
150 #define PERIPH_DIV(_name, _reg, _shift, _table) \
151 struct clk_divider rate_##_name = { \
152 .reg = (void *)_reg, \
153 .table = _table, \
154 .shift = _shift, \
155 .hw.init = &(struct clk_init_data){ \
156 .ops = &clk_divider_ro_ops, \
157 } \
158 };
159
160 #define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \
161 struct clk_pm_cpu muxrate_##_name = { \
162 .reg_mux = (void *)TBG_SEL, \
163 .mask_mux = 3, \
164 .shift_mux = _shift1, \
165 .reg_div = (void *)_reg, \
166 .shift_div = _shift2, \
167 .hw.init = &(struct clk_init_data){ \
168 .ops = &clk_pm_cpu_ops, \
169 } \
170 };
171
172 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\
173 static PERIPH_GATE(_name, _bit); \
174 static PERIPH_MUX(_name, _shift); \
175 static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
176
177 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \
178 static PERIPH_GATE(_name, _bit); \
179 static PERIPH_MUX(_name, _shift); \
180 static PERIPH_DIV(_name, _reg, _shift1, _table);
181
182 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \
183 static PERIPH_GATE(_name, _bit); \
184 static PERIPH_DIV(_name, _reg, _shift, _table);
185
186 #define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\
187 static PERIPH_MUX(_name, _shift); \
188 static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
189
190 #define REF_CLK_FULL(_name) \
191 { .name = #_name, \
192 .parent_names = (const char *[]){ "TBG-A-P", \
193 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
194 .num_parents = 4, \
195 .mux_hw = &mux_##_name.hw, \
196 .gate_hw = &gate_##_name.hw, \
197 .rate_hw = &rate_##_name.hw, \
198 }
199
200 #define REF_CLK_FULL_DD(_name) \
201 { .name = #_name, \
202 .parent_names = (const char *[]){ "TBG-A-P", \
203 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
204 .num_parents = 4, \
205 .mux_hw = &mux_##_name.hw, \
206 .gate_hw = &gate_##_name.hw, \
207 .rate_hw = &rate_##_name.hw, \
208 .is_double_div = true, \
209 }
210
211 #define REF_CLK_GATE(_name, _parent_name) \
212 { .name = #_name, \
213 .parent_names = (const char *[]){ _parent_name}, \
214 .num_parents = 1, \
215 .gate_hw = &gate_##_name.hw, \
216 }
217
218 #define REF_CLK_GATE_DIV(_name, _parent_name) \
219 { .name = #_name, \
220 .parent_names = (const char *[]){ _parent_name}, \
221 .num_parents = 1, \
222 .gate_hw = &gate_##_name.hw, \
223 .rate_hw = &rate_##_name.hw, \
224 }
225
226 #define REF_CLK_PM_CPU(_name) \
227 { .name = #_name, \
228 .parent_names = (const char *[]){ "TBG-A-P", \
229 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
230 .num_parents = 4, \
231 .muxrate_hw = &muxrate_##_name.hw, \
232 }
233
234 #define REF_CLK_MUX_DD(_name) \
235 { .name = #_name, \
236 .parent_names = (const char *[]){ "TBG-A-P", \
237 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
238 .num_parents = 4, \
239 .mux_hw = &mux_##_name.hw, \
240 .rate_hw = &rate_##_name.hw, \
241 .is_double_div = true, \
242 }
243
244 /* NB periph clocks */
245 PERIPH_CLK_FULL_DD(mmc, 2, 0, DIV_SEL2, DIV_SEL2, 16, 13);
246 PERIPH_CLK_FULL_DD(sata_host, 3, 2, DIV_SEL2, DIV_SEL2, 10, 7);
247 PERIPH_CLK_FULL_DD(sec_at, 6, 4, DIV_SEL1, DIV_SEL1, 3, 0);
248 PERIPH_CLK_FULL_DD(sec_dap, 7, 6, DIV_SEL1, DIV_SEL1, 9, 6);
249 PERIPH_CLK_FULL_DD(tscem, 8, 8, DIV_SEL1, DIV_SEL1, 15, 12);
250 PERIPH_CLK_FULL(tscem_tmx, 10, 10, DIV_SEL1, 18, clk_table6);
251 static PERIPH_GATE(avs, 11);
252 PERIPH_CLK_FULL_DD(pwm, 13, 14, DIV_SEL0, DIV_SEL0, 3, 0);
253 PERIPH_CLK_FULL_DD(sqf, 12, 12, DIV_SEL1, DIV_SEL1, 27, 24);
254 static PERIPH_GATE(i2c_2, 16);
255 static PERIPH_GATE(i2c_1, 17);
256 PERIPH_CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, clk_table2);
257 PERIPH_CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12);
258 PERIPH_CLK_FULL(trace, 22, 18, DIV_SEL0, 20, clk_table6);
259 PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL0, 23, clk_table6);
260 PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19);
261 static PERIPH_PM_CPU(cpu, 22, DIV_SEL0, 28);
262
263 static struct clk_periph_data data_nb[] = {
264 REF_CLK_FULL_DD(mmc),
265 REF_CLK_FULL_DD(sata_host),
266 REF_CLK_FULL_DD(sec_at),
267 REF_CLK_FULL_DD(sec_dap),
268 REF_CLK_FULL_DD(tscem),
269 REF_CLK_FULL(tscem_tmx),
270 REF_CLK_GATE(avs, "xtal"),
271 REF_CLK_FULL_DD(sqf),
272 REF_CLK_FULL_DD(pwm),
273 REF_CLK_GATE(i2c_2, "xtal"),
274 REF_CLK_GATE(i2c_1, "xtal"),
275 REF_CLK_GATE_DIV(ddr_phy, "TBG-A-S"),
276 REF_CLK_FULL_DD(ddr_fclk),
277 REF_CLK_FULL(trace),
278 REF_CLK_FULL(counter),
279 REF_CLK_FULL_DD(eip97),
280 REF_CLK_PM_CPU(cpu),
281 { },
282 };
283
284 /* SB periph clocks */
285 PERIPH_CLK_MUX_DD(gbe_50, 6, DIV_SEL2, DIV_SEL2, 6, 9);
286 PERIPH_CLK_MUX_DD(gbe_core, 8, DIV_SEL1, DIV_SEL1, 18, 21);
287 PERIPH_CLK_MUX_DD(gbe_125, 10, DIV_SEL1, DIV_SEL1, 6, 9);
288 static PERIPH_GATE(gbe1_50, 0);
289 static PERIPH_GATE(gbe0_50, 1);
290 static PERIPH_GATE(gbe1_125, 2);
291 static PERIPH_GATE(gbe0_125, 3);
292 PERIPH_CLK_GATE_DIV(gbe1_core, 4, DIV_SEL1, 13, clk_table1);
293 PERIPH_CLK_GATE_DIV(gbe0_core, 5, DIV_SEL1, 14, clk_table1);
294 PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1);
295 PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6);
296 PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12);
297 PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18);
298
299 static struct clk_periph_data data_sb[] = {
300 REF_CLK_MUX_DD(gbe_50),
301 REF_CLK_MUX_DD(gbe_core),
302 REF_CLK_MUX_DD(gbe_125),
303 REF_CLK_GATE(gbe1_50, "gbe_50"),
304 REF_CLK_GATE(gbe0_50, "gbe_50"),
305 REF_CLK_GATE(gbe1_125, "gbe_125"),
306 REF_CLK_GATE(gbe0_125, "gbe_125"),
307 REF_CLK_GATE_DIV(gbe1_core, "gbe_core"),
308 REF_CLK_GATE_DIV(gbe0_core, "gbe_core"),
309 REF_CLK_GATE_DIV(gbe_bm, "gbe_core"),
310 REF_CLK_FULL_DD(sdio),
311 REF_CLK_FULL_DD(usb32_usb2_sys),
312 REF_CLK_FULL_DD(usb32_ss_sys),
313 { },
314 };
315
316 static unsigned int get_div(void __iomem *reg, int shift)
317 {
318 u32 val;
319
320 val = (readl(reg) >> shift) & 0x7;
321 if (val > 6)
322 return 0;
323 return val;
324 }
325
326 static unsigned long clk_double_div_recalc_rate(struct clk_hw *hw,
327 unsigned long parent_rate)
328 {
329 struct clk_double_div *double_div = to_clk_double_div(hw);
330 unsigned int div;
331
332 div = get_div(double_div->reg1, double_div->shift1);
333 div *= get_div(double_div->reg2, double_div->shift2);
334
335 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
336 }
337
338 static const struct clk_ops clk_double_div_ops = {
339 .recalc_rate = clk_double_div_recalc_rate,
340 };
341
342 static void armada_3700_pm_dvfs_update_regs(unsigned int load_level,
343 unsigned int *reg,
344 unsigned int *offset)
345 {
346 if (load_level <= ARMADA_37XX_DVFS_LOAD_1)
347 *reg = ARMADA_37XX_NB_L0L1;
348 else
349 *reg = ARMADA_37XX_NB_L2L3;
350
351 if (load_level == ARMADA_37XX_DVFS_LOAD_0 ||
352 load_level == ARMADA_37XX_DVFS_LOAD_2)
353 *offset += ARMADA_37XX_NB_CONFIG_SHIFT;
354 }
355
356 static bool armada_3700_pm_dvfs_is_enabled(struct regmap *base)
357 {
358 unsigned int val, reg = ARMADA_37XX_NB_DYN_MOD;
359
360 if (IS_ERR(base))
361 return false;
362
363 regmap_read(base, reg, &val);
364
365 return !!(val & BIT(ARMADA_37XX_NB_DFS_EN));
366 }
367
368 static unsigned int armada_3700_pm_dvfs_get_cpu_div(struct regmap *base)
369 {
370 unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
371 unsigned int offset = ARMADA_37XX_NB_TBG_DIV_OFF;
372 unsigned int load_level, div;
373
374 /*
375 * This function is always called after the function
376 * armada_3700_pm_dvfs_is_enabled, so no need to check again
377 * if the base is valid.
378 */
379 regmap_read(base, reg, &load_level);
380
381 /*
382 * The register and the offset inside this register accessed to
383 * read the current divider depend on the load level
384 */
385 load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
386 armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
387
388 regmap_read(base, reg, &div);
389
390 return (div >> offset) & ARMADA_37XX_NB_TBG_DIV_MASK;
391 }
392
393 static unsigned int armada_3700_pm_dvfs_get_cpu_parent(struct regmap *base)
394 {
395 unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
396 unsigned int offset = ARMADA_37XX_NB_TBG_SEL_OFF;
397 unsigned int load_level, sel;
398
399 /*
400 * This function is always called after the function
401 * armada_3700_pm_dvfs_is_enabled, so no need to check again
402 * if the base is valid
403 */
404 regmap_read(base, reg, &load_level);
405
406 /*
407 * The register and the offset inside this register accessed to
408 * read the current divider depend on the load level
409 */
410 load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
411 armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
412
413 regmap_read(base, reg, &sel);
414
415 return (sel >> offset) & ARMADA_37XX_NB_TBG_SEL_MASK;
416 }
417
418 static u8 clk_pm_cpu_get_parent(struct clk_hw *hw)
419 {
420 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
421 int num_parents = clk_hw_get_num_parents(hw);
422 u32 val;
423
424 if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base)) {
425 val = armada_3700_pm_dvfs_get_cpu_parent(pm_cpu->nb_pm_base);
426 } else {
427 val = readl(pm_cpu->reg_mux) >> pm_cpu->shift_mux;
428 val &= pm_cpu->mask_mux;
429 }
430
431 if (val >= num_parents)
432 return -EINVAL;
433
434 return val;
435 }
436
437 static int clk_pm_cpu_set_parent(struct clk_hw *hw, u8 index)
438 {
439 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
440 struct regmap *base = pm_cpu->nb_pm_base;
441 int load_level;
442
443 /*
444 * We set the clock parent only if the DVFS is available but
445 * not enabled.
446 */
447 if (IS_ERR(base) || armada_3700_pm_dvfs_is_enabled(base))
448 return -EINVAL;
449
450 /* Set the parent clock for all the load level */
451 for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
452 unsigned int reg, mask, val,
453 offset = ARMADA_37XX_NB_TBG_SEL_OFF;
454
455 armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
456
457 val = index << offset;
458 mask = ARMADA_37XX_NB_TBG_SEL_MASK << offset;
459 regmap_update_bits(base, reg, mask, val);
460 }
461 return 0;
462 }
463
464 static unsigned long clk_pm_cpu_recalc_rate(struct clk_hw *hw,
465 unsigned long parent_rate)
466 {
467 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
468 unsigned int div;
469
470 if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base))
471 div = armada_3700_pm_dvfs_get_cpu_div(pm_cpu->nb_pm_base);
472 else
473 div = get_div(pm_cpu->reg_div, pm_cpu->shift_div);
474 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
475 }
476
477 static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
478 unsigned long *parent_rate)
479 {
480 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
481 struct regmap *base = pm_cpu->nb_pm_base;
482 unsigned int div = *parent_rate / rate;
483 unsigned int load_level;
484 /* only available when DVFS is enabled */
485 if (!armada_3700_pm_dvfs_is_enabled(base))
486 return -EINVAL;
487
488 for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
489 unsigned int reg, val, offset = ARMADA_37XX_NB_TBG_DIV_OFF;
490
491 armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
492
493 regmap_read(base, reg, &val);
494
495 val >>= offset;
496 val &= ARMADA_37XX_NB_TBG_DIV_MASK;
497 if (val == div)
498 /*
499 * We found a load level matching the target
500 * divider, switch to this load level and
501 * return.
502 */
503 return *parent_rate / div;
504 }
505
506 /* We didn't find any valid divider */
507 return -EINVAL;
508 }
509
510 static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
511 unsigned long parent_rate)
512 {
513 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
514 struct regmap *base = pm_cpu->nb_pm_base;
515 unsigned int div = parent_rate / rate;
516 unsigned int load_level;
517
518 /* only available when DVFS is enabled */
519 if (!armada_3700_pm_dvfs_is_enabled(base))
520 return -EINVAL;
521
522 for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
523 unsigned int reg, mask, val,
524 offset = ARMADA_37XX_NB_TBG_DIV_OFF;
525
526 armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
527
528 regmap_read(base, reg, &val);
529 val >>= offset;
530 val &= ARMADA_37XX_NB_TBG_DIV_MASK;
531
532 if (val == div) {
533 /*
534 * We found a load level matching the target
535 * divider, switch to this load level and
536 * return.
537 */
538 reg = ARMADA_37XX_NB_CPU_LOAD;
539 mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
540 regmap_update_bits(base, reg, mask, load_level);
541
542 return rate;
543 }
544 }
545
546 /* We didn't find any valid divider */
547 return -EINVAL;
548 }
549
550 static const struct clk_ops clk_pm_cpu_ops = {
551 .get_parent = clk_pm_cpu_get_parent,
552 .set_parent = clk_pm_cpu_set_parent,
553 .round_rate = clk_pm_cpu_round_rate,
554 .set_rate = clk_pm_cpu_set_rate,
555 .recalc_rate = clk_pm_cpu_recalc_rate,
556 };
557
558 static const struct of_device_id armada_3700_periph_clock_of_match[] = {
559 { .compatible = "marvell,armada-3700-periph-clock-nb",
560 .data = data_nb, },
561 { .compatible = "marvell,armada-3700-periph-clock-sb",
562 .data = data_sb, },
563 { }
564 };
565
566 static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
567 void __iomem *reg, spinlock_t *lock,
568 struct device *dev, struct clk_hw **hw)
569 {
570 const struct clk_ops *mux_ops = NULL, *gate_ops = NULL,
571 *rate_ops = NULL;
572 struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *rate_hw = NULL;
573
574 if (data->mux_hw) {
575 struct clk_mux *mux;
576
577 mux_hw = data->mux_hw;
578 mux = to_clk_mux(mux_hw);
579 mux->lock = lock;
580 mux_ops = mux_hw->init->ops;
581 mux->reg = reg + (u64)mux->reg;
582 }
583
584 if (data->gate_hw) {
585 struct clk_gate *gate;
586
587 gate_hw = data->gate_hw;
588 gate = to_clk_gate(gate_hw);
589 gate->lock = lock;
590 gate_ops = gate_hw->init->ops;
591 gate->reg = reg + (u64)gate->reg;
592 gate->flags = CLK_GATE_SET_TO_DISABLE;
593 }
594
595 if (data->rate_hw) {
596 rate_hw = data->rate_hw;
597 rate_ops = rate_hw->init->ops;
598 if (data->is_double_div) {
599 struct clk_double_div *rate;
600
601 rate = to_clk_double_div(rate_hw);
602 rate->reg1 = reg + (u64)rate->reg1;
603 rate->reg2 = reg + (u64)rate->reg2;
604 } else {
605 struct clk_divider *rate = to_clk_divider(rate_hw);
606 const struct clk_div_table *clkt;
607 int table_size = 0;
608
609 rate->reg = reg + (u64)rate->reg;
610 for (clkt = rate->table; clkt->div; clkt++)
611 table_size++;
612 rate->width = order_base_2(table_size);
613 rate->lock = lock;
614 }
615 }
616
617 if (data->muxrate_hw) {
618 struct clk_pm_cpu *pmcpu_clk;
619 struct clk_hw *muxrate_hw = data->muxrate_hw;
620 struct regmap *map;
621
622 pmcpu_clk = to_clk_pm_cpu(muxrate_hw);
623 pmcpu_clk->reg_mux = reg + (u64)pmcpu_clk->reg_mux;
624 pmcpu_clk->reg_div = reg + (u64)pmcpu_clk->reg_div;
625
626 mux_hw = muxrate_hw;
627 rate_hw = muxrate_hw;
628 mux_ops = muxrate_hw->init->ops;
629 rate_ops = muxrate_hw->init->ops;
630
631 map = syscon_regmap_lookup_by_compatible(
632 "marvell,armada-3700-nb-pm");
633 pmcpu_clk->nb_pm_base = map;
634 }
635
636 *hw = clk_hw_register_composite(dev, data->name, data->parent_names,
637 data->num_parents, mux_hw,
638 mux_ops, rate_hw, rate_ops,
639 gate_hw, gate_ops, CLK_IGNORE_UNUSED);
640
641 return PTR_ERR_OR_ZERO(*hw);
642 }
643
644 static int armada_3700_periph_clock_probe(struct platform_device *pdev)
645 {
646 struct clk_periph_driver_data *driver_data;
647 struct device_node *np = pdev->dev.of_node;
648 const struct clk_periph_data *data;
649 struct device *dev = &pdev->dev;
650 int num_periph = 0, i, ret;
651 struct resource *res;
652 void __iomem *reg;
653
654 data = of_device_get_match_data(dev);
655 if (!data)
656 return -ENODEV;
657
658 while (data[num_periph].name)
659 num_periph++;
660
661 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
662 reg = devm_ioremap_resource(dev, res);
663 if (IS_ERR(reg))
664 return PTR_ERR(reg);
665
666 driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
667 if (!driver_data)
668 return -ENOMEM;
669
670 driver_data->hw_data = devm_kzalloc(dev, sizeof(*driver_data->hw_data) +
671 sizeof(*driver_data->hw_data->hws) * num_periph,
672 GFP_KERNEL);
673 if (!driver_data->hw_data)
674 return -ENOMEM;
675 driver_data->hw_data->num = num_periph;
676
677 spin_lock_init(&driver_data->lock);
678
679 for (i = 0; i < num_periph; i++) {
680 struct clk_hw **hw = &driver_data->hw_data->hws[i];
681
682 if (armada_3700_add_composite_clk(&data[i], reg,
683 &driver_data->lock, dev, hw))
684 dev_err(dev, "Can't register periph clock %s\n",
685 data[i].name);
686 }
687
688 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
689 driver_data->hw_data);
690 if (ret) {
691 for (i = 0; i < num_periph; i++)
692 clk_hw_unregister(driver_data->hw_data->hws[i]);
693 return ret;
694 }
695
696 platform_set_drvdata(pdev, driver_data);
697 return 0;
698 }
699
700 static int armada_3700_periph_clock_remove(struct platform_device *pdev)
701 {
702 struct clk_periph_driver_data *data = platform_get_drvdata(pdev);
703 struct clk_hw_onecell_data *hw_data = data->hw_data;
704 int i;
705
706 of_clk_del_provider(pdev->dev.of_node);
707
708 for (i = 0; i < hw_data->num; i++)
709 clk_hw_unregister(hw_data->hws[i]);
710
711 return 0;
712 }
713
714 static struct platform_driver armada_3700_periph_clock_driver = {
715 .probe = armada_3700_periph_clock_probe,
716 .remove = armada_3700_periph_clock_remove,
717 .driver = {
718 .name = "marvell-armada-3700-periph-clock",
719 .of_match_table = armada_3700_periph_clock_of_match,
720 },
721 };
722
723 builtin_platform_driver(armada_3700_periph_clock_driver);
Linux with added FPC-III support