drivers/clk/mxs/clk-ssp.c

   1 /*
   2  * Copyright 2012 DENX Software Engineering, GmbH
   3  *
   4  * Pulled from code:
   5  * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
   6  * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
   7  *
   8  * Copyright 2008 Embedded Alley Solutions, Inc.
   9  * Copyright 2009-2011 Freescale Semiconductor, Inc.
  10  *
  11  * The code contained herein is licensed under the GNU General Public
  12  * License. You may obtain a copy of the GNU General Public License
  13  * Version 2 or later at the following locations:
  14  *
  15  * http://www.opensource.org/licenses/gpl-license.html
  16  * http://www.gnu.org/copyleft/gpl.html
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/clk.h>
  22 #include <linux/module.h>
  23 #include <linux/device.h>
  24 #include <linux/io.h>
  25 #include <linux/spi/mxs-spi.h>
  26
  27 void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate)
  28 {
  29         unsigned int ssp_clk, ssp_sck;
  30         u32 clock_divide, clock_rate;
  31         u32 val;
  32
  33         ssp_clk = clk_get_rate(ssp->clk);
  34
  35         for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
  36                 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
  37                 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
  38                 if (clock_rate <= 255)
  39                         break;
  40         }
  41
  42         if (clock_divide > 254) {
  43                 dev_err(ssp->dev,
  44                         "%s: cannot set clock to %d\n", __func__, rate);
  45                 return;
  46         }
  47
  48         ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
  49
  50         val = readl(ssp->base + HW_SSP_TIMING(ssp));
  51         val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
  52         val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
  53         val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
  54         writel(val, ssp->base + HW_SSP_TIMING(ssp));
  55
  56         ssp->clk_rate = ssp_sck;
  57
  58         dev_dbg(ssp->dev,
  59                 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
  60                 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
  61 }
  62 EXPORT_SYMBOL_GPL(mxs_ssp_set_clk_rate);