drivers/clk/qcom/clk-regmap-divider.c

   1 /*
   2  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/regmap.h>
  17 #include <linux/export.h>
  18
  19 #include "clk-regmap-divider.h"
  20
  21 static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw)
  22 {
  23         return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr);
  24 }
  25
  26 static long div_round_ro_rate(struct clk_hw *hw, unsigned long rate,
  27                               unsigned long *prate)
  28 {
  29         struct clk_regmap_div *divider = to_clk_regmap_div(hw);
  30         struct clk_regmap *clkr = &divider->clkr;
  31         u32 div;
  32         struct clk_hw *hw_parent = clk_hw_get_parent(hw);
  33
  34         regmap_read(clkr->regmap, divider->reg, &div);
  35         div >>= divider->shift;
  36         div &= BIT(divider->width) - 1;
  37         div += 1;
  38
  39         if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
  40                 if (!hw_parent)
  41                         return -EINVAL;
  42
  43                 *prate = clk_hw_round_rate(hw_parent, rate * div);
  44         }
  45
  46         return DIV_ROUND_UP_ULL((u64)*prate, div);
  47 }
  48
  49 static long div_round_rate(struct clk_hw *hw, unsigned long rate,
  50                            unsigned long *prate)
  51 {
  52         struct clk_regmap_div *divider = to_clk_regmap_div(hw);
  53
  54         return divider_round_rate(hw, rate, prate, NULL, divider->width,
  55                                   CLK_DIVIDER_ROUND_CLOSEST);
  56 }
  57
  58 static int div_set_rate(struct clk_hw *hw, unsigned long rate,
  59                         unsigned long parent_rate)
  60 {
  61         struct clk_regmap_div *divider = to_clk_regmap_div(hw);
  62         struct clk_regmap *clkr = &divider->clkr;
  63         u32 div;
  64
  65         div = divider_get_val(rate, parent_rate, NULL, divider->width,
  66                               CLK_DIVIDER_ROUND_CLOSEST);
  67
  68         return regmap_update_bits(clkr->regmap, divider->reg,
  69                                   (BIT(divider->width) - 1) << divider->shift,
  70                                   div << divider->shift);
  71 }
  72
  73 static unsigned long div_recalc_rate(struct clk_hw *hw,
  74                                      unsigned long parent_rate)
  75 {
  76         struct clk_regmap_div *divider = to_clk_regmap_div(hw);
  77         struct clk_regmap *clkr = &divider->clkr;
  78         u32 div;
  79
  80         regmap_read(clkr->regmap, divider->reg, &div);
  81         div >>= divider->shift;
  82         div &= BIT(divider->width) - 1;
  83
  84         return divider_recalc_rate(hw, parent_rate, div, NULL,
  85                                    CLK_DIVIDER_ROUND_CLOSEST, divider->width);
  86 }
  87
  88 const struct clk_ops clk_regmap_div_ops = {
  89         .round_rate = div_round_rate,
  90         .set_rate = div_set_rate,
  91         .recalc_rate = div_recalc_rate,
  92 };
  93 EXPORT_SYMBOL_GPL(clk_regmap_div_ops);
  94
  95 const struct clk_ops clk_regmap_div_ro_ops = {
  96         .round_rate = div_round_ro_rate,
  97         .recalc_rate = div_recalc_rate,
  98 };
  99 EXPORT_SYMBOL_GPL(clk_regmap_div_ro_ops);