drivers/clk/qcom/gcc-msm8994.c

   1 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/err.h>
  16 #include <linux/ctype.h>
  17 #include <linux/io.h>
  18 #include <linux/of.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/module.h>
  21 #include <linux/regmap.h>
  22
  23 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
  24
  25 #include "common.h"
  26 #include "clk-regmap.h"
  27 #include "clk-alpha-pll.h"
  28 #include "clk-rcg.h"
  29 #include "clk-branch.h"
  30 #include "reset.h"
  31
  32 enum {
  33         P_XO,
  34         P_GPLL0,
  35         P_GPLL4,
  36 };
  37
  38 static const struct parent_map gcc_xo_gpll0_map[] = {
  39         { P_XO, 0 },
  40         { P_GPLL0, 1 },
  41 };
  42
  43 static const char * const gcc_xo_gpll0[] = {
  44         "xo",
  45         "gpll0",
  46 };
  47
  48 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  49         { P_XO, 0 },
  50         { P_GPLL0, 1 },
  51         { P_GPLL4, 5 },
  52 };
  53
  54 static const char * const gcc_xo_gpll0_gpll4[] = {
  55         "xo",
  56         "gpll0",
  57         "gpll4",
  58 };
  59
  60 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  61
  62 static struct clk_fixed_factor xo = {
  63         .mult = 1,
  64         .div = 1,
  65         .hw.init = &(struct clk_init_data)
  66         {
  67                 .name = "xo",
  68                 .parent_names = (const char *[]) { "xo_board" },
  69                 .num_parents = 1,
  70                 .ops = &clk_fixed_factor_ops,
  71         },
  72 };
  73
  74 static struct clk_alpha_pll gpll0_early = {
  75         .offset = 0x00000,
  76         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  77         .clkr = {
  78                 .enable_reg = 0x1480,
  79                 .enable_mask = BIT(0),
  80                 .hw.init = &(struct clk_init_data)
  81                 {
  82                         .name = "gpll0_early",
  83                         .parent_names = (const char *[]) { "xo" },
  84                         .num_parents = 1,
  85                         .ops = &clk_alpha_pll_ops,
  86                 },
  87         },
  88 };
  89
  90 static struct clk_alpha_pll_postdiv gpll0 = {
  91         .offset = 0x00000,
  92         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  93         .clkr.hw.init = &(struct clk_init_data)
  94         {
  95                 .name = "gpll0",
  96                 .parent_names = (const char *[]) { "gpll0_early" },
  97                 .num_parents = 1,
  98                 .ops = &clk_alpha_pll_postdiv_ops,
  99         },
 100 };
 101
 102 static struct clk_alpha_pll gpll4_early = {
 103         .offset = 0x1dc0,
 104         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 105         .clkr = {
 106                 .enable_reg = 0x1480,
 107                 .enable_mask = BIT(4),
 108                 .hw.init = &(struct clk_init_data)
 109                 {
 110                         .name = "gpll4_early",
 111                         .parent_names = (const char *[]) { "xo" },
 112                         .num_parents = 1,
 113                         .ops = &clk_alpha_pll_ops,
 114                 },
 115         },
 116 };
 117
 118 static struct clk_alpha_pll_postdiv gpll4 = {
 119         .offset = 0x1dc0,
 120         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 121         .clkr.hw.init = &(struct clk_init_data)
 122         {
 123                 .name = "gpll4",
 124                 .parent_names = (const char *[]) { "gpll4_early" },
 125                 .num_parents = 1,
 126                 .ops = &clk_alpha_pll_postdiv_ops,
 127         },
 128 };
 129
 130 static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
 131         F(50000000, P_GPLL0, 12, 0, 0),
 132         F(100000000, P_GPLL0, 6, 0, 0),
 133         F(150000000, P_GPLL0, 4, 0, 0),
 134         F(171430000, P_GPLL0, 3.5, 0, 0),
 135         F(200000000, P_GPLL0, 3, 0, 0),
 136         F(240000000, P_GPLL0, 2.5, 0, 0),
 137         { }
 138 };
 139
 140 static struct clk_rcg2 ufs_axi_clk_src = {
 141         .cmd_rcgr = 0x1d68,
 142         .mnd_width = 8,
 143         .hid_width = 5,
 144         .parent_map = gcc_xo_gpll0_map,
 145         .freq_tbl = ftbl_ufs_axi_clk_src,
 146         .clkr.hw.init = &(struct clk_init_data)
 147         {
 148                 .name = "ufs_axi_clk_src",
 149                 .parent_names = gcc_xo_gpll0,
 150                 .num_parents = 2,
 151                 .ops = &clk_rcg2_ops,
 152         },
 153 };
 154
 155 static struct freq_tbl ftbl_usb30_master_clk_src[] = {
 156         F(19200000, P_XO, 1, 0, 0),
 157         F(125000000, P_GPLL0, 1, 5, 24),
 158         { }
 159 };
 160
 161 static struct clk_rcg2 usb30_master_clk_src = {
 162         .cmd_rcgr = 0x03d4,
 163         .mnd_width = 8,
 164         .hid_width = 5,
 165         .parent_map = gcc_xo_gpll0_map,
 166         .freq_tbl = ftbl_usb30_master_clk_src,
 167         .clkr.hw.init = &(struct clk_init_data)
 168         {
 169                 .name = "usb30_master_clk_src",
 170                 .parent_names = gcc_xo_gpll0,
 171                 .num_parents = 2,
 172                 .ops = &clk_rcg2_ops,
 173         },
 174 };
 175
 176 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
 177         F(19200000, P_XO, 1, 0, 0),
 178         F(50000000, P_GPLL0, 12, 0, 0),
 179         { }
 180 };
 181
 182 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 183         .cmd_rcgr = 0x0660,
 184         .hid_width = 5,
 185         .parent_map = gcc_xo_gpll0_map,
 186         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 187         .clkr.hw.init = &(struct clk_init_data)
 188         {
 189                 .name = "blsp1_qup1_i2c_apps_clk_src",
 190                 .parent_names = gcc_xo_gpll0,
 191                 .num_parents = 2,
 192                 .ops = &clk_rcg2_ops,
 193         },
 194 };
 195
 196 static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = {
 197         F(960000, P_XO, 10, 1, 2),
 198         F(4800000, P_XO, 4, 0, 0),
 199         F(9600000, P_XO, 2, 0, 0),
 200         F(15000000, P_GPLL0, 10, 1, 4),
 201         F(19200000, P_XO, 1, 0, 0),
 202         F(24000000, P_GPLL0, 12.5, 1, 2),
 203         F(25000000, P_GPLL0, 12, 1, 2),
 204         F(48000000, P_GPLL0, 12.5, 0, 0),
 205         F(50000000, P_GPLL0, 12, 0, 0),
 206         { }
 207 };
 208
 209 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 210         .cmd_rcgr = 0x064c,
 211         .mnd_width = 8,
 212         .hid_width = 5,
 213         .parent_map = gcc_xo_gpll0_map,
 214         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 215         .clkr.hw.init = &(struct clk_init_data)
 216         {
 217                 .name = "blsp1_qup1_spi_apps_clk_src",
 218                 .parent_names = gcc_xo_gpll0,
 219                 .num_parents = 2,
 220                 .ops = &clk_rcg2_ops,
 221         },
 222 };
 223
 224 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 225         .cmd_rcgr = 0x06e0,
 226         .hid_width = 5,
 227         .parent_map = gcc_xo_gpll0_map,
 228         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 229         .clkr.hw.init = &(struct clk_init_data)
 230         {
 231                 .name = "blsp1_qup2_i2c_apps_clk_src",
 232                 .parent_names = gcc_xo_gpll0,
 233                 .num_parents = 2,
 234                 .ops = &clk_rcg2_ops,
 235         },
 236 };
 237
 238 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 239         .cmd_rcgr = 0x06cc,
 240         .mnd_width = 8,
 241         .hid_width = 5,
 242         .parent_map = gcc_xo_gpll0_map,
 243         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 244         .clkr.hw.init = &(struct clk_init_data)
 245         {
 246                 .name = "blsp1_qup2_spi_apps_clk_src",
 247                 .parent_names = gcc_xo_gpll0,
 248                 .num_parents = 2,
 249                 .ops = &clk_rcg2_ops,
 250         },
 251 };
 252
 253 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 254         .cmd_rcgr = 0x0760,
 255         .hid_width = 5,
 256         .parent_map = gcc_xo_gpll0_map,
 257         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 258         .clkr.hw.init = &(struct clk_init_data)
 259         {
 260                 .name = "blsp1_qup3_i2c_apps_clk_src",
 261                 .parent_names = gcc_xo_gpll0,
 262                 .num_parents = 2,
 263                 .ops = &clk_rcg2_ops,
 264         },
 265 };
 266
 267 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 268         .cmd_rcgr = 0x074c,
 269         .mnd_width = 8,
 270         .hid_width = 5,
 271         .parent_map = gcc_xo_gpll0_map,
 272         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 273         .clkr.hw.init = &(struct clk_init_data)
 274         {
 275                 .name = "blsp1_qup3_spi_apps_clk_src",
 276                 .parent_names = gcc_xo_gpll0,
 277                 .num_parents = 2,
 278                 .ops = &clk_rcg2_ops,
 279         },
 280 };
 281
 282 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 283         .cmd_rcgr = 0x07e0,
 284         .hid_width = 5,
 285         .parent_map = gcc_xo_gpll0_map,
 286         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 287         .clkr.hw.init = &(struct clk_init_data)
 288         {
 289                 .name = "blsp1_qup4_i2c_apps_clk_src",
 290                 .parent_names = gcc_xo_gpll0,
 291                 .num_parents = 2,
 292                 .ops = &clk_rcg2_ops,
 293         },
 294 };
 295
 296 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 297         .cmd_rcgr = 0x07cc,
 298         .mnd_width = 8,
 299         .hid_width = 5,
 300         .parent_map = gcc_xo_gpll0_map,
 301         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 302         .clkr.hw.init = &(struct clk_init_data)
 303         {
 304                 .name = "blsp1_qup4_spi_apps_clk_src",
 305                 .parent_names = gcc_xo_gpll0,
 306                 .num_parents = 2,
 307                 .ops = &clk_rcg2_ops,
 308         },
 309 };
 310
 311 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 312         .cmd_rcgr = 0x0860,
 313         .hid_width = 5,
 314         .parent_map = gcc_xo_gpll0_map,
 315         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 316         .clkr.hw.init = &(struct clk_init_data)
 317         {
 318                 .name = "blsp1_qup5_i2c_apps_clk_src",
 319                 .parent_names = gcc_xo_gpll0,
 320                 .num_parents = 2,
 321                 .ops = &clk_rcg2_ops,
 322         },
 323 };
 324
 325 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 326         .cmd_rcgr = 0x084c,
 327         .mnd_width = 8,
 328         .hid_width = 5,
 329         .parent_map = gcc_xo_gpll0_map,
 330         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 331         .clkr.hw.init = &(struct clk_init_data)
 332         {
 333                 .name = "blsp1_qup5_spi_apps_clk_src",
 334                 .parent_names = gcc_xo_gpll0,
 335                 .num_parents = 2,
 336                 .ops = &clk_rcg2_ops,
 337         },
 338 };
 339
 340 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 341         .cmd_rcgr = 0x08e0,
 342         .hid_width = 5,
 343         .parent_map = gcc_xo_gpll0_map,
 344         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 345         .clkr.hw.init = &(struct clk_init_data)
 346         {
 347                 .name = "blsp1_qup6_i2c_apps_clk_src",
 348                 .parent_names = gcc_xo_gpll0,
 349                 .num_parents = 2,
 350                 .ops = &clk_rcg2_ops,
 351         },
 352 };
 353
 354 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 355         .cmd_rcgr = 0x08cc,
 356         .mnd_width = 8,
 357         .hid_width = 5,
 358         .parent_map = gcc_xo_gpll0_map,
 359         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 360         .clkr.hw.init = &(struct clk_init_data)
 361         {
 362                 .name = "blsp1_qup6_spi_apps_clk_src",
 363                 .parent_names = gcc_xo_gpll0,
 364                 .num_parents = 2,
 365                 .ops = &clk_rcg2_ops,
 366         },
 367 };
 368
 369 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
 370         F(3686400, P_GPLL0, 1, 96, 15625),
 371         F(7372800, P_GPLL0, 1, 192, 15625),
 372         F(14745600, P_GPLL0, 1, 384, 15625),
 373         F(16000000, P_GPLL0, 5, 2, 15),
 374         F(19200000, P_XO, 1, 0, 0),
 375         F(24000000, P_GPLL0, 5, 1, 5),
 376         F(32000000, P_GPLL0, 1, 4, 75),
 377         F(40000000, P_GPLL0, 15, 0, 0),
 378         F(46400000, P_GPLL0, 1, 29, 375),
 379         F(48000000, P_GPLL0, 12.5, 0, 0),
 380         F(51200000, P_GPLL0, 1, 32, 375),
 381         F(56000000, P_GPLL0, 1, 7, 75),
 382         F(58982400, P_GPLL0, 1, 1536, 15625),
 383         F(60000000, P_GPLL0, 10, 0, 0),
 384         F(63160000, P_GPLL0, 9.5, 0, 0),
 385         { }
 386 };
 387
 388 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 389         .cmd_rcgr = 0x068c,
 390         .mnd_width = 16,
 391         .hid_width = 5,
 392         .parent_map = gcc_xo_gpll0_map,
 393         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 394         .clkr.hw.init = &(struct clk_init_data)
 395         {
 396                 .name = "blsp1_uart1_apps_clk_src",
 397                 .parent_names = gcc_xo_gpll0,
 398                 .num_parents = 2,
 399                 .ops = &clk_rcg2_ops,
 400         },
 401 };
 402
 403 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 404         .cmd_rcgr = 0x070c,
 405         .mnd_width = 16,
 406         .hid_width = 5,
 407         .parent_map = gcc_xo_gpll0_map,
 408         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 409         .clkr.hw.init = &(struct clk_init_data)
 410         {
 411                 .name = "blsp1_uart2_apps_clk_src",
 412                 .parent_names = gcc_xo_gpll0,
 413                 .num_parents = 2,
 414                 .ops = &clk_rcg2_ops,
 415         },
 416 };
 417
 418 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 419         .cmd_rcgr = 0x078c,
 420         .mnd_width = 16,
 421         .hid_width = 5,
 422         .parent_map = gcc_xo_gpll0_map,
 423         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 424         .clkr.hw.init = &(struct clk_init_data)
 425         {
 426                 .name = "blsp1_uart3_apps_clk_src",
 427                 .parent_names = gcc_xo_gpll0,
 428                 .num_parents = 2,
 429                 .ops = &clk_rcg2_ops,
 430         },
 431 };
 432
 433 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 434         .cmd_rcgr = 0x080c,
 435         .mnd_width = 16,
 436         .hid_width = 5,
 437         .parent_map = gcc_xo_gpll0_map,
 438         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 439         .clkr.hw.init = &(struct clk_init_data)
 440         {
 441                 .name = "blsp1_uart4_apps_clk_src",
 442                 .parent_names = gcc_xo_gpll0,
 443                 .num_parents = 2,
 444                 .ops = &clk_rcg2_ops,
 445         },
 446 };
 447
 448 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 449         .cmd_rcgr = 0x088c,
 450         .mnd_width = 16,
 451         .hid_width = 5,
 452         .parent_map = gcc_xo_gpll0_map,
 453         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 454         .clkr.hw.init = &(struct clk_init_data)
 455         {
 456                 .name = "blsp1_uart5_apps_clk_src",
 457                 .parent_names = gcc_xo_gpll0,
 458                 .num_parents = 2,
 459                 .ops = &clk_rcg2_ops,
 460         },
 461 };
 462
 463 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 464         .cmd_rcgr = 0x090c,
 465         .mnd_width = 16,
 466         .hid_width = 5,
 467         .parent_map = gcc_xo_gpll0_map,
 468         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 469         .clkr.hw.init = &(struct clk_init_data)
 470         {
 471                 .name = "blsp1_uart6_apps_clk_src",
 472                 .parent_names = gcc_xo_gpll0,
 473                 .num_parents = 2,
 474                 .ops = &clk_rcg2_ops,
 475         },
 476 };
 477
 478 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 479         .cmd_rcgr = 0x09a0,
 480         .hid_width = 5,
 481         .parent_map = gcc_xo_gpll0_map,
 482         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 483         .clkr.hw.init = &(struct clk_init_data)
 484         {
 485                 .name = "blsp2_qup1_i2c_apps_clk_src",
 486                 .parent_names = gcc_xo_gpll0,
 487                 .num_parents = 2,
 488                 .ops = &clk_rcg2_ops,
 489         },
 490 };
 491
 492 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 493         .cmd_rcgr = 0x098c,
 494         .mnd_width = 8,
 495         .hid_width = 5,
 496         .parent_map = gcc_xo_gpll0_map,
 497         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 498         .clkr.hw.init = &(struct clk_init_data)
 499         {
 500                 .name = "blsp2_qup1_spi_apps_clk_src",
 501                 .parent_names = gcc_xo_gpll0,
 502                 .num_parents = 2,
 503                 .ops = &clk_rcg2_ops,
 504         },
 505 };
 506
 507 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 508         .cmd_rcgr = 0x0a20,
 509         .hid_width = 5,
 510         .parent_map = gcc_xo_gpll0_map,
 511         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 512         .clkr.hw.init = &(struct clk_init_data)
 513         {
 514                 .name = "blsp2_qup2_i2c_apps_clk_src",
 515                 .parent_names = gcc_xo_gpll0,
 516                 .num_parents = 2,
 517                 .ops = &clk_rcg2_ops,
 518         },
 519 };
 520
 521 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 522         .cmd_rcgr = 0x0a0c,
 523         .mnd_width = 8,
 524         .hid_width = 5,
 525         .parent_map = gcc_xo_gpll0_map,
 526         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 527         .clkr.hw.init = &(struct clk_init_data)
 528         {
 529                 .name = "blsp2_qup2_spi_apps_clk_src",
 530                 .parent_names = gcc_xo_gpll0,
 531                 .num_parents = 2,
 532                 .ops = &clk_rcg2_ops,
 533         },
 534 };
 535
 536 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 537         .cmd_rcgr = 0x0aa0,
 538         .hid_width = 5,
 539         .parent_map = gcc_xo_gpll0_map,
 540         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 541         .clkr.hw.init = &(struct clk_init_data)
 542         {
 543                 .name = "blsp2_qup3_i2c_apps_clk_src",
 544                 .parent_names = gcc_xo_gpll0,
 545                 .num_parents = 2,
 546                 .ops = &clk_rcg2_ops,
 547         },
 548 };
 549
 550 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 551         .cmd_rcgr = 0x0a8c,
 552         .mnd_width = 8,
 553         .hid_width = 5,
 554         .parent_map = gcc_xo_gpll0_map,
 555         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 556         .clkr.hw.init = &(struct clk_init_data)
 557         {
 558                 .name = "blsp2_qup3_spi_apps_clk_src",
 559                 .parent_names = gcc_xo_gpll0,
 560                 .num_parents = 2,
 561                 .ops = &clk_rcg2_ops,
 562         },
 563 };
 564
 565 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 566         .cmd_rcgr = 0x0b20,
 567         .hid_width = 5,
 568         .parent_map = gcc_xo_gpll0_map,
 569         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 570         .clkr.hw.init = &(struct clk_init_data)
 571         {
 572                 .name = "blsp2_qup4_i2c_apps_clk_src",
 573                 .parent_names = gcc_xo_gpll0,
 574                 .num_parents = 2,
 575                 .ops = &clk_rcg2_ops,
 576         },
 577 };
 578
 579 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 580         .cmd_rcgr = 0x0b0c,
 581         .mnd_width = 8,
 582         .hid_width = 5,
 583         .parent_map = gcc_xo_gpll0_map,
 584         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 585         .clkr.hw.init = &(struct clk_init_data)
 586         {
 587                 .name = "blsp2_qup4_spi_apps_clk_src",
 588                 .parent_names = gcc_xo_gpll0,
 589                 .num_parents = 2,
 590                 .ops = &clk_rcg2_ops,
 591         },
 592 };
 593
 594 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 595         .cmd_rcgr = 0x0ba0,
 596         .hid_width = 5,
 597         .parent_map = gcc_xo_gpll0_map,
 598         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 599         .clkr.hw.init = &(struct clk_init_data)
 600         {
 601                 .name = "blsp2_qup5_i2c_apps_clk_src",
 602                 .parent_names = gcc_xo_gpll0,
 603                 .num_parents = 2,
 604                 .ops = &clk_rcg2_ops,
 605         },
 606 };
 607
 608 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 609         .cmd_rcgr = 0x0b8c,
 610         .mnd_width = 8,
 611         .hid_width = 5,
 612         .parent_map = gcc_xo_gpll0_map,
 613         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 614         .clkr.hw.init = &(struct clk_init_data)
 615         {
 616                 .name = "blsp2_qup5_spi_apps_clk_src",
 617                 .parent_names = gcc_xo_gpll0,
 618                 .num_parents = 2,
 619                 .ops = &clk_rcg2_ops,
 620         },
 621 };
 622
 623 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 624         .cmd_rcgr = 0x0c20,
 625         .hid_width = 5,
 626         .parent_map = gcc_xo_gpll0_map,
 627         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 628         .clkr.hw.init = &(struct clk_init_data)
 629         {
 630                 .name = "blsp2_qup6_i2c_apps_clk_src",
 631                 .parent_names = gcc_xo_gpll0,
 632                 .num_parents = 2,
 633                 .ops = &clk_rcg2_ops,
 634         },
 635 };
 636
 637 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 638         .cmd_rcgr = 0x0c0c,
 639         .mnd_width = 8,
 640         .hid_width = 5,
 641         .parent_map = gcc_xo_gpll0_map,
 642         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 643         .clkr.hw.init = &(struct clk_init_data)
 644         {
 645                 .name = "blsp2_qup6_spi_apps_clk_src",
 646                 .parent_names = gcc_xo_gpll0,
 647                 .num_parents = 2,
 648                 .ops = &clk_rcg2_ops,
 649         },
 650 };
 651
 652 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 653         .cmd_rcgr = 0x09cc,
 654         .mnd_width = 16,
 655         .hid_width = 5,
 656         .parent_map = gcc_xo_gpll0_map,
 657         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 658         .clkr.hw.init = &(struct clk_init_data)
 659         {
 660                 .name = "blsp2_uart1_apps_clk_src",
 661                 .parent_names = gcc_xo_gpll0,
 662                 .num_parents = 2,
 663                 .ops = &clk_rcg2_ops,
 664         },
 665 };
 666
 667 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 668         .cmd_rcgr = 0x0a4c,
 669         .mnd_width = 16,
 670         .hid_width = 5,
 671         .parent_map = gcc_xo_gpll0_map,
 672         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 673         .clkr.hw.init = &(struct clk_init_data)
 674         {
 675                 .name = "blsp2_uart2_apps_clk_src",
 676                 .parent_names = gcc_xo_gpll0,
 677                 .num_parents = 2,
 678                 .ops = &clk_rcg2_ops,
 679         },
 680 };
 681
 682 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 683         .cmd_rcgr = 0x0acc,
 684         .mnd_width = 16,
 685         .hid_width = 5,
 686         .parent_map = gcc_xo_gpll0_map,
 687         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 688         .clkr.hw.init = &(struct clk_init_data)
 689         {
 690                 .name = "blsp2_uart3_apps_clk_src",
 691                 .parent_names = gcc_xo_gpll0,
 692                 .num_parents = 2,
 693                 .ops = &clk_rcg2_ops,
 694         },
 695 };
 696
 697 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 698         .cmd_rcgr = 0x0b4c,
 699         .mnd_width = 16,
 700         .hid_width = 5,
 701         .parent_map = gcc_xo_gpll0_map,
 702         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 703         .clkr.hw.init = &(struct clk_init_data)
 704         {
 705                 .name = "blsp2_uart4_apps_clk_src",
 706                 .parent_names = gcc_xo_gpll0,
 707                 .num_parents = 2,
 708                 .ops = &clk_rcg2_ops,
 709         },
 710 };
 711
 712 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 713         .cmd_rcgr = 0x0bcc,
 714         .mnd_width = 16,
 715         .hid_width = 5,
 716         .parent_map = gcc_xo_gpll0_map,
 717         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 718         .clkr.hw.init = &(struct clk_init_data)
 719         {
 720                 .name = "blsp2_uart5_apps_clk_src",
 721                 .parent_names = gcc_xo_gpll0,
 722                 .num_parents = 2,
 723                 .ops = &clk_rcg2_ops,
 724         },
 725 };
 726
 727 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 728         .cmd_rcgr = 0x0c4c,
 729         .mnd_width = 16,
 730         .hid_width = 5,
 731         .parent_map = gcc_xo_gpll0_map,
 732         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 733         .clkr.hw.init = &(struct clk_init_data)
 734         {
 735                 .name = "blsp2_uart6_apps_clk_src",
 736                 .parent_names = gcc_xo_gpll0,
 737                 .num_parents = 2,
 738                 .ops = &clk_rcg2_ops,
 739         },
 740 };
 741
 742 static struct freq_tbl ftbl_gp1_clk_src[] = {
 743         F(19200000, P_XO, 1, 0, 0),
 744         F(100000000, P_GPLL0, 6, 0, 0),
 745         F(200000000, P_GPLL0, 3, 0, 0),
 746         { }
 747 };
 748
 749 static struct clk_rcg2 gp1_clk_src = {
 750         .cmd_rcgr = 0x1904,
 751         .mnd_width = 8,
 752         .hid_width = 5,
 753         .parent_map = gcc_xo_gpll0_map,
 754         .freq_tbl = ftbl_gp1_clk_src,
 755         .clkr.hw.init = &(struct clk_init_data)
 756         {
 757                 .name = "gp1_clk_src",
 758                 .parent_names = gcc_xo_gpll0,
 759                 .num_parents = 2,
 760                 .ops = &clk_rcg2_ops,
 761         },
 762 };
 763
 764 static struct freq_tbl ftbl_gp2_clk_src[] = {
 765         F(19200000, P_XO, 1, 0, 0),
 766         F(100000000, P_GPLL0, 6, 0, 0),
 767         F(200000000, P_GPLL0, 3, 0, 0),
 768         { }
 769 };
 770
 771 static struct clk_rcg2 gp2_clk_src = {
 772         .cmd_rcgr = 0x1944,
 773         .mnd_width = 8,
 774         .hid_width = 5,
 775         .parent_map = gcc_xo_gpll0_map,
 776         .freq_tbl = ftbl_gp2_clk_src,
 777         .clkr.hw.init = &(struct clk_init_data)
 778         {
 779                 .name = "gp2_clk_src",
 780                 .parent_names = gcc_xo_gpll0,
 781                 .num_parents = 2,
 782                 .ops = &clk_rcg2_ops,
 783         },
 784 };
 785
 786 static struct freq_tbl ftbl_gp3_clk_src[] = {
 787         F(19200000, P_XO, 1, 0, 0),
 788         F(100000000, P_GPLL0, 6, 0, 0),
 789         F(200000000, P_GPLL0, 3, 0, 0),
 790         { }
 791 };
 792
 793 static struct clk_rcg2 gp3_clk_src = {
 794         .cmd_rcgr = 0x1984,
 795         .mnd_width = 8,
 796         .hid_width = 5,
 797         .parent_map = gcc_xo_gpll0_map,
 798         .freq_tbl = ftbl_gp3_clk_src,
 799         .clkr.hw.init = &(struct clk_init_data)
 800         {
 801                 .name = "gp3_clk_src",
 802                 .parent_names = gcc_xo_gpll0,
 803                 .num_parents = 2,
 804                 .ops = &clk_rcg2_ops,
 805         },
 806 };
 807
 808 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
 809         F(1011000, P_XO, 1, 1, 19),
 810         { }
 811 };
 812
 813 static struct clk_rcg2 pcie_0_aux_clk_src = {
 814         .cmd_rcgr = 0x1b00,
 815         .mnd_width = 8,
 816         .hid_width = 5,
 817         .freq_tbl = ftbl_pcie_0_aux_clk_src,
 818         .clkr.hw.init = &(struct clk_init_data)
 819         {
 820                 .name = "pcie_0_aux_clk_src",
 821                 .parent_names = (const char *[]) { "xo" },
 822                 .num_parents = 1,
 823                 .ops = &clk_rcg2_ops,
 824         },
 825 };
 826
 827 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
 828         F(125000000, P_XO, 1, 0, 0),
 829         { }
 830 };
 831
 832 static struct clk_rcg2 pcie_0_pipe_clk_src = {
 833         .cmd_rcgr = 0x1adc,
 834         .hid_width = 5,
 835         .freq_tbl = ftbl_pcie_pipe_clk_src,
 836         .clkr.hw.init = &(struct clk_init_data)
 837         {
 838                 .name = "pcie_0_pipe_clk_src",
 839                 .parent_names = (const char *[]) { "xo" },
 840                 .num_parents = 1,
 841                 .ops = &clk_rcg2_ops,
 842         },
 843 };
 844
 845 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
 846         F(1011000, P_XO, 1, 1, 19),
 847         { }
 848 };
 849
 850 static struct clk_rcg2 pcie_1_aux_clk_src = {
 851         .cmd_rcgr = 0x1b80,
 852         .mnd_width = 8,
 853         .hid_width = 5,
 854         .freq_tbl = ftbl_pcie_1_aux_clk_src,
 855         .clkr.hw.init = &(struct clk_init_data)
 856         {
 857                 .name = "pcie_1_aux_clk_src",
 858                 .parent_names = (const char *[]) { "xo" },
 859                 .num_parents = 1,
 860                 .ops = &clk_rcg2_ops,
 861         },
 862 };
 863
 864 static struct clk_rcg2 pcie_1_pipe_clk_src = {
 865         .cmd_rcgr = 0x1b5c,
 866         .hid_width = 5,
 867         .freq_tbl = ftbl_pcie_pipe_clk_src,
 868         .clkr.hw.init = &(struct clk_init_data)
 869         {
 870                 .name = "pcie_1_pipe_clk_src",
 871                 .parent_names = (const char *[]) { "xo" },
 872                 .num_parents = 1,
 873                 .ops = &clk_rcg2_ops,
 874         },
 875 };
 876
 877 static struct freq_tbl ftbl_pdm2_clk_src[] = {
 878         F(60000000, P_GPLL0, 10, 0, 0),
 879         { }
 880 };
 881
 882 static struct clk_rcg2 pdm2_clk_src = {
 883         .cmd_rcgr = 0x0cd0,
 884         .hid_width = 5,
 885         .parent_map = gcc_xo_gpll0_map,
 886         .freq_tbl = ftbl_pdm2_clk_src,
 887         .clkr.hw.init = &(struct clk_init_data)
 888         {
 889                 .name = "pdm2_clk_src",
 890                 .parent_names = gcc_xo_gpll0,
 891                 .num_parents = 2,
 892                 .ops = &clk_rcg2_ops,
 893         },
 894 };
 895
 896 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
 897         F(144000, P_XO, 16, 3, 25),
 898         F(400000, P_XO, 12, 1, 4),
 899         F(20000000, P_GPLL0, 15, 1, 2),
 900         F(25000000, P_GPLL0, 12, 1, 2),
 901         F(50000000, P_GPLL0, 12, 0, 0),
 902         F(100000000, P_GPLL0, 6, 0, 0),
 903         F(192000000, P_GPLL4, 2, 0, 0),
 904         F(384000000, P_GPLL4, 1, 0, 0),
 905         { }
 906 };
 907
 908 static struct clk_rcg2 sdcc1_apps_clk_src = {
 909         .cmd_rcgr = 0x04d0,
 910         .mnd_width = 8,
 911         .hid_width = 5,
 912         .parent_map = gcc_xo_gpll0_gpll4_map,
 913         .freq_tbl = ftbl_sdcc1_apps_clk_src,
 914         .clkr.hw.init = &(struct clk_init_data)
 915         {
 916                 .name = "sdcc1_apps_clk_src",
 917                 .parent_names = gcc_xo_gpll0_gpll4,
 918                 .num_parents = 3,
 919                 .ops = &clk_rcg2_floor_ops,
 920         },
 921 };
 922
 923 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
 924         F(144000, P_XO, 16, 3, 25),
 925         F(400000, P_XO, 12, 1, 4),
 926         F(20000000, P_GPLL0, 15, 1, 2),
 927         F(25000000, P_GPLL0, 12, 1, 2),
 928         F(50000000, P_GPLL0, 12, 0, 0),
 929         F(100000000, P_GPLL0, 6, 0, 0),
 930         F(200000000, P_GPLL0, 3, 0, 0),
 931         { }
 932 };
 933
 934 static struct clk_rcg2 sdcc2_apps_clk_src = {
 935         .cmd_rcgr = 0x0510,
 936         .mnd_width = 8,
 937         .hid_width = 5,
 938         .parent_map = gcc_xo_gpll0_map,
 939         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
 940         .clkr.hw.init = &(struct clk_init_data)
 941         {
 942                 .name = "sdcc2_apps_clk_src",
 943                 .parent_names = gcc_xo_gpll0,
 944                 .num_parents = 2,
 945                 .ops = &clk_rcg2_floor_ops,
 946         },
 947 };
 948
 949 static struct clk_rcg2 sdcc3_apps_clk_src = {
 950         .cmd_rcgr = 0x0550,
 951         .mnd_width = 8,
 952         .hid_width = 5,
 953         .parent_map = gcc_xo_gpll0_map,
 954         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
 955         .clkr.hw.init = &(struct clk_init_data)
 956         {
 957                 .name = "sdcc3_apps_clk_src",
 958                 .parent_names = gcc_xo_gpll0,
 959                 .num_parents = 2,
 960                 .ops = &clk_rcg2_floor_ops,
 961         },
 962 };
 963
 964 static struct clk_rcg2 sdcc4_apps_clk_src = {
 965         .cmd_rcgr = 0x0590,
 966         .mnd_width = 8,
 967         .hid_width = 5,
 968         .parent_map = gcc_xo_gpll0_map,
 969         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
 970         .clkr.hw.init = &(struct clk_init_data)
 971         {
 972                 .name = "sdcc4_apps_clk_src",
 973                 .parent_names = gcc_xo_gpll0,
 974                 .num_parents = 2,
 975                 .ops = &clk_rcg2_floor_ops,
 976         },
 977 };
 978
 979 static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
 980         F(105500, P_XO, 1, 1, 182),
 981         { }
 982 };
 983
 984 static struct clk_rcg2 tsif_ref_clk_src = {
 985         .cmd_rcgr = 0x0d90,
 986         .mnd_width = 8,
 987         .hid_width = 5,
 988         .freq_tbl = ftbl_tsif_ref_clk_src,
 989         .clkr.hw.init = &(struct clk_init_data)
 990         {
 991                 .name = "tsif_ref_clk_src",
 992                 .parent_names = (const char *[]) { "xo" },
 993                 .num_parents = 1,
 994                 .ops = &clk_rcg2_ops,
 995         },
 996 };
 997
 998 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
 999         F(19200000, P_XO, 1, 0, 0),
1000         F(60000000, P_GPLL0, 10, 0, 0),
1001         { }
1002 };
1003
1004 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1005         .cmd_rcgr = 0x03e8,
1006         .hid_width = 5,
1007         .parent_map = gcc_xo_gpll0_map,
1008         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1009         .clkr.hw.init = &(struct clk_init_data)
1010         {
1011                 .name = "usb30_mock_utmi_clk_src",
1012                 .parent_names = gcc_xo_gpll0,
1013                 .num_parents = 2,
1014                 .ops = &clk_rcg2_ops,
1015         },
1016 };
1017
1018 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1019         F(1200000, P_XO, 16, 0, 0),
1020         { }
1021 };
1022
1023 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1024         .cmd_rcgr = 0x1414,
1025         .hid_width = 5,
1026         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1027         .clkr.hw.init = &(struct clk_init_data)
1028         {
1029                 .name = "usb3_phy_aux_clk_src",
1030                 .parent_names = (const char *[]) { "xo" },
1031                 .num_parents = 1,
1032                 .ops = &clk_rcg2_ops,
1033         },
1034 };
1035
1036 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1037         F(75000000, P_GPLL0, 8, 0, 0),
1038         { }
1039 };
1040
1041 static struct clk_rcg2 usb_hs_system_clk_src = {
1042         .cmd_rcgr = 0x0490,
1043         .hid_width = 5,
1044         .parent_map = gcc_xo_gpll0_map,
1045         .freq_tbl = ftbl_usb_hs_system_clk_src,
1046         .clkr.hw.init = &(struct clk_init_data)
1047         {
1048                 .name = "usb_hs_system_clk_src",
1049                 .parent_names = gcc_xo_gpll0,
1050                 .num_parents = 2,
1051                 .ops = &clk_rcg2_ops,
1052         },
1053 };
1054
1055 static struct clk_branch gcc_blsp1_ahb_clk = {
1056         .halt_reg = 0x05c4,
1057         .halt_check = BRANCH_HALT_VOTED,
1058         .clkr = {
1059                 .enable_reg = 0x1484,
1060                 .enable_mask = BIT(17),
1061                 .hw.init = &(struct clk_init_data)
1062                 {
1063                         .name = "gcc_blsp1_ahb_clk",
1064                         .ops = &clk_branch2_ops,
1065                 },
1066         },
1067 };
1068
1069 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1070         .halt_reg = 0x0648,
1071         .clkr = {
1072                 .enable_reg = 0x0648,
1073                 .enable_mask = BIT(0),
1074                 .hw.init = &(struct clk_init_data)
1075                 {
1076                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1077                         .parent_names = (const char *[]) {
1078                                 "blsp1_qup1_i2c_apps_clk_src",
1079                         },
1080                         .num_parents = 1,
1081                         .flags = CLK_SET_RATE_PARENT,
1082                         .ops = &clk_branch2_ops,
1083                 },
1084         },
1085 };
1086
1087 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1088         .halt_reg = 0x0644,
1089         .clkr = {
1090                 .enable_reg = 0x0644,
1091                 .enable_mask = BIT(0),
1092                 .hw.init = &(struct clk_init_data)
1093                 {
1094                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1095                         .parent_names = (const char *[]) {
1096                                 "blsp1_qup1_spi_apps_clk_src",
1097                         },
1098                         .num_parents = 1,
1099                         .flags = CLK_SET_RATE_PARENT,
1100                         .ops = &clk_branch2_ops,
1101                 },
1102         },
1103 };
1104
1105 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1106         .halt_reg = 0x06c8,
1107         .clkr = {
1108                 .enable_reg = 0x06c8,
1109                 .enable_mask = BIT(0),
1110                 .hw.init = &(struct clk_init_data)
1111                 {
1112                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1113                         .parent_names = (const char *[]) {
1114                                 "blsp1_qup2_i2c_apps_clk_src",
1115                         },
1116                         .num_parents = 1,
1117                         .flags = CLK_SET_RATE_PARENT,
1118                         .ops = &clk_branch2_ops,
1119                 },
1120         },
1121 };
1122
1123 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1124         .halt_reg = 0x06c4,
1125         .clkr = {
1126                 .enable_reg = 0x06c4,
1127                 .enable_mask = BIT(0),
1128                 .hw.init = &(struct clk_init_data)
1129                 {
1130                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1131                         .parent_names = (const char *[]) {
1132                                 "blsp1_qup2_spi_apps_clk_src",
1133                         },
1134                         .num_parents = 1,
1135                         .flags = CLK_SET_RATE_PARENT,
1136                         .ops = &clk_branch2_ops,
1137                 },
1138         },
1139 };
1140
1141 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1142         .halt_reg = 0x0748,
1143         .clkr = {
1144                 .enable_reg = 0x0748,
1145                 .enable_mask = BIT(0),
1146                 .hw.init = &(struct clk_init_data)
1147                 {
1148                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1149                         .parent_names = (const char *[]) {
1150                                 "blsp1_qup3_i2c_apps_clk_src",
1151                         },
1152                         .num_parents = 1,
1153                         .flags = CLK_SET_RATE_PARENT,
1154                         .ops = &clk_branch2_ops,
1155                 },
1156         },
1157 };
1158
1159 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1160         .halt_reg = 0x0744,
1161         .clkr = {
1162                 .enable_reg = 0x0744,
1163                 .enable_mask = BIT(0),
1164                 .hw.init = &(struct clk_init_data)
1165                 {
1166                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1167                         .parent_names = (const char *[]) {
1168                                 "blsp1_qup3_spi_apps_clk_src",
1169                         },
1170                         .num_parents = 1,
1171                         .flags = CLK_SET_RATE_PARENT,
1172                         .ops = &clk_branch2_ops,
1173                 },
1174         },
1175 };
1176
1177 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1178         .halt_reg = 0x07c8,
1179         .clkr = {
1180                 .enable_reg = 0x07c8,
1181                 .enable_mask = BIT(0),
1182                 .hw.init = &(struct clk_init_data)
1183                 {
1184                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1185                         .parent_names = (const char *[]) {
1186                                 "blsp1_qup4_i2c_apps_clk_src",
1187                         },
1188                         .num_parents = 1,
1189                         .flags = CLK_SET_RATE_PARENT,
1190                         .ops = &clk_branch2_ops,
1191                 },
1192         },
1193 };
1194
1195 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1196         .halt_reg = 0x07c4,
1197         .clkr = {
1198                 .enable_reg = 0x07c4,
1199                 .enable_mask = BIT(0),
1200                 .hw.init = &(struct clk_init_data)
1201                 {
1202                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1203                         .parent_names = (const char *[]) {
1204                                 "blsp1_qup4_spi_apps_clk_src",
1205                         },
1206                         .num_parents = 1,
1207                         .flags = CLK_SET_RATE_PARENT,
1208                         .ops = &clk_branch2_ops,
1209                 },
1210         },
1211 };
1212
1213 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1214         .halt_reg = 0x0848,
1215         .clkr = {
1216                 .enable_reg = 0x0848,
1217                 .enable_mask = BIT(0),
1218                 .hw.init = &(struct clk_init_data)
1219                 {
1220                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1221                         .parent_names = (const char *[]) {
1222                                 "blsp1_qup5_i2c_apps_clk_src",
1223                         },
1224                         .num_parents = 1,
1225                         .flags = CLK_SET_RATE_PARENT,
1226                         .ops = &clk_branch2_ops,
1227                 },
1228         },
1229 };
1230
1231 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1232         .halt_reg = 0x0844,
1233         .clkr = {
1234                 .enable_reg = 0x0844,
1235                 .enable_mask = BIT(0),
1236                 .hw.init = &(struct clk_init_data)
1237                 {
1238                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1239                         .parent_names = (const char *[]) {
1240                                 "blsp1_qup5_spi_apps_clk_src",
1241                         },
1242                         .num_parents = 1,
1243                         .flags = CLK_SET_RATE_PARENT,
1244                         .ops = &clk_branch2_ops,
1245                 },
1246         },
1247 };
1248
1249 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1250         .halt_reg = 0x08c8,
1251         .clkr = {
1252                 .enable_reg = 0x08c8,
1253                 .enable_mask = BIT(0),
1254                 .hw.init = &(struct clk_init_data)
1255                 {
1256                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1257                         .parent_names = (const char *[]) {
1258                                 "blsp1_qup6_i2c_apps_clk_src",
1259                         },
1260                         .num_parents = 1,
1261                         .flags = CLK_SET_RATE_PARENT,
1262                         .ops = &clk_branch2_ops,
1263                 },
1264         },
1265 };
1266
1267 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1268         .halt_reg = 0x08c4,
1269         .clkr = {
1270                 .enable_reg = 0x08c4,
1271                 .enable_mask = BIT(0),
1272                 .hw.init = &(struct clk_init_data)
1273                 {
1274                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1275                         .parent_names = (const char *[]) {
1276                                 "blsp1_qup6_spi_apps_clk_src",
1277                         },
1278                         .num_parents = 1,
1279                         .flags = CLK_SET_RATE_PARENT,
1280                         .ops = &clk_branch2_ops,
1281                 },
1282         },
1283 };
1284
1285 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1286         .halt_reg = 0x0684,
1287         .clkr = {
1288                 .enable_reg = 0x0684,
1289                 .enable_mask = BIT(0),
1290                 .hw.init = &(struct clk_init_data)
1291                 {
1292                         .name = "gcc_blsp1_uart1_apps_clk",
1293                         .parent_names = (const char *[]) {
1294                                 "blsp1_uart1_apps_clk_src",
1295                         },
1296                         .num_parents = 1,
1297                         .flags = CLK_SET_RATE_PARENT,
1298                         .ops = &clk_branch2_ops,
1299                 },
1300         },
1301 };
1302
1303 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1304         .halt_reg = 0x0704,
1305         .clkr = {
1306                 .enable_reg = 0x0704,
1307                 .enable_mask = BIT(0),
1308                 .hw.init = &(struct clk_init_data)
1309                 {
1310                         .name = "gcc_blsp1_uart2_apps_clk",
1311                         .parent_names = (const char *[]) {
1312                                 "blsp1_uart2_apps_clk_src",
1313                         },
1314                         .num_parents = 1,
1315                         .flags = CLK_SET_RATE_PARENT,
1316                         .ops = &clk_branch2_ops,
1317                 },
1318         },
1319 };
1320
1321 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1322         .halt_reg = 0x0784,
1323         .clkr = {
1324                 .enable_reg = 0x0784,
1325                 .enable_mask = BIT(0),
1326                 .hw.init = &(struct clk_init_data)
1327                 {
1328                         .name = "gcc_blsp1_uart3_apps_clk",
1329                         .parent_names = (const char *[]) {
1330                                 "blsp1_uart3_apps_clk_src",
1331                         },
1332                         .num_parents = 1,
1333                         .flags = CLK_SET_RATE_PARENT,
1334                         .ops = &clk_branch2_ops,
1335                 },
1336         },
1337 };
1338
1339 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1340         .halt_reg = 0x0804,
1341         .clkr = {
1342                 .enable_reg = 0x0804,
1343                 .enable_mask = BIT(0),
1344                 .hw.init = &(struct clk_init_data)
1345                 {
1346                         .name = "gcc_blsp1_uart4_apps_clk",
1347                         .parent_names = (const char *[]) {
1348                                 "blsp1_uart4_apps_clk_src",
1349                         },
1350                         .num_parents = 1,
1351                         .flags = CLK_SET_RATE_PARENT,
1352                         .ops = &clk_branch2_ops,
1353                 },
1354         },
1355 };
1356
1357 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1358         .halt_reg = 0x0884,
1359         .clkr = {
1360                 .enable_reg = 0x0884,
1361                 .enable_mask = BIT(0),
1362                 .hw.init = &(struct clk_init_data)
1363                 {
1364                         .name = "gcc_blsp1_uart5_apps_clk",
1365                         .parent_names = (const char *[]) {
1366                                 "blsp1_uart5_apps_clk_src",
1367                         },
1368                         .num_parents = 1,
1369                         .flags = CLK_SET_RATE_PARENT,
1370                         .ops = &clk_branch2_ops,
1371                 },
1372         },
1373 };
1374
1375 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1376         .halt_reg = 0x0904,
1377         .clkr = {
1378                 .enable_reg = 0x0904,
1379                 .enable_mask = BIT(0),
1380                 .hw.init = &(struct clk_init_data)
1381                 {
1382                         .name = "gcc_blsp1_uart6_apps_clk",
1383                         .parent_names = (const char *[]) {
1384                                 "blsp1_uart6_apps_clk_src",
1385                         },
1386                         .num_parents = 1,
1387                         .flags = CLK_SET_RATE_PARENT,
1388                         .ops = &clk_branch2_ops,
1389                 },
1390         },
1391 };
1392
1393 static struct clk_branch gcc_blsp2_ahb_clk = {
1394         .halt_reg = 0x0944,
1395         .halt_check = BRANCH_HALT_VOTED,
1396         .clkr = {
1397                 .enable_reg = 0x1484,
1398                 .enable_mask = BIT(15),
1399                 .hw.init = &(struct clk_init_data)
1400                 {
1401                         .name = "gcc_blsp2_ahb_clk",
1402                         .ops = &clk_branch2_ops,
1403                 },
1404         },
1405 };
1406
1407 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1408         .halt_reg = 0x0988,
1409         .clkr = {
1410                 .enable_reg = 0x0988,
1411                 .enable_mask = BIT(0),
1412                 .hw.init = &(struct clk_init_data)
1413                 {
1414                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1415                         .parent_names = (const char *[]) {
1416                                 "blsp2_qup1_i2c_apps_clk_src",
1417                         },
1418                         .num_parents = 1,
1419                         .flags = CLK_SET_RATE_PARENT,
1420                         .ops = &clk_branch2_ops,
1421                 },
1422         },
1423 };
1424
1425 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1426         .halt_reg = 0x0984,
1427         .clkr = {
1428                 .enable_reg = 0x0984,
1429                 .enable_mask = BIT(0),
1430                 .hw.init = &(struct clk_init_data)
1431                 {
1432                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1433                         .parent_names = (const char *[]) {
1434                                 "blsp2_qup1_spi_apps_clk_src",
1435                         },
1436                         .num_parents = 1,
1437                         .flags = CLK_SET_RATE_PARENT,
1438                         .ops = &clk_branch2_ops,
1439                 },
1440         },
1441 };
1442
1443 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1444         .halt_reg = 0x0a08,
1445         .clkr = {
1446                 .enable_reg = 0x0a08,
1447                 .enable_mask = BIT(0),
1448                 .hw.init = &(struct clk_init_data)
1449                 {
1450                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1451                         .parent_names = (const char *[]) {
1452                                 "blsp2_qup2_i2c_apps_clk_src",
1453                         },
1454                         .num_parents = 1,
1455                         .flags = CLK_SET_RATE_PARENT,
1456                         .ops = &clk_branch2_ops,
1457                 },
1458         },
1459 };
1460
1461 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1462         .halt_reg = 0x0a04,
1463         .clkr = {
1464                 .enable_reg = 0x0a04,
1465                 .enable_mask = BIT(0),
1466                 .hw.init = &(struct clk_init_data)
1467                 {
1468                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1469                         .parent_names = (const char *[]) {
1470                                 "blsp2_qup2_spi_apps_clk_src",
1471                         },
1472                         .num_parents = 1,
1473                         .flags = CLK_SET_RATE_PARENT,
1474                         .ops = &clk_branch2_ops,
1475                 },
1476         },
1477 };
1478
1479 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1480         .halt_reg = 0x0a88,
1481         .clkr = {
1482                 .enable_reg = 0x0a88,
1483                 .enable_mask = BIT(0),
1484                 .hw.init = &(struct clk_init_data)
1485                 {
1486                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
1487                         .parent_names = (const char *[]) {
1488                                 "blsp2_qup3_i2c_apps_clk_src",
1489                         },
1490                         .num_parents = 1,
1491                         .flags = CLK_SET_RATE_PARENT,
1492                         .ops = &clk_branch2_ops,
1493                 },
1494         },
1495 };
1496
1497 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1498         .halt_reg = 0x0a84,
1499         .clkr = {
1500                 .enable_reg = 0x0a84,
1501                 .enable_mask = BIT(0),
1502                 .hw.init = &(struct clk_init_data)
1503                 {
1504                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1505                         .parent_names = (const char *[]) {
1506                                 "blsp2_qup3_spi_apps_clk_src",
1507                         },
1508                         .num_parents = 1,
1509                         .flags = CLK_SET_RATE_PARENT,
1510                         .ops = &clk_branch2_ops,
1511                 },
1512         },
1513 };
1514
1515 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1516         .halt_reg = 0x0b08,
1517         .clkr = {
1518                 .enable_reg = 0x0b08,
1519                 .enable_mask = BIT(0),
1520                 .hw.init = &(struct clk_init_data)
1521                 {
1522                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
1523                         .parent_names = (const char *[]) {
1524                                 "blsp2_qup4_i2c_apps_clk_src",
1525                         },
1526                         .num_parents = 1,
1527                         .flags = CLK_SET_RATE_PARENT,
1528                         .ops = &clk_branch2_ops,
1529                 },
1530         },
1531 };
1532
1533 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1534         .halt_reg = 0x0b04,
1535         .clkr = {
1536                 .enable_reg = 0x0b04,
1537                 .enable_mask = BIT(0),
1538                 .hw.init = &(struct clk_init_data)
1539                 {
1540                         .name = "gcc_blsp2_qup4_spi_apps_clk",
1541                         .parent_names = (const char *[]) {
1542                                 "blsp2_qup4_spi_apps_clk_src",
1543                         },
1544                         .num_parents = 1,
1545                         .flags = CLK_SET_RATE_PARENT,
1546                         .ops = &clk_branch2_ops,
1547                 },
1548         },
1549 };
1550
1551 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1552         .halt_reg = 0x0b88,
1553         .clkr = {
1554                 .enable_reg = 0x0b88,
1555                 .enable_mask = BIT(0),
1556                 .hw.init = &(struct clk_init_data)
1557                 {
1558                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
1559                         .parent_names = (const char *[]) {
1560                                 "blsp2_qup5_i2c_apps_clk_src",
1561                         },
1562                         .num_parents = 1,
1563                         .flags = CLK_SET_RATE_PARENT,
1564                         .ops = &clk_branch2_ops,
1565                 },
1566         },
1567 };
1568
1569 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1570         .halt_reg = 0x0b84,
1571         .clkr = {
1572                 .enable_reg = 0x0b84,
1573                 .enable_mask = BIT(0),
1574                 .hw.init = &(struct clk_init_data)
1575                 {
1576                         .name = "gcc_blsp2_qup5_spi_apps_clk",
1577                         .parent_names = (const char *[]) {
1578                                 "blsp2_qup5_spi_apps_clk_src",
1579                         },
1580                         .num_parents = 1,
1581                         .flags = CLK_SET_RATE_PARENT,
1582                         .ops = &clk_branch2_ops,
1583                 },
1584         },
1585 };
1586
1587 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1588         .halt_reg = 0x0c08,
1589         .clkr = {
1590                 .enable_reg = 0x0c08,
1591                 .enable_mask = BIT(0),
1592                 .hw.init = &(struct clk_init_data)
1593                 {
1594                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
1595                         .parent_names = (const char *[]) {
1596                                 "blsp2_qup6_i2c_apps_clk_src",
1597                         },
1598                         .num_parents = 1,
1599                         .flags = CLK_SET_RATE_PARENT,
1600                         .ops = &clk_branch2_ops,
1601                 },
1602         },
1603 };
1604
1605 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1606         .halt_reg = 0x0c04,
1607         .clkr = {
1608                 .enable_reg = 0x0c04,
1609                 .enable_mask = BIT(0),
1610                 .hw.init = &(struct clk_init_data)
1611                 {
1612                         .name = "gcc_blsp2_qup6_spi_apps_clk",
1613                         .parent_names = (const char *[]) {
1614                                 "blsp2_qup6_spi_apps_clk_src",
1615                         },
1616                         .num_parents = 1,
1617                         .flags = CLK_SET_RATE_PARENT,
1618                         .ops = &clk_branch2_ops,
1619                 },
1620         },
1621 };
1622
1623 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1624         .halt_reg = 0x09c4,
1625         .clkr = {
1626                 .enable_reg = 0x09c4,
1627                 .enable_mask = BIT(0),
1628                 .hw.init = &(struct clk_init_data)
1629                 {
1630                         .name = "gcc_blsp2_uart1_apps_clk",
1631                         .parent_names = (const char *[]) {
1632                                 "blsp2_uart1_apps_clk_src",
1633                         },
1634                         .num_parents = 1,
1635                         .flags = CLK_SET_RATE_PARENT,
1636                         .ops = &clk_branch2_ops,
1637                 },
1638         },
1639 };
1640
1641 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1642         .halt_reg = 0x0a44,
1643         .clkr = {
1644                 .enable_reg = 0x0a44,
1645                 .enable_mask = BIT(0),
1646                 .hw.init = &(struct clk_init_data)
1647                 {
1648                         .name = "gcc_blsp2_uart2_apps_clk",
1649                         .parent_names = (const char *[]) {
1650                                 "blsp2_uart2_apps_clk_src",
1651                         },
1652                         .num_parents = 1,
1653                         .flags = CLK_SET_RATE_PARENT,
1654                         .ops = &clk_branch2_ops,
1655                 },
1656         },
1657 };
1658
1659 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1660         .halt_reg = 0x0ac4,
1661         .clkr = {
1662                 .enable_reg = 0x0ac4,
1663                 .enable_mask = BIT(0),
1664                 .hw.init = &(struct clk_init_data)
1665                 {
1666                         .name = "gcc_blsp2_uart3_apps_clk",
1667                         .parent_names = (const char *[]) {
1668                                 "blsp2_uart3_apps_clk_src",
1669                         },
1670                         .num_parents = 1,
1671                         .flags = CLK_SET_RATE_PARENT,
1672                         .ops = &clk_branch2_ops,
1673                 },
1674         },
1675 };
1676
1677 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1678         .halt_reg = 0x0b44,
1679         .clkr = {
1680                 .enable_reg = 0x0b44,
1681                 .enable_mask = BIT(0),
1682                 .hw.init = &(struct clk_init_data)
1683                 {
1684                         .name = "gcc_blsp2_uart4_apps_clk",
1685                         .parent_names = (const char *[]) {
1686                                 "blsp2_uart4_apps_clk_src",
1687                         },
1688                         .num_parents = 1,
1689                         .flags = CLK_SET_RATE_PARENT,
1690                         .ops = &clk_branch2_ops,
1691                 },
1692         },
1693 };
1694
1695 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1696         .halt_reg = 0x0bc4,
1697         .clkr = {
1698                 .enable_reg = 0x0bc4,
1699                 .enable_mask = BIT(0),
1700                 .hw.init = &(struct clk_init_data)
1701                 {
1702                         .name = "gcc_blsp2_uart5_apps_clk",
1703                         .parent_names = (const char *[]) {
1704                                 "blsp2_uart5_apps_clk_src",
1705                         },
1706                         .num_parents = 1,
1707                         .flags = CLK_SET_RATE_PARENT,
1708                         .ops = &clk_branch2_ops,
1709                 },
1710         },
1711 };
1712
1713 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1714         .halt_reg = 0x0c44,
1715         .clkr = {
1716                 .enable_reg = 0x0c44,
1717                 .enable_mask = BIT(0),
1718                 .hw.init = &(struct clk_init_data)
1719                 {
1720                         .name = "gcc_blsp2_uart6_apps_clk",
1721                         .parent_names = (const char *[]) {
1722                                 "blsp2_uart6_apps_clk_src",
1723                         },
1724                         .num_parents = 1,
1725                         .flags = CLK_SET_RATE_PARENT,
1726                         .ops = &clk_branch2_ops,
1727                 },
1728         },
1729 };
1730
1731 static struct clk_branch gcc_gp1_clk = {
1732         .halt_reg = 0x1900,
1733         .clkr = {
1734                 .enable_reg = 0x1900,
1735                 .enable_mask = BIT(0),
1736                 .hw.init = &(struct clk_init_data)
1737                 {
1738                         .name = "gcc_gp1_clk",
1739                         .parent_names = (const char *[]) {
1740                                 "gp1_clk_src",
1741                         },
1742                         .num_parents = 1,
1743                         .flags = CLK_SET_RATE_PARENT,
1744                         .ops = &clk_branch2_ops,
1745                 },
1746         },
1747 };
1748
1749 static struct clk_branch gcc_gp2_clk = {
1750         .halt_reg = 0x1940,
1751         .clkr = {
1752                 .enable_reg = 0x1940,
1753                 .enable_mask = BIT(0),
1754                 .hw.init = &(struct clk_init_data)
1755                 {
1756                         .name = "gcc_gp2_clk",
1757                         .parent_names = (const char *[]) {
1758                                 "gp2_clk_src",
1759                         },
1760                         .num_parents = 1,
1761                         .flags = CLK_SET_RATE_PARENT,
1762                         .ops = &clk_branch2_ops,
1763                 },
1764         },
1765 };
1766
1767 static struct clk_branch gcc_gp3_clk = {
1768         .halt_reg = 0x1980,
1769         .clkr = {
1770                 .enable_reg = 0x1980,
1771                 .enable_mask = BIT(0),
1772                 .hw.init = &(struct clk_init_data)
1773                 {
1774                         .name = "gcc_gp3_clk",
1775                         .parent_names = (const char *[]) {
1776                                 "gp3_clk_src",
1777                         },
1778                         .num_parents = 1,
1779                         .flags = CLK_SET_RATE_PARENT,
1780                         .ops = &clk_branch2_ops,
1781                 },
1782         },
1783 };
1784
1785 static struct clk_branch gcc_pcie_0_aux_clk = {
1786         .halt_reg = 0x1ad4,
1787         .clkr = {
1788                 .enable_reg = 0x1ad4,
1789                 .enable_mask = BIT(0),
1790                 .hw.init = &(struct clk_init_data)
1791                 {
1792                         .name = "gcc_pcie_0_aux_clk",
1793                         .parent_names = (const char *[]) {
1794                                 "pcie_0_aux_clk_src",
1795                         },
1796                         .num_parents = 1,
1797                         .flags = CLK_SET_RATE_PARENT,
1798                         .ops = &clk_branch2_ops,
1799                 },
1800         },
1801 };
1802
1803 static struct clk_branch gcc_pcie_0_pipe_clk = {
1804         .halt_reg = 0x1ad8,
1805         .halt_check = BRANCH_HALT_DELAY,
1806         .clkr = {
1807                 .enable_reg = 0x1ad8,
1808                 .enable_mask = BIT(0),
1809                 .hw.init = &(struct clk_init_data)
1810                 {
1811                         .name = "gcc_pcie_0_pipe_clk",
1812                         .parent_names = (const char *[]) {
1813                                 "pcie_0_pipe_clk_src",
1814                         },
1815                         .num_parents = 1,
1816                         .flags = CLK_SET_RATE_PARENT,
1817                         .ops = &clk_branch2_ops,
1818                 },
1819         },
1820 };
1821
1822 static struct clk_branch gcc_pcie_1_aux_clk = {
1823         .halt_reg = 0x1b54,
1824         .clkr = {
1825                 .enable_reg = 0x1b54,
1826                 .enable_mask = BIT(0),
1827                 .hw.init = &(struct clk_init_data)
1828                 {
1829                         .name = "gcc_pcie_1_aux_clk",
1830                         .parent_names = (const char *[]) {
1831                                 "pcie_1_aux_clk_src",
1832                         },
1833                         .num_parents = 1,
1834                         .flags = CLK_SET_RATE_PARENT,
1835                         .ops = &clk_branch2_ops,
1836                 },
1837         },
1838 };
1839
1840 static struct clk_branch gcc_pcie_1_pipe_clk = {
1841         .halt_reg = 0x1b58,
1842         .halt_check = BRANCH_HALT_DELAY,
1843         .clkr = {
1844                 .enable_reg = 0x1b58,
1845                 .enable_mask = BIT(0),
1846                 .hw.init = &(struct clk_init_data)
1847                 {
1848                         .name = "gcc_pcie_1_pipe_clk",
1849                         .parent_names = (const char *[]) {
1850                                 "pcie_1_pipe_clk_src",
1851                         },
1852                         .num_parents = 1,
1853                         .flags = CLK_SET_RATE_PARENT,
1854                         .ops = &clk_branch2_ops,
1855                 },
1856         },
1857 };
1858
1859 static struct clk_branch gcc_pdm2_clk = {
1860         .halt_reg = 0x0ccc,
1861         .clkr = {
1862                 .enable_reg = 0x0ccc,
1863                 .enable_mask = BIT(0),
1864                 .hw.init = &(struct clk_init_data)
1865                 {
1866                         .name = "gcc_pdm2_clk",
1867                         .parent_names = (const char *[]) {
1868                                 "pdm2_clk_src",
1869                         },
1870                         .num_parents = 1,
1871                         .flags = CLK_SET_RATE_PARENT,
1872                         .ops = &clk_branch2_ops,
1873                 },
1874         },
1875 };
1876
1877 static struct clk_branch gcc_sdcc1_apps_clk = {
1878         .halt_reg = 0x04c4,
1879         .clkr = {
1880                 .enable_reg = 0x04c4,
1881                 .enable_mask = BIT(0),
1882                 .hw.init = &(struct clk_init_data)
1883                 {
1884                         .name = "gcc_sdcc1_apps_clk",
1885                         .parent_names = (const char *[]) {
1886                                 "sdcc1_apps_clk_src",
1887                         },
1888                         .num_parents = 1,
1889                         .flags = CLK_SET_RATE_PARENT,
1890                         .ops = &clk_branch2_ops,
1891                 },
1892         },
1893 };
1894
1895 static struct clk_branch gcc_sdcc1_ahb_clk = {
1896         .halt_reg = 0x04c8,
1897         .clkr = {
1898                 .enable_reg = 0x04c8,
1899                 .enable_mask = BIT(0),
1900                 .hw.init = &(struct clk_init_data)
1901                 {
1902                         .name = "gcc_sdcc1_ahb_clk",
1903                         .parent_names = (const char *[]){
1904                                 "periph_noc_clk_src",
1905                         },
1906                         .num_parents = 1,
1907                         .ops = &clk_branch2_ops,
1908                 },
1909         },
1910 };
1911
1912 static struct clk_branch gcc_sdcc2_apps_clk = {
1913         .halt_reg = 0x0504,
1914         .clkr = {
1915                 .enable_reg = 0x0504,
1916                 .enable_mask = BIT(0),
1917                 .hw.init = &(struct clk_init_data)
1918                 {
1919                         .name = "gcc_sdcc2_apps_clk",
1920                         .parent_names = (const char *[]) {
1921                                 "sdcc2_apps_clk_src",
1922                         },
1923                         .num_parents = 1,
1924                         .flags = CLK_SET_RATE_PARENT,
1925                         .ops = &clk_branch2_ops,
1926                 },
1927         },
1928 };
1929
1930 static struct clk_branch gcc_sdcc3_apps_clk = {
1931         .halt_reg = 0x0544,
1932         .clkr = {
1933                 .enable_reg = 0x0544,
1934                 .enable_mask = BIT(0),
1935                 .hw.init = &(struct clk_init_data)
1936                 {
1937                         .name = "gcc_sdcc3_apps_clk",
1938                         .parent_names = (const char *[]) {
1939                                 "sdcc3_apps_clk_src",
1940                         },
1941                         .num_parents = 1,
1942                         .flags = CLK_SET_RATE_PARENT,
1943                         .ops = &clk_branch2_ops,
1944                 },
1945         },
1946 };
1947
1948 static struct clk_branch gcc_sdcc4_apps_clk = {
1949         .halt_reg = 0x0584,
1950         .clkr = {
1951                 .enable_reg = 0x0584,
1952                 .enable_mask = BIT(0),
1953                 .hw.init = &(struct clk_init_data)
1954                 {
1955                         .name = "gcc_sdcc4_apps_clk",
1956                         .parent_names = (const char *[]) {
1957                                 "sdcc4_apps_clk_src",
1958                         },
1959                         .num_parents = 1,
1960                         .flags = CLK_SET_RATE_PARENT,
1961                         .ops = &clk_branch2_ops,
1962                 },
1963         },
1964 };
1965
1966 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1967         .halt_reg = 0x1d7c,
1968         .clkr = {
1969                 .enable_reg = 0x1d7c,
1970                 .enable_mask = BIT(0),
1971                 .hw.init = &(struct clk_init_data)
1972                 {
1973                         .name = "gcc_sys_noc_ufs_axi_clk",
1974                         .parent_names = (const char *[]) {
1975                                 "ufs_axi_clk_src",
1976                         },
1977                         .num_parents = 1,
1978                         .flags = CLK_SET_RATE_PARENT,
1979                         .ops = &clk_branch2_ops,
1980                 },
1981         },
1982 };
1983
1984 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1985         .halt_reg = 0x03fc,
1986         .clkr = {
1987                 .enable_reg = 0x03fc,
1988                 .enable_mask = BIT(0),
1989                 .hw.init = &(struct clk_init_data)
1990                 {
1991                         .name = "gcc_sys_noc_usb3_axi_clk",
1992                         .parent_names = (const char *[]) {
1993                                 "usb30_master_clk_src",
1994                         },
1995                         .num_parents = 1,
1996                         .flags = CLK_SET_RATE_PARENT,
1997                         .ops = &clk_branch2_ops,
1998                 },
1999         },
2000 };
2001
2002 static struct clk_branch gcc_tsif_ref_clk = {
2003         .halt_reg = 0x0d88,
2004         .clkr = {
2005                 .enable_reg = 0x0d88,
2006                 .enable_mask = BIT(0),
2007                 .hw.init = &(struct clk_init_data)
2008                 {
2009                         .name = "gcc_tsif_ref_clk",
2010                         .parent_names = (const char *[]) {
2011                                 "tsif_ref_clk_src",
2012                         },
2013                         .num_parents = 1,
2014                         .flags = CLK_SET_RATE_PARENT,
2015                         .ops = &clk_branch2_ops,
2016                 },
2017         },
2018 };
2019
2020 static struct clk_branch gcc_ufs_axi_clk = {
2021         .halt_reg = 0x1d48,
2022         .clkr = {
2023                 .enable_reg = 0x1d48,
2024                 .enable_mask = BIT(0),
2025                 .hw.init = &(struct clk_init_data)
2026                 {
2027                         .name = "gcc_ufs_axi_clk",
2028                         .parent_names = (const char *[]) {
2029                                 "ufs_axi_clk_src",
2030                         },
2031                         .num_parents = 1,
2032                         .flags = CLK_SET_RATE_PARENT,
2033                         .ops = &clk_branch2_ops,
2034                 },
2035         },
2036 };
2037
2038 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2039         .halt_reg = 0x1d54,
2040         .clkr = {
2041                 .enable_reg = 0x1d54,
2042                 .enable_mask = BIT(0),
2043                 .hw.init = &(struct clk_init_data)
2044                 {
2045                         .name = "gcc_ufs_rx_cfg_clk",
2046                         .parent_names = (const char *[]) {
2047                                 "ufs_axi_clk_src",
2048                         },
2049                         .num_parents = 1,
2050                         .flags = CLK_SET_RATE_PARENT,
2051                         .ops = &clk_branch2_ops,
2052                 },
2053         },
2054 };
2055
2056 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2057         .halt_reg = 0x1d50,
2058         .clkr = {
2059                 .enable_reg = 0x1d50,
2060                 .enable_mask = BIT(0),
2061                 .hw.init = &(struct clk_init_data)
2062                 {
2063                         .name = "gcc_ufs_tx_cfg_clk",
2064                         .parent_names = (const char *[]) {
2065                                 "ufs_axi_clk_src",
2066                         },
2067                         .num_parents = 1,
2068                         .flags = CLK_SET_RATE_PARENT,
2069                         .ops = &clk_branch2_ops,
2070                 },
2071         },
2072 };
2073
2074 static struct clk_branch gcc_usb30_master_clk = {
2075         .halt_reg = 0x03c8,
2076         .clkr = {
2077                 .enable_reg = 0x03c8,
2078                 .enable_mask = BIT(0),
2079                 .hw.init = &(struct clk_init_data)
2080                 {
2081                         .name = "gcc_usb30_master_clk",
2082                         .parent_names = (const char *[]) {
2083                                 "usb30_master_clk_src",
2084                         },
2085                         .num_parents = 1,
2086                         .flags = CLK_SET_RATE_PARENT,
2087                         .ops = &clk_branch2_ops,
2088                 },
2089         },
2090 };
2091
2092 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2093         .halt_reg = 0x03d0,
2094         .clkr = {
2095                 .enable_reg = 0x03d0,
2096                 .enable_mask = BIT(0),
2097                 .hw.init = &(struct clk_init_data)
2098                 {
2099                         .name = "gcc_usb30_mock_utmi_clk",
2100                         .parent_names = (const char *[]) {
2101                                 "usb30_mock_utmi_clk_src",
2102                         },
2103                         .num_parents = 1,
2104                         .flags = CLK_SET_RATE_PARENT,
2105                         .ops = &clk_branch2_ops,
2106                 },
2107         },
2108 };
2109
2110 static struct clk_branch gcc_usb3_phy_aux_clk = {
2111         .halt_reg = 0x1408,
2112         .clkr = {
2113                 .enable_reg = 0x1408,
2114                 .enable_mask = BIT(0),
2115                 .hw.init = &(struct clk_init_data)
2116                 {
2117                         .name = "gcc_usb3_phy_aux_clk",
2118                         .parent_names = (const char *[]) {
2119                                 "usb3_phy_aux_clk_src",
2120                         },
2121                         .num_parents = 1,
2122                         .flags = CLK_SET_RATE_PARENT,
2123                         .ops = &clk_branch2_ops,
2124                 },
2125         },
2126 };
2127
2128 static struct clk_branch gcc_usb_hs_system_clk = {
2129         .halt_reg = 0x0484,
2130         .clkr = {
2131                 .enable_reg = 0x0484,
2132                 .enable_mask = BIT(0),
2133                 .hw.init = &(struct clk_init_data)
2134                 {
2135                         .name = "gcc_usb_hs_system_clk",
2136                         .parent_names = (const char *[]) {
2137                                 "usb_hs_system_clk_src",
2138                         },
2139                         .num_parents = 1,
2140                         .flags = CLK_SET_RATE_PARENT,
2141                         .ops = &clk_branch2_ops,
2142                 },
2143         },
2144 };
2145
2146 static struct clk_regmap *gcc_msm8994_clocks[] = {
2147         [GPLL0_EARLY] = &gpll0_early.clkr,
2148         [GPLL0] = &gpll0.clkr,
2149         [GPLL4_EARLY] = &gpll4_early.clkr,
2150         [GPLL4] = &gpll4.clkr,
2151         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2152         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2153         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2154         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2155         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2156         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2157         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2158         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2159         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2160         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2161         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2162         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2163         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2164         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2165         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2166         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2167         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2168         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2169         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2170         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2171         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2172         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2173         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2174         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2175         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2176         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2177         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2178         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2179         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2180         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2181         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2182         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2183         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2184         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2185         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2186         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2187         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2188         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2189         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2190         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2191         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2192         [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2193         [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2194         [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2195         [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2196         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2197         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2198         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2199         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2200         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2201         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2202         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2203         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2204         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2205         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2206         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2207         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2208         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2209         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2210         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2211         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2212         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2213         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2214         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2215         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2216         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2217         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2218         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2219         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2220         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2221         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2222         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2223         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2224         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2225         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2226         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2227         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2228         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2229         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2230         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2231         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2232         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2233         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2234         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2235         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2236         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2237         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2238         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2239         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2240         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2241         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2242         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2243         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2244         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2245         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2246         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2247         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2248         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2249         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2250         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2251         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2252         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2253         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2254         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2255         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2256         [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2257         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2258         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2259         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2260         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2261         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2262         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2263         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2264         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2265         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2266 };
2267
2268 static const struct regmap_config gcc_msm8994_regmap_config = {
2269         .reg_bits       = 32,
2270         .reg_stride     = 4,
2271         .val_bits       = 32,
2272         .max_register   = 0x2000,
2273         .fast_io        = true,
2274 };
2275
2276 static const struct qcom_cc_desc gcc_msm8994_desc = {
2277         .config = &gcc_msm8994_regmap_config,
2278         .clks = gcc_msm8994_clocks,
2279         .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2280 };
2281
2282 static const struct of_device_id gcc_msm8994_match_table[] = {
2283         { .compatible = "qcom,gcc-msm8994" },
2284         {}
2285 };
2286 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2287
2288 static int gcc_msm8994_probe(struct platform_device *pdev)
2289 {
2290         struct device *dev = &pdev->dev;
2291         struct clk *clk;
2292
2293         clk = devm_clk_register(dev, &xo.hw);
2294         if (IS_ERR(clk))
2295                 return PTR_ERR(clk);
2296
2297         return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2298 }
2299
2300 static struct platform_driver gcc_msm8994_driver = {
2301         .probe          = gcc_msm8994_probe,
2302         .driver         = {
2303                 .name   = "gcc-msm8994",
2304                 .of_match_table = gcc_msm8994_match_table,
2305         },
2306 };
2307
2308 static int __init gcc_msm8994_init(void)
2309 {
2310         return platform_driver_register(&gcc_msm8994_driver);
2311 }
2312 core_initcall(gcc_msm8994_init);
2313
2314 static void __exit gcc_msm8994_exit(void)
2315 {
2316         platform_driver_unregister(&gcc_msm8994_driver);
2317 }
2318 module_exit(gcc_msm8994_exit);
2319
2320 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2321 MODULE_LICENSE("GPL v2");
2322 MODULE_ALIAS("platform:gcc-msm8994");