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Linux 4.16.11
[linux/fpc-iii.git] / drivers / clk / renesas / rcar-gen3-cpg.c
blob0904886f55015a3bdf309f7bdb38add0fd08a7e3
1 /*
2 * R-Car Gen3 Clock Pulse Generator
3 *
4 * Copyright (C) 2015-2016 Glider bvba
5 *
6 * Based on clk-rcar-gen3.c
7 *
8 * Copyright (C) 2015 Renesas Electronics Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */
14
15 #include <linux/bug.h>
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/device.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/pm.h>
23 #include <linux/slab.h>
24 #include <linux/sys_soc.h>
25
26 #include "renesas-cpg-mssr.h"
27 #include "rcar-gen3-cpg.h"
28
29 #define CPG_PLL0CR 0x00d8
30 #define CPG_PLL2CR 0x002c
31 #define CPG_PLL4CR 0x01f4
32
33 struct cpg_simple_notifier {
34 struct notifier_block nb;
35 void __iomem *reg;
36 u32 saved;
37 };
38
39 static int cpg_simple_notifier_call(struct notifier_block *nb,
40 unsigned long action, void *data)
41 {
42 struct cpg_simple_notifier *csn =
43 container_of(nb, struct cpg_simple_notifier, nb);
44
45 switch (action) {
46 case PM_EVENT_SUSPEND:
47 csn->saved = readl(csn->reg);
48 return NOTIFY_OK;
49
50 case PM_EVENT_RESUME:
51 writel(csn->saved, csn->reg);
52 return NOTIFY_OK;
53 }
54 return NOTIFY_DONE;
55 }
56
57 static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
58 struct cpg_simple_notifier *csn)
59 {
60 csn->nb.notifier_call = cpg_simple_notifier_call;
61 raw_notifier_chain_register(notifiers, &csn->nb);
62 }
63
64 /*
65 * SDn Clock
66 */
67 #define CPG_SD_STP_HCK BIT(9)
68 #define CPG_SD_STP_CK BIT(8)
69
70 #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
71 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
72
73 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
74 { \
75 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
76 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
77 ((sd_srcfc) << 2) | \
78 ((sd_fc) << 0), \
79 .div = (sd_div), \
80 }
81
82 struct sd_div_table {
83 u32 val;
84 unsigned int div;
85 };
86
87 struct sd_clock {
88 struct clk_hw hw;
89 const struct sd_div_table *div_table;
90 struct cpg_simple_notifier csn;
91 unsigned int div_num;
92 unsigned int div_min;
93 unsigned int div_max;
94 unsigned int cur_div_idx;
95 };
96
97 /* SDn divider
98 * sd_srcfc sd_fc div
99 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
100 *-------------------------------------------------------------------
101 * 0 0 0 (1) 1 (4) 4
102 * 0 0 1 (2) 1 (4) 8
103 * 1 0 2 (4) 1 (4) 16
104 * 1 0 3 (8) 1 (4) 32
105 * 1 0 4 (16) 1 (4) 64
106 * 0 0 0 (1) 0 (2) 2
107 * 0 0 1 (2) 0 (2) 4
108 * 1 0 2 (4) 0 (2) 8
109 * 1 0 3 (8) 0 (2) 16
110 * 1 0 4 (16) 0 (2) 32
111 */
112 static const struct sd_div_table cpg_sd_div_table[] = {
113 /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
114 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
115 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
116 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
117 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
118 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
119 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
120 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
121 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
122 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
123 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
124 };
125
126 #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
127
128 static int cpg_sd_clock_enable(struct clk_hw *hw)
129 {
130 struct sd_clock *clock = to_sd_clock(hw);
131 u32 val = readl(clock->csn.reg);
132
133 val &= ~(CPG_SD_STP_MASK);
134 val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK;
135
136 writel(val, clock->csn.reg);
137
138 return 0;
139 }
140
141 static void cpg_sd_clock_disable(struct clk_hw *hw)
142 {
143 struct sd_clock *clock = to_sd_clock(hw);
144
145 writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg);
146 }
147
148 static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
149 {
150 struct sd_clock *clock = to_sd_clock(hw);
151
152 return !(readl(clock->csn.reg) & CPG_SD_STP_MASK);
153 }
154
155 static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
156 unsigned long parent_rate)
157 {
158 struct sd_clock *clock = to_sd_clock(hw);
159
160 return DIV_ROUND_CLOSEST(parent_rate,
161 clock->div_table[clock->cur_div_idx].div);
162 }
163
164 static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
165 unsigned long rate,
166 unsigned long parent_rate)
167 {
168 unsigned int div;
169
170 if (!rate)
171 rate = 1;
172
173 div = DIV_ROUND_CLOSEST(parent_rate, rate);
174
175 return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
176 }
177
178 static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
179 unsigned long *parent_rate)
180 {
181 struct sd_clock *clock = to_sd_clock(hw);
182 unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
183
184 return DIV_ROUND_CLOSEST(*parent_rate, div);
185 }
186
187 static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
188 unsigned long parent_rate)
189 {
190 struct sd_clock *clock = to_sd_clock(hw);
191 unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
192 u32 val;
193 unsigned int i;
194
195 for (i = 0; i < clock->div_num; i++)
196 if (div == clock->div_table[i].div)
197 break;
198
199 if (i >= clock->div_num)
200 return -EINVAL;
201
202 clock->cur_div_idx = i;
203
204 val = readl(clock->csn.reg);
205 val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
206 val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
207 writel(val, clock->csn.reg);
208
209 return 0;
210 }
211
212 static const struct clk_ops cpg_sd_clock_ops = {
213 .enable = cpg_sd_clock_enable,
214 .disable = cpg_sd_clock_disable,
215 .is_enabled = cpg_sd_clock_is_enabled,
216 .recalc_rate = cpg_sd_clock_recalc_rate,
217 .round_rate = cpg_sd_clock_round_rate,
218 .set_rate = cpg_sd_clock_set_rate,
219 };
220
221 static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
222 void __iomem *base, const char *parent_name,
223 struct raw_notifier_head *notifiers)
224 {
225 struct clk_init_data init;
226 struct sd_clock *clock;
227 struct clk *clk;
228 unsigned int i;
229 u32 sd_fc;
230
231 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
232 if (!clock)
233 return ERR_PTR(-ENOMEM);
234
235 init.name = core->name;
236 init.ops = &cpg_sd_clock_ops;
237 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
238 init.parent_names = &parent_name;
239 init.num_parents = 1;
240
241 clock->csn.reg = base + core->offset;
242 clock->hw.init = &init;
243 clock->div_table = cpg_sd_div_table;
244 clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
245
246 sd_fc = readl(clock->csn.reg) & CPG_SD_FC_MASK;
247 for (i = 0; i < clock->div_num; i++)
248 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
249 break;
250
251 if (WARN_ON(i >= clock->div_num)) {
252 kfree(clock);
253 return ERR_PTR(-EINVAL);
254 }
255
256 clock->cur_div_idx = i;
257
258 clock->div_max = clock->div_table[0].div;
259 clock->div_min = clock->div_max;
260 for (i = 1; i < clock->div_num; i++) {
261 clock->div_max = max(clock->div_max, clock->div_table[i].div);
262 clock->div_min = min(clock->div_min, clock->div_table[i].div);
263 }
264
265 clk = clk_register(NULL, &clock->hw);
266 if (IS_ERR(clk))
267 goto free_clock;
268
269 cpg_simple_notifier_register(notifiers, &clock->csn);
270 return clk;
271
272 free_clock:
273 kfree(clock);
274 return clk;
275 }
276
277
278 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
279 static unsigned int cpg_clk_extalr __initdata;
280 static u32 cpg_mode __initdata;
281 static u32 cpg_quirks __initdata;
282
283 #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
284 #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
285
286 static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
287 {
288 .soc_id = "r8a7795", .revision = "ES1.0",
289 .data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
290 },
291 {
292 .soc_id = "r8a7795", .revision = "ES1.*",
293 .data = (void *)RCKCR_CKSEL,
294 },
295 {
296 .soc_id = "r8a7796", .revision = "ES1.0",
297 .data = (void *)RCKCR_CKSEL,
298 },
299 { /* sentinel */ }
300 };
301
302 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
303 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
304 struct clk **clks, void __iomem *base,
305 struct raw_notifier_head *notifiers)
306 {
307 const struct clk *parent;
308 unsigned int mult = 1;
309 unsigned int div = 1;
310 u32 value;
311
312 parent = clks[core->parent & 0xffff]; /* CLK_TYPE_PE uses high bits */
313 if (IS_ERR(parent))
314 return ERR_CAST(parent);
315
316 switch (core->type) {
317 case CLK_TYPE_GEN3_MAIN:
318 div = cpg_pll_config->extal_div;
319 break;
320
321 case CLK_TYPE_GEN3_PLL0:
322 /*
323 * PLL0 is a configurable multiplier clock. Register it as a
324 * fixed factor clock for now as there's no generic multiplier
325 * clock implementation and we currently have no need to change
326 * the multiplier value.
327 */
328 value = readl(base + CPG_PLL0CR);
329 mult = (((value >> 24) & 0x7f) + 1) * 2;
330 if (cpg_quirks & PLL_ERRATA)
331 mult *= 2;
332 break;
333
334 case CLK_TYPE_GEN3_PLL1:
335 mult = cpg_pll_config->pll1_mult;
336 div = cpg_pll_config->pll1_div;
337 break;
338
339 case CLK_TYPE_GEN3_PLL2:
340 /*
341 * PLL2 is a configurable multiplier clock. Register it as a
342 * fixed factor clock for now as there's no generic multiplier
343 * clock implementation and we currently have no need to change
344 * the multiplier value.
345 */
346 value = readl(base + CPG_PLL2CR);
347 mult = (((value >> 24) & 0x7f) + 1) * 2;
348 if (cpg_quirks & PLL_ERRATA)
349 mult *= 2;
350 break;
351
352 case CLK_TYPE_GEN3_PLL3:
353 mult = cpg_pll_config->pll3_mult;
354 div = cpg_pll_config->pll3_div;
355 break;
356
357 case CLK_TYPE_GEN3_PLL4:
358 /*
359 * PLL4 is a configurable multiplier clock. Register it as a
360 * fixed factor clock for now as there's no generic multiplier
361 * clock implementation and we currently have no need to change
362 * the multiplier value.
363 */
364 value = readl(base + CPG_PLL4CR);
365 mult = (((value >> 24) & 0x7f) + 1) * 2;
366 if (cpg_quirks & PLL_ERRATA)
367 mult *= 2;
368 break;
369
370 case CLK_TYPE_GEN3_SD:
371 return cpg_sd_clk_register(core, base, __clk_get_name(parent),
372 notifiers);
373
374 case CLK_TYPE_GEN3_R:
375 if (cpg_quirks & RCKCR_CKSEL) {
376 struct cpg_simple_notifier *csn;
377
378 csn = kzalloc(sizeof(*csn), GFP_KERNEL);
379 if (!csn)
380 return ERR_PTR(-ENOMEM);
381
382 csn->reg = base + CPG_RCKCR;
383
384 /*
385 * RINT is default.
386 * Only if EXTALR is populated, we switch to it.
387 */
388 value = readl(csn->reg) & 0x3f;
389
390 if (clk_get_rate(clks[cpg_clk_extalr])) {
391 parent = clks[cpg_clk_extalr];
392 value |= BIT(15);
393 }
394
395 writel(value, csn->reg);
396 cpg_simple_notifier_register(notifiers, csn);
397 break;
398 }
399
400 /* Select parent clock of RCLK by MD28 */
401 if (cpg_mode & BIT(28))
402 parent = clks[cpg_clk_extalr];
403 break;
404
405 case CLK_TYPE_GEN3_PE:
406 /*
407 * Peripheral clock with a fixed divider, selectable between
408 * clean and spread spectrum parents using MD12
409 */
410 if (cpg_mode & BIT(12)) {
411 /* Clean */
412 div = core->div & 0xffff;
413 } else {
414 /* SCCG */
415 parent = clks[core->parent >> 16];
416 if (IS_ERR(parent))
417 return ERR_CAST(parent);
418 div = core->div >> 16;
419 }
420 mult = 1;
421 break;
422
423 default:
424 return ERR_PTR(-EINVAL);
425 }
426
427 return clk_register_fixed_factor(NULL, core->name,
428 __clk_get_name(parent), 0, mult, div);
429 }
430
431 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
432 unsigned int clk_extalr, u32 mode)
433 {
434 const struct soc_device_attribute *attr;
435
436 cpg_pll_config = config;
437 cpg_clk_extalr = clk_extalr;
438 cpg_mode = mode;
439 attr = soc_device_match(cpg_quirks_match);
440 if (attr)
441 cpg_quirks = (uintptr_t)attr->data;
442 pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
443 return 0;
444 }
Linux with added FPC-III support