2 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
3 * Author: Marek Szyprowski <m.szyprowski@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * Common Clock Framework support for Exynos4412 ISP module.
12 #include <dt-bindings/clock/exynos4.h>
13 #include <linux/slab.h>
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
22 /* Exynos4x12 specific registers, which belong to ISP power domain */
23 #define E4X12_DIV_ISP0 0x0300
24 #define E4X12_DIV_ISP1 0x0304
25 #define E4X12_GATE_ISP0 0x0800
26 #define E4X12_GATE_ISP1 0x0804
29 * Support for CMU save/restore across system suspends
31 static struct samsung_clk_reg_dump
*exynos4x12_save_isp
;
33 static const unsigned long exynos4x12_clk_isp_save
[] __initconst
= {
40 PNAME(mout_user_aclk400_mcuisp_p4x12
) = { "fin_pll", "div_aclk400_mcuisp", };
42 static struct samsung_div_clock exynos4x12_isp_div_clks
[] = {
43 DIV(CLK_ISP_DIV_ISP0
, "div_isp0", "aclk200", E4X12_DIV_ISP0
, 0, 3),
44 DIV(CLK_ISP_DIV_ISP1
, "div_isp1", "aclk200", E4X12_DIV_ISP0
, 4, 3),
45 DIV(CLK_ISP_DIV_MCUISP0
, "div_mcuisp0", "aclk400_mcuisp",
46 E4X12_DIV_ISP1
, 4, 3),
47 DIV(CLK_ISP_DIV_MCUISP1
, "div_mcuisp1", "div_mcuisp0",
48 E4X12_DIV_ISP1
, 8, 3),
49 DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1
, 0, 3),
52 static struct samsung_gate_clock exynos4x12_isp_gate_clks
[] = {
53 GATE(CLK_ISP_FIMC_ISP
, "isp", "aclk200", E4X12_GATE_ISP0
, 0, 0, 0),
54 GATE(CLK_ISP_FIMC_DRC
, "drc", "aclk200", E4X12_GATE_ISP0
, 1, 0, 0),
55 GATE(CLK_ISP_FIMC_FD
, "fd", "aclk200", E4X12_GATE_ISP0
, 2, 0, 0),
56 GATE(CLK_ISP_FIMC_LITE0
, "lite0", "aclk200", E4X12_GATE_ISP0
, 3, 0, 0),
57 GATE(CLK_ISP_FIMC_LITE1
, "lite1", "aclk200", E4X12_GATE_ISP0
, 4, 0, 0),
58 GATE(CLK_ISP_MCUISP
, "mcuisp", "aclk200", E4X12_GATE_ISP0
, 5, 0, 0),
59 GATE(CLK_ISP_GICISP
, "gicisp", "aclk200", E4X12_GATE_ISP0
, 7, 0, 0),
60 GATE(CLK_ISP_SMMU_ISP
, "smmu_isp", "aclk200", E4X12_GATE_ISP0
, 8, 0, 0),
61 GATE(CLK_ISP_SMMU_DRC
, "smmu_drc", "aclk200", E4X12_GATE_ISP0
, 9, 0, 0),
62 GATE(CLK_ISP_SMMU_FD
, "smmu_fd", "aclk200", E4X12_GATE_ISP0
, 10, 0, 0),
63 GATE(CLK_ISP_SMMU_LITE0
, "smmu_lite0", "aclk200", E4X12_GATE_ISP0
, 11,
65 GATE(CLK_ISP_SMMU_LITE1
, "smmu_lite1", "aclk200", E4X12_GATE_ISP0
, 12,
67 GATE(CLK_ISP_PPMUISPMX
, "ppmuispmx", "aclk200", E4X12_GATE_ISP0
, 20,
69 GATE(CLK_ISP_PPMUISPX
, "ppmuispx", "aclk200", E4X12_GATE_ISP0
, 21,
71 GATE(CLK_ISP_MCUCTL_ISP
, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0
, 23,
73 GATE(CLK_ISP_MPWM_ISP
, "mpwm_isp", "aclk200", E4X12_GATE_ISP0
, 24,
75 GATE(CLK_ISP_I2C0_ISP
, "i2c0_isp", "aclk200", E4X12_GATE_ISP0
, 25,
77 GATE(CLK_ISP_I2C1_ISP
, "i2c1_isp", "aclk200", E4X12_GATE_ISP0
, 26,
79 GATE(CLK_ISP_MTCADC_ISP
, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0
, 27,
81 GATE(CLK_ISP_PWM_ISP
, "pwm_isp", "aclk200", E4X12_GATE_ISP0
, 28, 0, 0),
82 GATE(CLK_ISP_WDT_ISP
, "wdt_isp", "aclk200", E4X12_GATE_ISP0
, 30, 0, 0),
83 GATE(CLK_ISP_UART_ISP
, "uart_isp", "aclk200", E4X12_GATE_ISP0
, 31,
85 GATE(CLK_ISP_ASYNCAXIM
, "asyncaxim", "aclk200", E4X12_GATE_ISP1
, 0,
87 GATE(CLK_ISP_SMMU_ISPCX
, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1
, 4,
89 GATE(CLK_ISP_SPI0_ISP
, "spi0_isp", "aclk200", E4X12_GATE_ISP1
, 12,
91 GATE(CLK_ISP_SPI1_ISP
, "spi1_isp", "aclk200", E4X12_GATE_ISP1
, 13,
95 static int __maybe_unused
exynos4x12_isp_clk_suspend(struct device
*dev
)
97 struct samsung_clk_provider
*ctx
= dev_get_drvdata(dev
);
99 samsung_clk_save(ctx
->reg_base
, exynos4x12_save_isp
,
100 ARRAY_SIZE(exynos4x12_clk_isp_save
));
104 static int __maybe_unused
exynos4x12_isp_clk_resume(struct device
*dev
)
106 struct samsung_clk_provider
*ctx
= dev_get_drvdata(dev
);
108 samsung_clk_restore(ctx
->reg_base
, exynos4x12_save_isp
,
109 ARRAY_SIZE(exynos4x12_clk_isp_save
));
113 static int __init
exynos4x12_isp_clk_probe(struct platform_device
*pdev
)
115 struct samsung_clk_provider
*ctx
;
116 struct device
*dev
= &pdev
->dev
;
117 struct device_node
*np
= dev
->of_node
;
118 struct resource
*res
;
119 void __iomem
*reg_base
;
121 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
122 reg_base
= devm_ioremap_resource(dev
, res
);
123 if (IS_ERR(reg_base
)) {
124 dev_err(dev
, "failed to map registers\n");
125 return PTR_ERR(reg_base
);
128 exynos4x12_save_isp
= samsung_clk_alloc_reg_dump(exynos4x12_clk_isp_save
,
129 ARRAY_SIZE(exynos4x12_clk_isp_save
));
130 if (!exynos4x12_save_isp
)
133 ctx
= samsung_clk_init(np
, reg_base
, CLK_NR_ISP_CLKS
);
136 platform_set_drvdata(pdev
, ctx
);
138 pm_runtime_set_active(dev
);
139 pm_runtime_enable(dev
);
140 pm_runtime_get_sync(dev
);
142 samsung_clk_register_div(ctx
, exynos4x12_isp_div_clks
,
143 ARRAY_SIZE(exynos4x12_isp_div_clks
));
144 samsung_clk_register_gate(ctx
, exynos4x12_isp_gate_clks
,
145 ARRAY_SIZE(exynos4x12_isp_gate_clks
));
147 samsung_clk_of_add_provider(np
, ctx
);
153 static const struct of_device_id exynos4x12_isp_clk_of_match
[] = {
154 { .compatible
= "samsung,exynos4412-isp-clock", },
158 static const struct dev_pm_ops exynos4x12_isp_pm_ops
= {
159 SET_RUNTIME_PM_OPS(exynos4x12_isp_clk_suspend
,
160 exynos4x12_isp_clk_resume
, NULL
)
161 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend
,
162 pm_runtime_force_resume
)
165 static struct platform_driver exynos4x12_isp_clk_driver __refdata
= {
167 .name
= "exynos4x12-isp-clk",
168 .of_match_table
= exynos4x12_isp_clk_of_match
,
169 .suppress_bind_attrs
= true,
170 .pm
= &exynos4x12_isp_pm_ops
,
172 .probe
= exynos4x12_isp_clk_probe
,
175 static int __init
exynos4x12_isp_clk_init(void)
177 return platform_driver_register(&exynos4x12_isp_clk_driver
);
179 core_initcall(exynos4x12_isp_clk_init
);