2 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Common Clock Framework support for S3C2443 and following SoCs.
11 #include <linux/clk-provider.h>
13 #include <linux/of_address.h>
14 #include <linux/syscore_ops.h>
15 #include <linux/reboot.h>
17 #include <dt-bindings/clock/s3c2443.h>
22 /* S3C2416 clock controller register offsets */
27 #define EPLLCON_K 0x1C
44 /* list of PLLs to be registered */
49 static void __iomem
*reg_base
;
51 #ifdef CONFIG_PM_SLEEP
52 static struct samsung_clk_reg_dump
*s3c2443_save
;
55 * list of controller registers to be saved and restored during a
56 * suspend/resume cycle.
58 static unsigned long s3c2443_clk_regs
[] __initdata
= {
73 static int s3c2443_clk_suspend(void)
75 samsung_clk_save(reg_base
, s3c2443_save
,
76 ARRAY_SIZE(s3c2443_clk_regs
));
81 static void s3c2443_clk_resume(void)
83 samsung_clk_restore(reg_base
, s3c2443_save
,
84 ARRAY_SIZE(s3c2443_clk_regs
));
87 static struct syscore_ops s3c2443_clk_syscore_ops
= {
88 .suspend
= s3c2443_clk_suspend
,
89 .resume
= s3c2443_clk_resume
,
92 static void __init
s3c2443_clk_sleep_init(void)
94 s3c2443_save
= samsung_clk_alloc_reg_dump(s3c2443_clk_regs
,
95 ARRAY_SIZE(s3c2443_clk_regs
));
97 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
102 register_syscore_ops(&s3c2443_clk_syscore_ops
);
106 static void __init
s3c2443_clk_sleep_init(void) {}
109 PNAME(epllref_p
) = { "mpllref", "mpllref", "xti", "ext" };
110 PNAME(esysclk_p
) = { "epllref", "epll" };
111 PNAME(mpllref_p
) = { "xti", "mdivclk" };
112 PNAME(msysclk_p
) = { "mpllref", "mpll" };
113 PNAME(armclk_p
) = { "armdiv" , "hclk" };
114 PNAME(i2s0_p
) = { "div_i2s0", "ext_i2s", "epllref", "epllref" };
116 struct samsung_mux_clock s3c2443_common_muxes
[] __initdata
= {
117 MUX(0, "epllref", epllref_p
, CLKSRC
, 7, 2),
118 MUX(ESYSCLK
, "esysclk", esysclk_p
, CLKSRC
, 6, 1),
119 MUX(0, "mpllref", mpllref_p
, CLKSRC
, 3, 1),
120 MUX(MSYSCLK
, "msysclk", msysclk_p
, CLKSRC
, 4, 1),
121 MUX(ARMCLK
, "armclk", armclk_p
, CLKDIV0
, 13, 1),
122 MUX(0, "mux_i2s0", i2s0_p
, CLKSRC
, 14, 2),
125 static struct clk_div_table hclk_d
[] = {
126 { .val
= 0, .div
= 1 },
127 { .val
= 1, .div
= 2 },
128 { .val
= 3, .div
= 4 },
132 static struct clk_div_table mdivclk_d
[] = {
133 { .val
= 0, .div
= 1 },
134 { .val
= 1, .div
= 3 },
135 { .val
= 2, .div
= 5 },
136 { .val
= 3, .div
= 7 },
137 { .val
= 4, .div
= 9 },
138 { .val
= 5, .div
= 11 },
139 { .val
= 6, .div
= 13 },
140 { .val
= 7, .div
= 15 },
144 struct samsung_div_clock s3c2443_common_dividers
[] __initdata
= {
145 DIV_T(0, "mdivclk", "xti", CLKDIV0
, 6, 3, mdivclk_d
),
146 DIV(0, "prediv", "msysclk", CLKDIV0
, 4, 2),
147 DIV_T(HCLK
, "hclk", "prediv", CLKDIV0
, 0, 2, hclk_d
),
148 DIV(PCLK
, "pclk", "hclk", CLKDIV0
, 2, 1),
149 DIV(0, "div_hsspi0_epll", "esysclk", CLKDIV1
, 24, 2),
150 DIV(0, "div_fimd", "esysclk", CLKDIV1
, 16, 8),
151 DIV(0, "div_i2s0", "esysclk", CLKDIV1
, 12, 4),
152 DIV(0, "div_uart", "esysclk", CLKDIV1
, 8, 4),
153 DIV(0, "div_hsmmc1", "esysclk", CLKDIV1
, 6, 2),
154 DIV(0, "div_usbhost", "esysclk", CLKDIV1
, 4, 2),
157 struct samsung_gate_clock s3c2443_common_gates
[] __initdata
= {
158 GATE(SCLK_HSMMC_EXT
, "sclk_hsmmcext", "ext", SCLKCON
, 13, 0, 0),
159 GATE(SCLK_HSMMC1
, "sclk_hsmmc1", "div_hsmmc1", SCLKCON
, 12, 0, 0),
160 GATE(SCLK_FIMD
, "sclk_fimd", "div_fimd", SCLKCON
, 10, 0, 0),
161 GATE(SCLK_I2S0
, "sclk_i2s0", "mux_i2s0", SCLKCON
, 9, 0, 0),
162 GATE(SCLK_UART
, "sclk_uart", "div_uart", SCLKCON
, 8, 0, 0),
163 GATE(SCLK_USBH
, "sclk_usbhost", "div_usbhost", SCLKCON
, 1, 0, 0),
164 GATE(HCLK_DRAM
, "dram", "hclk", HCLKCON
, 19, CLK_IGNORE_UNUSED
, 0),
165 GATE(HCLK_SSMC
, "ssmc", "hclk", HCLKCON
, 18, CLK_IGNORE_UNUSED
, 0),
166 GATE(HCLK_HSMMC1
, "hsmmc1", "hclk", HCLKCON
, 16, 0, 0),
167 GATE(HCLK_USBD
, "usb-device", "hclk", HCLKCON
, 12, 0, 0),
168 GATE(HCLK_USBH
, "usb-host", "hclk", HCLKCON
, 11, 0, 0),
169 GATE(HCLK_LCD
, "lcd", "hclk", HCLKCON
, 9, 0, 0),
170 GATE(HCLK_DMA5
, "dma5", "hclk", HCLKCON
, 5, CLK_IGNORE_UNUSED
, 0),
171 GATE(HCLK_DMA4
, "dma4", "hclk", HCLKCON
, 4, CLK_IGNORE_UNUSED
, 0),
172 GATE(HCLK_DMA3
, "dma3", "hclk", HCLKCON
, 3, CLK_IGNORE_UNUSED
, 0),
173 GATE(HCLK_DMA2
, "dma2", "hclk", HCLKCON
, 2, CLK_IGNORE_UNUSED
, 0),
174 GATE(HCLK_DMA1
, "dma1", "hclk", HCLKCON
, 1, CLK_IGNORE_UNUSED
, 0),
175 GATE(HCLK_DMA0
, "dma0", "hclk", HCLKCON
, 0, CLK_IGNORE_UNUSED
, 0),
176 GATE(PCLK_GPIO
, "gpio", "pclk", PCLKCON
, 13, CLK_IGNORE_UNUSED
, 0),
177 GATE(PCLK_RTC
, "rtc", "pclk", PCLKCON
, 12, 0, 0),
178 GATE(PCLK_WDT
, "wdt", "pclk", PCLKCON
, 11, 0, 0),
179 GATE(PCLK_PWM
, "pwm", "pclk", PCLKCON
, 10, 0, 0),
180 GATE(PCLK_I2S0
, "i2s0", "pclk", PCLKCON
, 9, 0, 0),
181 GATE(PCLK_AC97
, "ac97", "pclk", PCLKCON
, 8, 0, 0),
182 GATE(PCLK_ADC
, "adc", "pclk", PCLKCON
, 7, 0, 0),
183 GATE(PCLK_SPI0
, "spi0", "pclk", PCLKCON
, 6, 0, 0),
184 GATE(PCLK_I2C0
, "i2c0", "pclk", PCLKCON
, 4, 0, 0),
185 GATE(PCLK_UART3
, "uart3", "pclk", PCLKCON
, 3, 0, 0),
186 GATE(PCLK_UART2
, "uart2", "pclk", PCLKCON
, 2, 0, 0),
187 GATE(PCLK_UART1
, "uart1", "pclk", PCLKCON
, 1, 0, 0),
188 GATE(PCLK_UART0
, "uart0", "pclk", PCLKCON
, 0, 0, 0),
191 struct samsung_clock_alias s3c2443_common_aliases
[] __initdata
= {
192 ALIAS(MSYSCLK
, NULL
, "msysclk"),
193 ALIAS(ARMCLK
, NULL
, "armclk"),
194 ALIAS(MPLL
, NULL
, "mpll"),
195 ALIAS(EPLL
, NULL
, "epll"),
196 ALIAS(HCLK
, NULL
, "hclk"),
197 ALIAS(HCLK_SSMC
, NULL
, "nand"),
198 ALIAS(PCLK_UART0
, "s3c2440-uart.0", "uart"),
199 ALIAS(PCLK_UART1
, "s3c2440-uart.1", "uart"),
200 ALIAS(PCLK_UART2
, "s3c2440-uart.2", "uart"),
201 ALIAS(PCLK_UART3
, "s3c2440-uart.3", "uart"),
202 ALIAS(PCLK_UART0
, "s3c2440-uart.0", "clk_uart_baud2"),
203 ALIAS(PCLK_UART1
, "s3c2440-uart.1", "clk_uart_baud2"),
204 ALIAS(PCLK_UART2
, "s3c2440-uart.2", "clk_uart_baud2"),
205 ALIAS(PCLK_UART3
, "s3c2440-uart.3", "clk_uart_baud2"),
206 ALIAS(SCLK_UART
, NULL
, "clk_uart_baud3"),
207 ALIAS(PCLK_PWM
, NULL
, "timers"),
208 ALIAS(PCLK_RTC
, NULL
, "rtc"),
209 ALIAS(PCLK_WDT
, NULL
, "watchdog"),
210 ALIAS(PCLK_ADC
, NULL
, "adc"),
211 ALIAS(PCLK_I2C0
, "s3c2410-i2c.0", "i2c"),
212 ALIAS(HCLK_USBD
, NULL
, "usb-device"),
213 ALIAS(HCLK_USBH
, NULL
, "usb-host"),
214 ALIAS(SCLK_USBH
, NULL
, "usb-bus-host"),
215 ALIAS(PCLK_SPI0
, "s3c2443-spi.0", "spi"),
216 ALIAS(PCLK_SPI0
, "s3c2443-spi.0", "spi_busclk0"),
217 ALIAS(HCLK_HSMMC1
, "s3c-sdhci.1", "hsmmc"),
218 ALIAS(HCLK_HSMMC1
, "s3c-sdhci.1", "mmc_busclk.0"),
219 ALIAS(PCLK_I2S0
, "samsung-i2s.0", "iis"),
220 ALIAS(SCLK_I2S0
, NULL
, "i2s-if"),
221 ALIAS(HCLK_LCD
, NULL
, "lcd"),
222 ALIAS(SCLK_FIMD
, NULL
, "sclk_fimd"),
225 /* S3C2416 specific clocks */
227 static struct samsung_pll_clock s3c2416_pll_clks
[] __initdata
= {
228 [mpll
] = PLL(pll_6552_s3c2416
, MPLL
, "mpll", "mpllref",
229 LOCKCON0
, MPLLCON
, NULL
),
230 [epll
] = PLL(pll_6553
, EPLL
, "epll", "epllref",
231 LOCKCON1
, EPLLCON
, NULL
),
234 PNAME(s3c2416_hsmmc0_p
) = { "sclk_hsmmc0", "sclk_hsmmcext" };
235 PNAME(s3c2416_hsmmc1_p
) = { "sclk_hsmmc1", "sclk_hsmmcext" };
236 PNAME(s3c2416_hsspi0_p
) = { "hsspi0_epll", "hsspi0_mpll" };
238 static struct clk_div_table armdiv_s3c2416_d
[] = {
239 { .val
= 0, .div
= 1 },
240 { .val
= 1, .div
= 2 },
241 { .val
= 2, .div
= 3 },
242 { .val
= 3, .div
= 4 },
243 { .val
= 5, .div
= 6 },
244 { .val
= 7, .div
= 8 },
248 struct samsung_div_clock s3c2416_dividers
[] __initdata
= {
249 DIV_T(ARMDIV
, "armdiv", "msysclk", CLKDIV0
, 9, 3, armdiv_s3c2416_d
),
250 DIV(0, "div_hsspi0_mpll", "msysclk", CLKDIV2
, 0, 4),
251 DIV(0, "div_hsmmc0", "esysclk", CLKDIV2
, 6, 2),
254 struct samsung_mux_clock s3c2416_muxes
[] __initdata
= {
255 MUX(MUX_HSMMC0
, "mux_hsmmc0", s3c2416_hsmmc0_p
, CLKSRC
, 16, 1),
256 MUX(MUX_HSMMC1
, "mux_hsmmc1", s3c2416_hsmmc1_p
, CLKSRC
, 17, 1),
257 MUX(MUX_HSSPI0
, "mux_hsspi0", s3c2416_hsspi0_p
, CLKSRC
, 18, 1),
260 struct samsung_gate_clock s3c2416_gates
[] __initdata
= {
261 GATE(0, "hsspi0_mpll", "div_hsspi0_mpll", SCLKCON
, 19, 0, 0),
262 GATE(0, "hsspi0_epll", "div_hsspi0_epll", SCLKCON
, 14, 0, 0),
263 GATE(0, "sclk_hsmmc0", "div_hsmmc0", SCLKCON
, 6, 0, 0),
264 GATE(HCLK_2D
, "2d", "hclk", HCLKCON
, 20, 0, 0),
265 GATE(HCLK_HSMMC0
, "hsmmc0", "hclk", HCLKCON
, 15, 0, 0),
266 GATE(HCLK_IROM
, "irom", "hclk", HCLKCON
, 13, CLK_IGNORE_UNUSED
, 0),
267 GATE(PCLK_PCM
, "pcm", "pclk", PCLKCON
, 19, 0, 0),
270 struct samsung_clock_alias s3c2416_aliases
[] __initdata
= {
271 ALIAS(HCLK_HSMMC0
, "s3c-sdhci.0", "hsmmc"),
272 ALIAS(HCLK_HSMMC0
, "s3c-sdhci.0", "mmc_busclk.0"),
273 ALIAS(MUX_HSMMC0
, "s3c-sdhci.0", "mmc_busclk.2"),
274 ALIAS(MUX_HSMMC1
, "s3c-sdhci.1", "mmc_busclk.2"),
275 ALIAS(MUX_HSSPI0
, "s3c2443-spi.0", "spi_busclk2"),
276 ALIAS(ARMDIV
, NULL
, "armdiv"),
279 /* S3C2443 specific clocks */
281 static struct samsung_pll_clock s3c2443_pll_clks
[] __initdata
= {
282 [mpll
] = PLL(pll_3000
, MPLL
, "mpll", "mpllref",
283 LOCKCON0
, MPLLCON
, NULL
),
284 [epll
] = PLL(pll_2126
, EPLL
, "epll", "epllref",
285 LOCKCON1
, EPLLCON
, NULL
),
288 static struct clk_div_table armdiv_s3c2443_d
[] = {
289 { .val
= 0, .div
= 1 },
290 { .val
= 8, .div
= 2 },
291 { .val
= 2, .div
= 3 },
292 { .val
= 9, .div
= 4 },
293 { .val
= 10, .div
= 6 },
294 { .val
= 11, .div
= 8 },
295 { .val
= 13, .div
= 12 },
296 { .val
= 15, .div
= 16 },
300 struct samsung_div_clock s3c2443_dividers
[] __initdata
= {
301 DIV_T(ARMDIV
, "armdiv", "msysclk", CLKDIV0
, 9, 4, armdiv_s3c2443_d
),
302 DIV(0, "div_cam", "esysclk", CLKDIV1
, 26, 4),
305 struct samsung_gate_clock s3c2443_gates
[] __initdata
= {
306 GATE(SCLK_HSSPI0
, "sclk_hsspi0", "div_hsspi0_epll", SCLKCON
, 14, 0, 0),
307 GATE(SCLK_CAM
, "sclk_cam", "div_cam", SCLKCON
, 11, 0, 0),
308 GATE(HCLK_CFC
, "cfc", "hclk", HCLKCON
, 17, CLK_IGNORE_UNUSED
, 0),
309 GATE(HCLK_CAM
, "cam", "hclk", HCLKCON
, 8, 0, 0),
310 GATE(PCLK_SPI1
, "spi1", "pclk", PCLKCON
, 15, 0, 0),
311 GATE(PCLK_SDI
, "sdi", "pclk", PCLKCON
, 5, 0, 0),
314 struct samsung_clock_alias s3c2443_aliases
[] __initdata
= {
315 ALIAS(SCLK_HSSPI0
, "s3c2443-spi.0", "spi_busclk2"),
316 ALIAS(SCLK_HSMMC1
, "s3c-sdhci.1", "mmc_busclk.2"),
317 ALIAS(SCLK_CAM
, NULL
, "camif-upll"),
318 ALIAS(PCLK_SPI1
, "s3c2410-spi.0", "spi"),
319 ALIAS(PCLK_SDI
, NULL
, "sdi"),
320 ALIAS(HCLK_CFC
, NULL
, "cfc"),
321 ALIAS(ARMDIV
, NULL
, "armdiv"),
324 /* S3C2450 specific clocks */
326 PNAME(s3c2450_cam_p
) = { "div_cam", "hclk" };
327 PNAME(s3c2450_hsspi1_p
) = { "hsspi1_epll", "hsspi1_mpll" };
328 PNAME(i2s1_p
) = { "div_i2s1", "ext_i2s", "epllref", "epllref" };
330 struct samsung_div_clock s3c2450_dividers
[] __initdata
= {
331 DIV(0, "div_cam", "esysclk", CLKDIV1
, 26, 4),
332 DIV(0, "div_hsspi1_epll", "esysclk", CLKDIV2
, 24, 2),
333 DIV(0, "div_hsspi1_mpll", "msysclk", CLKDIV2
, 16, 4),
334 DIV(0, "div_i2s1", "esysclk", CLKDIV2
, 12, 4),
337 struct samsung_mux_clock s3c2450_muxes
[] __initdata
= {
338 MUX(0, "mux_cam", s3c2450_cam_p
, CLKSRC
, 20, 1),
339 MUX(MUX_HSSPI1
, "mux_hsspi1", s3c2450_hsspi1_p
, CLKSRC
, 19, 1),
340 MUX(0, "mux_i2s1", i2s1_p
, CLKSRC
, 12, 2),
343 struct samsung_gate_clock s3c2450_gates
[] __initdata
= {
344 GATE(SCLK_I2S1
, "sclk_i2s1", "div_i2s1", SCLKCON
, 5, 0, 0),
345 GATE(HCLK_CFC
, "cfc", "hclk", HCLKCON
, 17, 0, 0),
346 GATE(HCLK_CAM
, "cam", "hclk", HCLKCON
, 8, 0, 0),
347 GATE(HCLK_DMA7
, "dma7", "hclk", HCLKCON
, 7, CLK_IGNORE_UNUSED
, 0),
348 GATE(HCLK_DMA6
, "dma6", "hclk", HCLKCON
, 6, CLK_IGNORE_UNUSED
, 0),
349 GATE(PCLK_I2S1
, "i2s1", "pclk", PCLKCON
, 17, 0, 0),
350 GATE(PCLK_I2C1
, "i2c1", "pclk", PCLKCON
, 16, 0, 0),
351 GATE(PCLK_SPI1
, "spi1", "pclk", PCLKCON
, 14, 0, 0),
354 struct samsung_clock_alias s3c2450_aliases
[] __initdata
= {
355 ALIAS(PCLK_SPI1
, "s3c2443-spi.1", "spi"),
356 ALIAS(PCLK_SPI1
, "s3c2443-spi.1", "spi_busclk0"),
357 ALIAS(MUX_HSSPI1
, "s3c2443-spi.1", "spi_busclk2"),
358 ALIAS(PCLK_I2C1
, "s3c2410-i2c.1", "i2c"),
361 static int s3c2443_restart(struct notifier_block
*this,
362 unsigned long mode
, void *cmd
)
364 __raw_writel(0x533c2443, reg_base
+ SWRST
);
368 static struct notifier_block s3c2443_restart_handler
= {
369 .notifier_call
= s3c2443_restart
,
374 * fixed rate clocks generated outside the soc
375 * Only necessary until the devicetree-move is complete
377 struct samsung_fixed_rate_clock s3c2443_common_frate_clks
[] __initdata
= {
378 FRATE(0, "xti", NULL
, 0, 0),
379 FRATE(0, "ext", NULL
, 0, 0),
380 FRATE(0, "ext_i2s", NULL
, 0, 0),
381 FRATE(0, "ext_uart", NULL
, 0, 0),
384 static void __init
s3c2443_common_clk_register_fixed_ext(
385 struct samsung_clk_provider
*ctx
, unsigned long xti_f
)
387 s3c2443_common_frate_clks
[0].fixed_rate
= xti_f
;
388 samsung_clk_register_fixed_rate(ctx
, s3c2443_common_frate_clks
,
389 ARRAY_SIZE(s3c2443_common_frate_clks
));
392 void __init
s3c2443_common_clk_init(struct device_node
*np
, unsigned long xti_f
,
396 struct samsung_clk_provider
*ctx
;
401 reg_base
= of_iomap(np
, 0);
403 panic("%s: failed to map registers\n", __func__
);
406 ctx
= samsung_clk_init(np
, reg_base
, NR_CLKS
);
408 /* Register external clocks only in non-dt cases */
410 s3c2443_common_clk_register_fixed_ext(ctx
, xti_f
);
413 if (current_soc
== S3C2416
|| current_soc
== S3C2450
)
414 samsung_clk_register_pll(ctx
, s3c2416_pll_clks
,
415 ARRAY_SIZE(s3c2416_pll_clks
), reg_base
);
417 samsung_clk_register_pll(ctx
, s3c2443_pll_clks
,
418 ARRAY_SIZE(s3c2443_pll_clks
), reg_base
);
420 /* Register common internal clocks. */
421 samsung_clk_register_mux(ctx
, s3c2443_common_muxes
,
422 ARRAY_SIZE(s3c2443_common_muxes
));
423 samsung_clk_register_div(ctx
, s3c2443_common_dividers
,
424 ARRAY_SIZE(s3c2443_common_dividers
));
425 samsung_clk_register_gate(ctx
, s3c2443_common_gates
,
426 ARRAY_SIZE(s3c2443_common_gates
));
427 samsung_clk_register_alias(ctx
, s3c2443_common_aliases
,
428 ARRAY_SIZE(s3c2443_common_aliases
));
430 /* Register SoC-specific clocks. */
431 switch (current_soc
) {
433 samsung_clk_register_div(ctx
, s3c2450_dividers
,
434 ARRAY_SIZE(s3c2450_dividers
));
435 samsung_clk_register_mux(ctx
, s3c2450_muxes
,
436 ARRAY_SIZE(s3c2450_muxes
));
437 samsung_clk_register_gate(ctx
, s3c2450_gates
,
438 ARRAY_SIZE(s3c2450_gates
));
439 samsung_clk_register_alias(ctx
, s3c2450_aliases
,
440 ARRAY_SIZE(s3c2450_aliases
));
441 /* fall through, as s3c2450 extends the s3c2416 clocks */
443 samsung_clk_register_div(ctx
, s3c2416_dividers
,
444 ARRAY_SIZE(s3c2416_dividers
));
445 samsung_clk_register_mux(ctx
, s3c2416_muxes
,
446 ARRAY_SIZE(s3c2416_muxes
));
447 samsung_clk_register_gate(ctx
, s3c2416_gates
,
448 ARRAY_SIZE(s3c2416_gates
));
449 samsung_clk_register_alias(ctx
, s3c2416_aliases
,
450 ARRAY_SIZE(s3c2416_aliases
));
453 samsung_clk_register_div(ctx
, s3c2443_dividers
,
454 ARRAY_SIZE(s3c2443_dividers
));
455 samsung_clk_register_gate(ctx
, s3c2443_gates
,
456 ARRAY_SIZE(s3c2443_gates
));
457 samsung_clk_register_alias(ctx
, s3c2443_aliases
,
458 ARRAY_SIZE(s3c2443_aliases
));
462 s3c2443_clk_sleep_init();
464 samsung_clk_of_add_provider(np
, ctx
);
466 ret
= register_restart_handler(&s3c2443_restart_handler
);
468 pr_warn("cannot register restart handler, %d\n", ret
);
471 static void __init
s3c2416_clk_init(struct device_node
*np
)
473 s3c2443_common_clk_init(np
, 0, S3C2416
, 0);
475 CLK_OF_DECLARE(s3c2416_clk
, "samsung,s3c2416-clock", s3c2416_clk_init
);
477 static void __init
s3c2443_clk_init(struct device_node
*np
)
479 s3c2443_common_clk_init(np
, 0, S3C2443
, 0);
481 CLK_OF_DECLARE(s3c2443_clk
, "samsung,s3c2443-clock", s3c2443_clk_init
);
483 static void __init
s3c2450_clk_init(struct device_node
*np
)
485 s3c2443_common_clk_init(np
, 0, S3C2450
, 0);
487 CLK_OF_DECLARE(s3c2450_clk
, "samsung,s3c2450-clock", s3c2450_clk_init
);