2 * Clock tree for CSR SiRFprimaII
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
7 * Licensed under GPLv2 or later.
10 #include <linux/module.h>
11 #include <linux/bitops.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16 #include <linux/syscore_ops.h>
19 #include "clk-common.c"
21 static struct clk_dmn clk_mmc01
= {
22 .regofs
= SIRFSOC_CLKC_MMC_CFG
,
25 .init
= &clk_mmc01_init
,
29 static struct clk_dmn clk_mmc23
= {
30 .regofs
= SIRFSOC_CLKC_MMC_CFG
,
33 .init
= &clk_mmc23_init
,
37 static struct clk_dmn clk_mmc45
= {
38 .regofs
= SIRFSOC_CLKC_MMC_CFG
,
41 .init
= &clk_mmc45_init
,
45 static const struct clk_init_data clk_nand_init
= {
48 .parent_names
= std_clk_io_parents
,
49 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
52 static struct clk_std clk_nand
= {
55 .init
= &clk_nand_init
,
59 enum prima2_clk_index
{
60 /* 0 1 2 3 4 5 6 7 8 9 */
61 rtc
, osc
, pll1
, pll2
, pll3
, mem
, sys
, security
, dsp
, gps
,
62 mf
, io
, cpu
, uart0
, uart1
, uart2
, tsc
, i2c0
, i2c1
, spi0
,
63 spi1
, pwmc
, efuse
, pulse
, dmac0
, dmac1
, nand
, audio
, usp0
, usp1
,
64 usp2
, vip
, gfx
, mm
, lcd
, vpp
, mmc01
, mmc23
, mmc45
, usbpll
,
65 usb0
, usb1
, cphif
, maxclk
,
68 static __initdata
struct clk_hw
*prima2_clk_hw_array
[maxclk
] = {
114 static struct clk
*prima2_clks
[maxclk
];
116 static void __init
prima2_clk_init(struct device_node
*np
)
118 struct device_node
*rscnp
;
121 rscnp
= of_find_compatible_node(NULL
, NULL
, "sirf,prima2-rsc");
122 sirfsoc_rsc_vbase
= of_iomap(rscnp
, 0);
123 if (!sirfsoc_rsc_vbase
)
124 panic("unable to map rsc registers\n");
127 sirfsoc_clk_vbase
= of_iomap(np
, 0);
128 if (!sirfsoc_clk_vbase
)
129 panic("unable to map clkc registers\n");
131 /* These are always available (RTC and 26MHz OSC)*/
132 prima2_clks
[rtc
] = clk_register_fixed_rate(NULL
, "rtc", NULL
, 0, 32768);
133 prima2_clks
[osc
] = clk_register_fixed_rate(NULL
, "osc", NULL
, 0,
136 for (i
= pll1
; i
< maxclk
; i
++) {
137 prima2_clks
[i
] = clk_register(NULL
, prima2_clk_hw_array
[i
]);
138 BUG_ON(!prima2_clks
[i
]);
140 clk_register_clkdev(prima2_clks
[cpu
], NULL
, "cpu");
141 clk_register_clkdev(prima2_clks
[io
], NULL
, "io");
142 clk_register_clkdev(prima2_clks
[mem
], NULL
, "mem");
143 clk_register_clkdev(prima2_clks
[mem
], NULL
, "osc");
145 clk_data
.clks
= prima2_clks
;
146 clk_data
.clk_num
= maxclk
;
148 of_clk_add_provider(np
, of_clk_src_onecell_get
, &clk_data
);
150 CLK_OF_DECLARE(prima2_clk
, "sirf,prima2-clkc", prima2_clk_init
);