2 * Copyright 2014 Linaro Ltd.
3 * Copyright (C) 2014 ZTE Corporation.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk-provider.h>
11 #include <linux/err.h>
12 #include <linux/gcd.h>
14 #include <linux/iopoll.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <asm/div64.h>
21 #define to_clk_zx_pll(_hw) container_of(_hw, struct clk_zx_pll, hw)
22 #define to_clk_zx_audio(_hw) container_of(_hw, struct clk_zx_audio, hw)
24 #define CFG0_CFG1_OFFSET 4
28 static int rate_to_idx(struct clk_zx_pll
*zx_pll
, unsigned long rate
)
30 const struct zx_pll_config
*config
= zx_pll
->lookup_table
;
33 for (i
= 0; i
< zx_pll
->count
; i
++) {
34 if (config
[i
].rate
> rate
)
35 return i
> 0 ? i
- 1 : 0;
37 if (config
[i
].rate
== rate
)
44 static int hw_to_idx(struct clk_zx_pll
*zx_pll
)
46 const struct zx_pll_config
*config
= zx_pll
->lookup_table
;
50 hw_cfg0
= readl_relaxed(zx_pll
->reg_base
);
51 hw_cfg1
= readl_relaxed(zx_pll
->reg_base
+ CFG0_CFG1_OFFSET
);
53 /* For matching the value in lookup table */
54 hw_cfg0
&= ~BIT(zx_pll
->lock_bit
);
56 /* Check availability of pd_bit */
57 if (zx_pll
->pd_bit
< 32)
58 hw_cfg0
|= BIT(zx_pll
->pd_bit
);
60 for (i
= 0; i
< zx_pll
->count
; i
++) {
61 if (hw_cfg0
== config
[i
].cfg0
&& hw_cfg1
== config
[i
].cfg1
)
68 static unsigned long zx_pll_recalc_rate(struct clk_hw
*hw
,
69 unsigned long parent_rate
)
71 struct clk_zx_pll
*zx_pll
= to_clk_zx_pll(hw
);
74 idx
= hw_to_idx(zx_pll
);
75 if (unlikely(idx
== -EINVAL
))
78 return zx_pll
->lookup_table
[idx
].rate
;
81 static long zx_pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
84 struct clk_zx_pll
*zx_pll
= to_clk_zx_pll(hw
);
87 idx
= rate_to_idx(zx_pll
, rate
);
89 return zx_pll
->lookup_table
[idx
].rate
;
92 static int zx_pll_set_rate(struct clk_hw
*hw
, unsigned long rate
,
93 unsigned long parent_rate
)
95 /* Assume current cpu is not running on current PLL */
96 struct clk_zx_pll
*zx_pll
= to_clk_zx_pll(hw
);
97 const struct zx_pll_config
*config
;
100 idx
= rate_to_idx(zx_pll
, rate
);
101 config
= &zx_pll
->lookup_table
[idx
];
103 writel_relaxed(config
->cfg0
, zx_pll
->reg_base
);
104 writel_relaxed(config
->cfg1
, zx_pll
->reg_base
+ CFG0_CFG1_OFFSET
);
109 static int zx_pll_enable(struct clk_hw
*hw
)
111 struct clk_zx_pll
*zx_pll
= to_clk_zx_pll(hw
);
114 /* If pd_bit is not available, simply return success. */
115 if (zx_pll
->pd_bit
> 31)
118 reg
= readl_relaxed(zx_pll
->reg_base
);
119 writel_relaxed(reg
& ~BIT(zx_pll
->pd_bit
), zx_pll
->reg_base
);
121 return readl_relaxed_poll_timeout(zx_pll
->reg_base
, reg
,
122 reg
& BIT(zx_pll
->lock_bit
), 0, 100);
125 static void zx_pll_disable(struct clk_hw
*hw
)
127 struct clk_zx_pll
*zx_pll
= to_clk_zx_pll(hw
);
130 if (zx_pll
->pd_bit
> 31)
133 reg
= readl_relaxed(zx_pll
->reg_base
);
134 writel_relaxed(reg
| BIT(zx_pll
->pd_bit
), zx_pll
->reg_base
);
137 static int zx_pll_is_enabled(struct clk_hw
*hw
)
139 struct clk_zx_pll
*zx_pll
= to_clk_zx_pll(hw
);
142 reg
= readl_relaxed(zx_pll
->reg_base
);
144 return !(reg
& BIT(zx_pll
->pd_bit
));
147 const struct clk_ops zx_pll_ops
= {
148 .recalc_rate
= zx_pll_recalc_rate
,
149 .round_rate
= zx_pll_round_rate
,
150 .set_rate
= zx_pll_set_rate
,
151 .enable
= zx_pll_enable
,
152 .disable
= zx_pll_disable
,
153 .is_enabled
= zx_pll_is_enabled
,
155 EXPORT_SYMBOL(zx_pll_ops
);
157 struct clk
*clk_register_zx_pll(const char *name
, const char *parent_name
,
158 unsigned long flags
, void __iomem
*reg_base
,
159 const struct zx_pll_config
*lookup_table
,
160 int count
, spinlock_t
*lock
)
162 struct clk_zx_pll
*zx_pll
;
164 struct clk_init_data init
;
166 zx_pll
= kzalloc(sizeof(*zx_pll
), GFP_KERNEL
);
168 return ERR_PTR(-ENOMEM
);
171 init
.ops
= &zx_pll_ops
;
173 init
.parent_names
= parent_name
? &parent_name
: NULL
;
174 init
.num_parents
= parent_name
? 1 : 0;
176 zx_pll
->reg_base
= reg_base
;
177 zx_pll
->lookup_table
= lookup_table
;
178 zx_pll
->count
= count
;
179 zx_pll
->lock_bit
= LOCK_FLAG
;
180 zx_pll
->pd_bit
= POWER_DOWN
;
182 zx_pll
->hw
.init
= &init
;
184 clk
= clk_register(NULL
, &zx_pll
->hw
);
192 static u32
calc_reg(u32 parent_rate
, u32 rate
)
194 u32 sel
, integ
, fra_div
, tmp
;
195 u64 tmp64
= (u64
)parent_rate
* BPAR
;
198 integ
= (u32
)tmp64
/ BPAR
;
201 tmp
= (u32
)tmp64
% BPAR
;
205 fra_div
= tmp
* 0xff / BPAR
;
206 tmp
= (sel
<< 24) | (integ
<< 16) | (0xff << 8) | fra_div
;
208 /* Set I2S integer divider as 1. This bit is reserved for SPDIF
215 static u32
calc_rate(u32 reg
, u32 parent_rate
)
217 u32 sel
, integ
, fra_div
, tmp
;
218 u64 tmp64
= (u64
)parent_rate
* BPAR
;
221 sel
= (tmp
>> 24) & BIT(0);
222 integ
= (tmp
>> 16) & 0xff;
223 fra_div
= tmp
& 0xff;
225 tmp
= fra_div
* BPAR
;
228 tmp
+= 2 * integ
* BPAR
;
234 static unsigned long zx_audio_recalc_rate(struct clk_hw
*hw
,
235 unsigned long parent_rate
)
237 struct clk_zx_audio
*zx_audio
= to_clk_zx_audio(hw
);
240 reg
= readl_relaxed(zx_audio
->reg_base
);
241 return calc_rate(reg
, parent_rate
);
244 static long zx_audio_round_rate(struct clk_hw
*hw
, unsigned long rate
,
245 unsigned long *prate
)
249 if (rate
* 2 > *prate
)
252 reg
= calc_reg(*prate
, rate
);
253 return calc_rate(reg
, *prate
);
256 static int zx_audio_set_rate(struct clk_hw
*hw
, unsigned long rate
,
257 unsigned long parent_rate
)
259 struct clk_zx_audio
*zx_audio
= to_clk_zx_audio(hw
);
262 reg
= calc_reg(parent_rate
, rate
);
263 writel_relaxed(reg
, zx_audio
->reg_base
);
268 #define ZX_AUDIO_EN BIT(25)
269 static int zx_audio_enable(struct clk_hw
*hw
)
271 struct clk_zx_audio
*zx_audio
= to_clk_zx_audio(hw
);
274 reg
= readl_relaxed(zx_audio
->reg_base
);
275 writel_relaxed(reg
& ~ZX_AUDIO_EN
, zx_audio
->reg_base
);
279 static void zx_audio_disable(struct clk_hw
*hw
)
281 struct clk_zx_audio
*zx_audio
= to_clk_zx_audio(hw
);
284 reg
= readl_relaxed(zx_audio
->reg_base
);
285 writel_relaxed(reg
| ZX_AUDIO_EN
, zx_audio
->reg_base
);
288 static const struct clk_ops zx_audio_ops
= {
289 .recalc_rate
= zx_audio_recalc_rate
,
290 .round_rate
= zx_audio_round_rate
,
291 .set_rate
= zx_audio_set_rate
,
292 .enable
= zx_audio_enable
,
293 .disable
= zx_audio_disable
,
296 struct clk
*clk_register_zx_audio(const char *name
,
297 const char * const parent_name
,
299 void __iomem
*reg_base
)
301 struct clk_zx_audio
*zx_audio
;
303 struct clk_init_data init
;
305 zx_audio
= kzalloc(sizeof(*zx_audio
), GFP_KERNEL
);
307 return ERR_PTR(-ENOMEM
);
310 init
.ops
= &zx_audio_ops
;
312 init
.parent_names
= parent_name
? &parent_name
: NULL
;
313 init
.num_parents
= parent_name
? 1 : 0;
315 zx_audio
->reg_base
= reg_base
;
316 zx_audio
->hw
.init
= &init
;
318 clk
= clk_register(NULL
, &zx_audio
->hw
);
325 #define CLK_AUDIO_DIV_FRAC BIT(0)
326 #define CLK_AUDIO_DIV_INT BIT(1)
327 #define CLK_AUDIO_DIV_UNCOMMON BIT(1)
329 #define CLK_AUDIO_DIV_FRAC_NSHIFT 16
330 #define CLK_AUDIO_DIV_INT_FRAC_RE BIT(16)
331 #define CLK_AUDIO_DIV_INT_FRAC_MAX (0xffff)
332 #define CLK_AUDIO_DIV_INT_FRAC_MIN (0x2)
333 #define CLK_AUDIO_DIV_INT_INT_SHIFT 24
334 #define CLK_AUDIO_DIV_INT_INT_WIDTH 4
336 struct zx_clk_audio_div_table
{
338 unsigned int int_reg
;
339 unsigned int frac_reg
;
342 #define to_clk_zx_audio_div(_hw) container_of(_hw, struct clk_zx_audio_divider, hw)
344 static unsigned long audio_calc_rate(struct clk_zx_audio_divider
*audio_div
,
345 u32 reg_frac
, u32 reg_int
,
346 unsigned long parent_rate
)
348 unsigned long rate
, m
, n
;
350 m
= reg_frac
& 0xffff;
351 n
= (reg_frac
>> 16) & 0xffff;
353 m
= (reg_int
& 0xffff) * n
+ m
;
354 rate
= (parent_rate
* n
) / m
;
359 static void audio_calc_reg(struct clk_zx_audio_divider
*audio_div
,
360 struct zx_clk_audio_div_table
*div_table
,
361 unsigned long rate
, unsigned long parent_rate
)
363 unsigned int reg_int
, reg_frac
;
364 unsigned long m
, n
, div
;
366 reg_int
= parent_rate
/ rate
;
368 if (reg_int
> CLK_AUDIO_DIV_INT_FRAC_MAX
)
369 reg_int
= CLK_AUDIO_DIV_INT_FRAC_MAX
;
370 else if (reg_int
< CLK_AUDIO_DIV_INT_FRAC_MIN
)
372 m
= parent_rate
- rate
* reg_int
;
379 if ((m
>> 16) || (n
>> 16)) {
388 reg_frac
= m
| (n
<< 16);
390 div_table
->rate
= parent_rate
* n
/ (reg_int
* n
+ m
);
391 div_table
->int_reg
= reg_int
;
392 div_table
->frac_reg
= reg_frac
;
395 static unsigned long zx_audio_div_recalc_rate(struct clk_hw
*hw
,
396 unsigned long parent_rate
)
398 struct clk_zx_audio_divider
*zx_audio_div
= to_clk_zx_audio_div(hw
);
399 u32 reg_frac
, reg_int
;
401 reg_frac
= readl_relaxed(zx_audio_div
->reg_base
);
402 reg_int
= readl_relaxed(zx_audio_div
->reg_base
+ 0x4);
404 return audio_calc_rate(zx_audio_div
, reg_frac
, reg_int
, parent_rate
);
407 static long zx_audio_div_round_rate(struct clk_hw
*hw
, unsigned long rate
,
408 unsigned long *prate
)
410 struct clk_zx_audio_divider
*zx_audio_div
= to_clk_zx_audio_div(hw
);
411 struct zx_clk_audio_div_table divt
;
413 audio_calc_reg(zx_audio_div
, &divt
, rate
, *prate
);
415 return audio_calc_rate(zx_audio_div
, divt
.frac_reg
, divt
.int_reg
, *prate
);
418 static int zx_audio_div_set_rate(struct clk_hw
*hw
, unsigned long rate
,
419 unsigned long parent_rate
)
421 struct clk_zx_audio_divider
*zx_audio_div
= to_clk_zx_audio_div(hw
);
422 struct zx_clk_audio_div_table divt
;
425 audio_calc_reg(zx_audio_div
, &divt
, rate
, parent_rate
);
426 if (divt
.rate
!= rate
)
427 pr_debug("the real rate is:%ld", divt
.rate
);
429 writel_relaxed(divt
.frac_reg
, zx_audio_div
->reg_base
);
431 val
= readl_relaxed(zx_audio_div
->reg_base
+ 0x4);
433 val
|= divt
.int_reg
| CLK_AUDIO_DIV_INT_FRAC_RE
;
434 writel_relaxed(val
, zx_audio_div
->reg_base
+ 0x4);
438 val
= readl_relaxed(zx_audio_div
->reg_base
+ 0x4);
439 val
&= ~CLK_AUDIO_DIV_INT_FRAC_RE
;
440 writel_relaxed(val
, zx_audio_div
->reg_base
+ 0x4);
445 const struct clk_ops zx_audio_div_ops
= {
446 .recalc_rate
= zx_audio_div_recalc_rate
,
447 .round_rate
= zx_audio_div_round_rate
,
448 .set_rate
= zx_audio_div_set_rate
,