drivers/gpio/gpio-mxs.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA  02110-1301, USA.
  21  */
  22
  23 #include <linux/err.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/irqdomain.h>
  29 #include <linux/of.h>
  30 #include <linux/of_address.h>
  31 #include <linux/of_device.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/slab.h>
  34 #include <linux/gpio/driver.h>
  35 /* FIXME: for gpio_get_value(), replace this by direct register read */
  36 #include <linux/gpio.h>
  37 #include <linux/module.h>
  38
  39 #define MXS_SET         0x4
  40 #define MXS_CLR         0x8
  41
  42 #define PINCTRL_DOUT(p)         ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
  43 #define PINCTRL_DIN(p)          ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
  44 #define PINCTRL_DOE(p)          ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
  45 #define PINCTRL_PIN2IRQ(p)      ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
  46 #define PINCTRL_IRQEN(p)        ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
  47 #define PINCTRL_IRQLEV(p)       ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
  48 #define PINCTRL_IRQPOL(p)       ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
  49 #define PINCTRL_IRQSTAT(p)      ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
  50
  51 #define GPIO_INT_FALL_EDGE      0x0
  52 #define GPIO_INT_LOW_LEV        0x1
  53 #define GPIO_INT_RISE_EDGE      0x2
  54 #define GPIO_INT_HIGH_LEV       0x3
  55 #define GPIO_INT_LEV_MASK       (1 << 0)
  56 #define GPIO_INT_POL_MASK       (1 << 1)
  57
  58 enum mxs_gpio_id {
  59         IMX23_GPIO,
  60         IMX28_GPIO,
  61 };
  62
  63 struct mxs_gpio_port {
  64         void __iomem *base;
  65         int id;
  66         int irq;
  67         struct irq_domain *domain;
  68         struct gpio_chip gc;
  69         struct device *dev;
  70         enum mxs_gpio_id devid;
  71         u32 both_edges;
  72 };
  73
  74 static inline int is_imx23_gpio(struct mxs_gpio_port *port)
  75 {
  76         return port->devid == IMX23_GPIO;
  77 }
  78
  79 static inline int is_imx28_gpio(struct mxs_gpio_port *port)
  80 {
  81         return port->devid == IMX28_GPIO;
  82 }
  83
  84 /* Note: This driver assumes 32 GPIOs are handled in one register */
  85
  86 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  87 {
  88         u32 val;
  89         u32 pin_mask = 1 << d->hwirq;
  90         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  91         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  92         struct mxs_gpio_port *port = gc->private;
  93         void __iomem *pin_addr;
  94         int edge;
  95
  96         if (!(ct->type & type))
  97                 if (irq_setup_alt_chip(d, type))
  98                         return -EINVAL;
  99
 100         port->both_edges &= ~pin_mask;
 101         switch (type) {
 102         case IRQ_TYPE_EDGE_BOTH:
 103                 val = gpio_get_value(port->gc.base + d->hwirq);
 104                 if (val)
 105                         edge = GPIO_INT_FALL_EDGE;
 106                 else
 107                         edge = GPIO_INT_RISE_EDGE;
 108                 port->both_edges |= pin_mask;
 109                 break;
 110         case IRQ_TYPE_EDGE_RISING:
 111                 edge = GPIO_INT_RISE_EDGE;
 112                 break;
 113         case IRQ_TYPE_EDGE_FALLING:
 114                 edge = GPIO_INT_FALL_EDGE;
 115                 break;
 116         case IRQ_TYPE_LEVEL_LOW:
 117                 edge = GPIO_INT_LOW_LEV;
 118                 break;
 119         case IRQ_TYPE_LEVEL_HIGH:
 120                 edge = GPIO_INT_HIGH_LEV;
 121                 break;
 122         default:
 123                 return -EINVAL;
 124         }
 125
 126         /* set level or edge */
 127         pin_addr = port->base + PINCTRL_IRQLEV(port);
 128         if (edge & GPIO_INT_LEV_MASK) {
 129                 writel(pin_mask, pin_addr + MXS_SET);
 130                 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
 131         } else {
 132                 writel(pin_mask, pin_addr + MXS_CLR);
 133                 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
 134         }
 135
 136         /* set polarity */
 137         pin_addr = port->base + PINCTRL_IRQPOL(port);
 138         if (edge & GPIO_INT_POL_MASK)
 139                 writel(pin_mask, pin_addr + MXS_SET);
 140         else
 141                 writel(pin_mask, pin_addr + MXS_CLR);
 142
 143         writel(pin_mask,
 144                port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 145
 146         return 0;
 147 }
 148
 149 static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
 150 {
 151         u32 bit, val, edge;
 152         void __iomem *pin_addr;
 153
 154         bit = 1 << gpio;
 155
 156         pin_addr = port->base + PINCTRL_IRQPOL(port);
 157         val = readl(pin_addr);
 158         edge = val & bit;
 159
 160         if (edge)
 161                 writel(bit, pin_addr + MXS_CLR);
 162         else
 163                 writel(bit, pin_addr + MXS_SET);
 164 }
 165
 166 /* MXS has one interrupt *per* gpio port */
 167 static void mxs_gpio_irq_handler(struct irq_desc *desc)
 168 {
 169         u32 irq_stat;
 170         struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
 171
 172         desc->irq_data.chip->irq_ack(&desc->irq_data);
 173
 174         irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
 175                         readl(port->base + PINCTRL_IRQEN(port));
 176
 177         while (irq_stat != 0) {
 178                 int irqoffset = fls(irq_stat) - 1;
 179                 if (port->both_edges & (1 << irqoffset))
 180                         mxs_flip_edge(port, irqoffset);
 181
 182                 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
 183                 irq_stat &= ~(1 << irqoffset);
 184         }
 185 }
 186
 187 /*
 188  * Set interrupt number "irq" in the GPIO as a wake-up source.
 189  * While system is running, all registered GPIO interrupts need to have
 190  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 191  * need to have wake-up enabled.
 192  * @param  irq          interrupt source number
 193  * @param  enable       enable as wake-up if equal to non-zero
 194  * @return       This function returns 0 on success.
 195  */
 196 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 197 {
 198         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 199         struct mxs_gpio_port *port = gc->private;
 200
 201         if (enable)
 202                 enable_irq_wake(port->irq);
 203         else
 204                 disable_irq_wake(port->irq);
 205
 206         return 0;
 207 }
 208
 209 static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
 210 {
 211         struct irq_chip_generic *gc;
 212         struct irq_chip_type *ct;
 213         int rv;
 214
 215         gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
 216                                          port->base, handle_level_irq);
 217         if (!gc)
 218                 return -ENOMEM;
 219
 220         gc->private = port;
 221
 222         ct = &gc->chip_types[0];
 223         ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
 224         ct->chip.irq_ack = irq_gc_ack_set_bit;
 225         ct->chip.irq_mask = irq_gc_mask_disable_reg;
 226         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 227         ct->chip.irq_set_type = mxs_gpio_set_irq_type;
 228         ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
 229         ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
 230         ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
 231         ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
 232         ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
 233
 234         ct = &gc->chip_types[1];
 235         ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 236         ct->chip.irq_ack = irq_gc_ack_set_bit;
 237         ct->chip.irq_mask = irq_gc_mask_disable_reg;
 238         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 239         ct->chip.irq_set_type = mxs_gpio_set_irq_type;
 240         ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
 241         ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
 242         ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
 243         ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
 244         ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
 245         ct->handler = handle_level_irq;
 246
 247         rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
 248                                          IRQ_GC_INIT_NESTED_LOCK,
 249                                          IRQ_NOREQUEST, 0);
 250
 251         return rv;
 252 }
 253
 254 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 255 {
 256         struct mxs_gpio_port *port = gpiochip_get_data(gc);
 257
 258         return irq_find_mapping(port->domain, offset);
 259 }
 260
 261 static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
 262 {
 263         struct mxs_gpio_port *port = gpiochip_get_data(gc);
 264         u32 mask = 1 << offset;
 265         u32 dir;
 266
 267         dir = readl(port->base + PINCTRL_DOE(port));
 268         return !(dir & mask);
 269 }
 270
 271 static const struct platform_device_id mxs_gpio_ids[] = {
 272         {
 273                 .name = "imx23-gpio",
 274                 .driver_data = IMX23_GPIO,
 275         }, {
 276                 .name = "imx28-gpio",
 277                 .driver_data = IMX28_GPIO,
 278         }, {
 279                 /* sentinel */
 280         }
 281 };
 282 MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
 283
 284 static const struct of_device_id mxs_gpio_dt_ids[] = {
 285         { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
 286         { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
 287         { /* sentinel */ }
 288 };
 289 MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
 290
 291 static int mxs_gpio_probe(struct platform_device *pdev)
 292 {
 293         const struct of_device_id *of_id =
 294                         of_match_device(mxs_gpio_dt_ids, &pdev->dev);
 295         struct device_node *np = pdev->dev.of_node;
 296         struct device_node *parent;
 297         static void __iomem *base;
 298         struct mxs_gpio_port *port;
 299         int irq_base;
 300         int err;
 301
 302         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
 303         if (!port)
 304                 return -ENOMEM;
 305
 306         port->id = of_alias_get_id(np, "gpio");
 307         if (port->id < 0)
 308                 return port->id;
 309         port->devid = (enum mxs_gpio_id) of_id->data;
 310         port->dev = &pdev->dev;
 311         port->irq = platform_get_irq(pdev, 0);
 312         if (port->irq < 0)
 313                 return port->irq;
 314
 315         /*
 316          * map memory region only once, as all the gpio ports
 317          * share the same one
 318          */
 319         if (!base) {
 320                 parent = of_get_parent(np);
 321                 base = of_iomap(parent, 0);
 322                 of_node_put(parent);
 323                 if (!base)
 324                         return -EADDRNOTAVAIL;
 325         }
 326         port->base = base;
 327
 328         /* initially disable the interrupts */
 329         writel(0, port->base + PINCTRL_PIN2IRQ(port));
 330         writel(0, port->base + PINCTRL_IRQEN(port));
 331
 332         /* clear address has to be used to clear IRQSTAT bits */
 333         writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 334
 335         irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
 336         if (irq_base < 0) {
 337                 err = irq_base;
 338                 goto out_iounmap;
 339         }
 340
 341         port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
 342                                              &irq_domain_simple_ops, NULL);
 343         if (!port->domain) {
 344                 err = -ENODEV;
 345                 goto out_iounmap;
 346         }
 347
 348         /* gpio-mxs can be a generic irq chip */
 349         err = mxs_gpio_init_gc(port, irq_base);
 350         if (err < 0)
 351                 goto out_irqdomain_remove;
 352
 353         /* setup one handler for each entry */
 354         irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
 355                                          port);
 356
 357         err = bgpio_init(&port->gc, &pdev->dev, 4,
 358                          port->base + PINCTRL_DIN(port),
 359                          port->base + PINCTRL_DOUT(port) + MXS_SET,
 360                          port->base + PINCTRL_DOUT(port) + MXS_CLR,
 361                          port->base + PINCTRL_DOE(port), NULL, 0);
 362         if (err)
 363                 goto out_irqdomain_remove;
 364
 365         port->gc.to_irq = mxs_gpio_to_irq;
 366         port->gc.get_direction = mxs_gpio_get_direction;
 367         port->gc.base = port->id * 32;
 368
 369         err = gpiochip_add_data(&port->gc, port);
 370         if (err)
 371                 goto out_irqdomain_remove;
 372
 373         return 0;
 374
 375 out_irqdomain_remove:
 376         irq_domain_remove(port->domain);
 377 out_iounmap:
 378         iounmap(port->base);
 379         return err;
 380 }
 381
 382 static struct platform_driver mxs_gpio_driver = {
 383         .driver         = {
 384                 .name   = "gpio-mxs",
 385                 .of_match_table = mxs_gpio_dt_ids,
 386                 .suppress_bind_attrs = true,
 387         },
 388         .probe          = mxs_gpio_probe,
 389         .id_table       = mxs_gpio_ids,
 390 };
 391
 392 static int __init mxs_gpio_init(void)
 393 {
 394         return platform_driver_register(&mxs_gpio_driver);
 395 }
 396 postcore_initcall(mxs_gpio_init);
 397
 398 MODULE_AUTHOR("Freescale Semiconductor, "
 399               "Daniel Mack <danielncaiaq.de>, "
 400               "Juergen Beisert <kernel@pengutronix.de>");
 401 MODULE_DESCRIPTION("Freescale MXS GPIO");
 402 MODULE_LICENSE("GPL");