drivers/gpu/ipu-v3/ipu-prg.c

   1 /*
   2  * Copyright (c) 2016-2017 Lucas Stach, Pengutronix
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  */
  13
  14 #include <drm/drm_fourcc.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/regmap.h>
  25 #include <video/imx-ipu-v3.h>
  26
  27 #include "ipu-prv.h"
  28
  29 #define IPU_PRG_CTL                             0x00
  30 #define  IPU_PRG_CTL_BYPASS(i)                  (1 << (0 + i))
  31 #define  IPU_PRG_CTL_SOFT_ARID_MASK             0x3
  32 #define  IPU_PRG_CTL_SOFT_ARID_SHIFT(i)         (8 + i * 2)
  33 #define  IPU_PRG_CTL_SOFT_ARID(i, v)            ((v & 0x3) << (8 + 2 * i))
  34 #define  IPU_PRG_CTL_SO(i)                      (1 << (16 + i))
  35 #define  IPU_PRG_CTL_VFLIP(i)                   (1 << (19 + i))
  36 #define  IPU_PRG_CTL_BLOCK_MODE(i)              (1 << (22 + i))
  37 #define  IPU_PRG_CTL_CNT_LOAD_EN(i)             (1 << (25 + i))
  38 #define  IPU_PRG_CTL_SOFTRST                    (1 << 30)
  39 #define  IPU_PRG_CTL_SHADOW_EN                  (1 << 31)
  40
  41 #define IPU_PRG_STATUS                          0x04
  42 #define  IPU_PRG_STATUS_BUFFER0_READY(i)        (1 << (0 + i * 2))
  43 #define  IPU_PRG_STATUS_BUFFER1_READY(i)        (1 << (1 + i * 2))
  44
  45 #define IPU_PRG_QOS                             0x08
  46 #define  IPU_PRG_QOS_ARID_MASK                  0xf
  47 #define  IPU_PRG_QOS_ARID_SHIFT(i)              (0 + i * 4)
  48
  49 #define IPU_PRG_REG_UPDATE                      0x0c
  50 #define  IPU_PRG_REG_UPDATE_REG_UPDATE          (1 << 0)
  51
  52 #define IPU_PRG_STRIDE(i)                       (0x10 + i * 0x4)
  53 #define  IPU_PRG_STRIDE_STRIDE_MASK             0x3fff
  54
  55 #define IPU_PRG_CROP_LINE                       0x1c
  56
  57 #define IPU_PRG_THD                             0x20
  58
  59 #define IPU_PRG_BADDR(i)                        (0x24 + i * 0x4)
  60
  61 #define IPU_PRG_OFFSET(i)                       (0x30 + i * 0x4)
  62
  63 #define IPU_PRG_ILO(i)                          (0x3c + i * 0x4)
  64
  65 #define IPU_PRG_HEIGHT(i)                       (0x48 + i * 0x4)
  66 #define  IPU_PRG_HEIGHT_PRE_HEIGHT_MASK         0xfff
  67 #define  IPU_PRG_HEIGHT_PRE_HEIGHT_SHIFT        0
  68 #define  IPU_PRG_HEIGHT_IPU_HEIGHT_MASK         0xfff
  69 #define  IPU_PRG_HEIGHT_IPU_HEIGHT_SHIFT        16
  70
  71 struct ipu_prg_channel {
  72         bool                    enabled;
  73         int                     used_pre;
  74 };
  75
  76 struct ipu_prg {
  77         struct list_head        list;
  78         struct device           *dev;
  79         int                     id;
  80
  81         void __iomem            *regs;
  82         struct clk              *clk_ipg, *clk_axi;
  83         struct regmap           *iomuxc_gpr;
  84         struct ipu_pre          *pres[3];
  85
  86         struct ipu_prg_channel  chan[3];
  87 };
  88
  89 static DEFINE_MUTEX(ipu_prg_list_mutex);
  90 static LIST_HEAD(ipu_prg_list);
  91
  92 struct ipu_prg *
  93 ipu_prg_lookup_by_phandle(struct device *dev, const char *name, int ipu_id)
  94 {
  95         struct device_node *prg_node = of_parse_phandle(dev->of_node,
  96                                                         name, 0);
  97         struct ipu_prg *prg;
  98
  99         mutex_lock(&ipu_prg_list_mutex);
 100         list_for_each_entry(prg, &ipu_prg_list, list) {
 101                 if (prg_node == prg->dev->of_node) {
 102                         mutex_unlock(&ipu_prg_list_mutex);
 103                         device_link_add(dev, prg->dev, DL_FLAG_AUTOREMOVE);
 104                         prg->id = ipu_id;
 105                         of_node_put(prg_node);
 106                         return prg;
 107                 }
 108         }
 109         mutex_unlock(&ipu_prg_list_mutex);
 110
 111         of_node_put(prg_node);
 112
 113         return NULL;
 114 }
 115
 116 int ipu_prg_max_active_channels(void)
 117 {
 118         return ipu_pre_get_available_count();
 119 }
 120 EXPORT_SYMBOL_GPL(ipu_prg_max_active_channels);
 121
 122 bool ipu_prg_present(struct ipu_soc *ipu)
 123 {
 124         if (ipu->prg_priv)
 125                 return true;
 126
 127         return false;
 128 }
 129 EXPORT_SYMBOL_GPL(ipu_prg_present);
 130
 131 bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
 132                               uint64_t modifier)
 133 {
 134         const struct drm_format_info *info = drm_format_info(format);
 135
 136         if (info->num_planes != 1)
 137                 return false;
 138
 139         switch (modifier) {
 140         case DRM_FORMAT_MOD_LINEAR:
 141         case DRM_FORMAT_MOD_VIVANTE_TILED:
 142         case DRM_FORMAT_MOD_VIVANTE_SUPER_TILED:
 143                 return true;
 144         default:
 145                 return false;
 146         }
 147 }
 148 EXPORT_SYMBOL_GPL(ipu_prg_format_supported);
 149
 150 int ipu_prg_enable(struct ipu_soc *ipu)
 151 {
 152         struct ipu_prg *prg = ipu->prg_priv;
 153
 154         if (!prg)
 155                 return 0;
 156
 157         return pm_runtime_get_sync(prg->dev);
 158 }
 159 EXPORT_SYMBOL_GPL(ipu_prg_enable);
 160
 161 void ipu_prg_disable(struct ipu_soc *ipu)
 162 {
 163         struct ipu_prg *prg = ipu->prg_priv;
 164
 165         if (!prg)
 166                 return;
 167
 168         pm_runtime_put(prg->dev);
 169 }
 170 EXPORT_SYMBOL_GPL(ipu_prg_disable);
 171
 172 /*
 173  * The channel configuartion functions below are not thread safe, as they
 174  * must be only called from the atomic commit path in the DRM driver, which
 175  * is properly serialized.
 176  */
 177 static int ipu_prg_ipu_to_prg_chan(int ipu_chan)
 178 {
 179         /*
 180          * This isn't clearly documented in the RM, but IPU to PRG channel
 181          * assignment is fixed, as only with this mapping the control signals
 182          * match up.
 183          */
 184         switch (ipu_chan) {
 185         case IPUV3_CHANNEL_MEM_BG_SYNC:
 186                 return 0;
 187         case IPUV3_CHANNEL_MEM_FG_SYNC:
 188                 return 1;
 189         case IPUV3_CHANNEL_MEM_DC_SYNC:
 190                 return 2;
 191         default:
 192                 return -EINVAL;
 193         }
 194 }
 195
 196 static int ipu_prg_get_pre(struct ipu_prg *prg, int prg_chan)
 197 {
 198         int i, ret;
 199
 200         /* channel 0 is special as it is hardwired to one of the PREs */
 201         if (prg_chan == 0) {
 202                 ret = ipu_pre_get(prg->pres[0]);
 203                 if (ret)
 204                         goto fail;
 205                 prg->chan[prg_chan].used_pre = 0;
 206                 return 0;
 207         }
 208
 209         for (i = 1; i < 3; i++) {
 210                 ret = ipu_pre_get(prg->pres[i]);
 211                 if (!ret) {
 212                         u32 val, mux;
 213                         int shift;
 214
 215                         prg->chan[prg_chan].used_pre = i;
 216
 217                         /* configure the PRE to PRG channel mux */
 218                         shift = (i == 1) ? 12 : 14;
 219                         mux = (prg->id << 1) | (prg_chan - 1);
 220                         regmap_update_bits(prg->iomuxc_gpr, IOMUXC_GPR5,
 221                                            0x3 << shift, mux << shift);
 222
 223                         /* check other mux, must not point to same channel */
 224                         shift = (i == 1) ? 14 : 12;
 225                         regmap_read(prg->iomuxc_gpr, IOMUXC_GPR5, &val);
 226                         if (((val >> shift) & 0x3) == mux) {
 227                                 regmap_update_bits(prg->iomuxc_gpr, IOMUXC_GPR5,
 228                                                    0x3 << shift,
 229                                                    (mux ^ 0x1) << shift);
 230                         }
 231
 232                         return 0;
 233                 }
 234         }
 235
 236 fail:
 237         dev_err(prg->dev, "could not get PRE for PRG chan %d", prg_chan);
 238         return ret;
 239 }
 240
 241 static void ipu_prg_put_pre(struct ipu_prg *prg, int prg_chan)
 242 {
 243         struct ipu_prg_channel *chan = &prg->chan[prg_chan];
 244
 245         ipu_pre_put(prg->pres[chan->used_pre]);
 246         chan->used_pre = -1;
 247 }
 248
 249 void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan)
 250 {
 251         int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
 252         struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
 253         struct ipu_prg_channel *chan;
 254         u32 val;
 255
 256         if (prg_chan < 0)
 257                 return;
 258
 259         chan = &prg->chan[prg_chan];
 260         if (!chan->enabled)
 261                 return;
 262
 263         pm_runtime_get_sync(prg->dev);
 264
 265         val = readl(prg->regs + IPU_PRG_CTL);
 266         val |= IPU_PRG_CTL_BYPASS(prg_chan);
 267         writel(val, prg->regs + IPU_PRG_CTL);
 268
 269         val = IPU_PRG_REG_UPDATE_REG_UPDATE;
 270         writel(val, prg->regs + IPU_PRG_REG_UPDATE);
 271
 272         pm_runtime_put(prg->dev);
 273
 274         ipu_prg_put_pre(prg, prg_chan);
 275
 276         chan->enabled = false;
 277 }
 278 EXPORT_SYMBOL_GPL(ipu_prg_channel_disable);
 279
 280 int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
 281                               unsigned int axi_id, unsigned int width,
 282                               unsigned int height, unsigned int stride,
 283                               u32 format, uint64_t modifier, unsigned long *eba)
 284 {
 285         int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
 286         struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
 287         struct ipu_prg_channel *chan;
 288         u32 val;
 289         int ret;
 290
 291         if (prg_chan < 0)
 292                 return prg_chan;
 293
 294         chan = &prg->chan[prg_chan];
 295
 296         if (chan->enabled) {
 297                 ipu_pre_update(prg->pres[chan->used_pre], *eba);
 298                 return 0;
 299         }
 300
 301         ret = ipu_prg_get_pre(prg, prg_chan);
 302         if (ret)
 303                 return ret;
 304
 305         ipu_pre_configure(prg->pres[chan->used_pre],
 306                           width, height, stride, format, modifier, *eba);
 307
 308
 309         pm_runtime_get_sync(prg->dev);
 310
 311         val = (stride - 1) & IPU_PRG_STRIDE_STRIDE_MASK;
 312         writel(val, prg->regs + IPU_PRG_STRIDE(prg_chan));
 313
 314         val = ((height & IPU_PRG_HEIGHT_PRE_HEIGHT_MASK) <<
 315                IPU_PRG_HEIGHT_PRE_HEIGHT_SHIFT) |
 316               ((height & IPU_PRG_HEIGHT_IPU_HEIGHT_MASK) <<
 317                IPU_PRG_HEIGHT_IPU_HEIGHT_SHIFT);
 318         writel(val, prg->regs + IPU_PRG_HEIGHT(prg_chan));
 319
 320         val = ipu_pre_get_baddr(prg->pres[chan->used_pre]);
 321         *eba = val;
 322         writel(val, prg->regs + IPU_PRG_BADDR(prg_chan));
 323
 324         val = readl(prg->regs + IPU_PRG_CTL);
 325         /* config AXI ID */
 326         val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK <<
 327                  IPU_PRG_CTL_SOFT_ARID_SHIFT(prg_chan));
 328         val |= IPU_PRG_CTL_SOFT_ARID(prg_chan, axi_id);
 329         /* enable channel */
 330         val &= ~IPU_PRG_CTL_BYPASS(prg_chan);
 331         writel(val, prg->regs + IPU_PRG_CTL);
 332
 333         val = IPU_PRG_REG_UPDATE_REG_UPDATE;
 334         writel(val, prg->regs + IPU_PRG_REG_UPDATE);
 335
 336         /* wait for both double buffers to be filled */
 337         readl_poll_timeout(prg->regs + IPU_PRG_STATUS, val,
 338                            (val & IPU_PRG_STATUS_BUFFER0_READY(prg_chan)) &&
 339                            (val & IPU_PRG_STATUS_BUFFER1_READY(prg_chan)),
 340                            5, 1000);
 341
 342         pm_runtime_put(prg->dev);
 343
 344         chan->enabled = true;
 345         return 0;
 346 }
 347 EXPORT_SYMBOL_GPL(ipu_prg_channel_configure);
 348
 349 static int ipu_prg_probe(struct platform_device *pdev)
 350 {
 351         struct device *dev = &pdev->dev;
 352         struct resource *res;
 353         struct ipu_prg *prg;
 354         u32 val;
 355         int i, ret;
 356
 357         prg = devm_kzalloc(dev, sizeof(*prg), GFP_KERNEL);
 358         if (!prg)
 359                 return -ENOMEM;
 360
 361         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 362         prg->regs = devm_ioremap_resource(&pdev->dev, res);
 363         if (IS_ERR(prg->regs))
 364                 return PTR_ERR(prg->regs);
 365
 366
 367         prg->clk_ipg = devm_clk_get(dev, "ipg");
 368         if (IS_ERR(prg->clk_ipg))
 369                 return PTR_ERR(prg->clk_ipg);
 370
 371         prg->clk_axi = devm_clk_get(dev, "axi");
 372         if (IS_ERR(prg->clk_axi))
 373                 return PTR_ERR(prg->clk_axi);
 374
 375         prg->iomuxc_gpr =
 376                 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 377         if (IS_ERR(prg->iomuxc_gpr))
 378                 return PTR_ERR(prg->iomuxc_gpr);
 379
 380         for (i = 0; i < 3; i++) {
 381                 prg->pres[i] = ipu_pre_lookup_by_phandle(dev, "fsl,pres", i);
 382                 if (!prg->pres[i])
 383                         return -EPROBE_DEFER;
 384         }
 385
 386         ret = clk_prepare_enable(prg->clk_ipg);
 387         if (ret)
 388                 return ret;
 389
 390         ret = clk_prepare_enable(prg->clk_axi);
 391         if (ret) {
 392                 clk_disable_unprepare(prg->clk_ipg);
 393                 return ret;
 394         }
 395
 396         /* init to free running mode */
 397         val = readl(prg->regs + IPU_PRG_CTL);
 398         val |= IPU_PRG_CTL_SHADOW_EN;
 399         writel(val, prg->regs + IPU_PRG_CTL);
 400
 401         /* disable address threshold */
 402         writel(0xffffffff, prg->regs + IPU_PRG_THD);
 403
 404         pm_runtime_set_active(dev);
 405         pm_runtime_enable(dev);
 406
 407         prg->dev = dev;
 408         platform_set_drvdata(pdev, prg);
 409         mutex_lock(&ipu_prg_list_mutex);
 410         list_add(&prg->list, &ipu_prg_list);
 411         mutex_unlock(&ipu_prg_list_mutex);
 412
 413         return 0;
 414 }
 415
 416 static int ipu_prg_remove(struct platform_device *pdev)
 417 {
 418         struct ipu_prg *prg = platform_get_drvdata(pdev);
 419
 420         mutex_lock(&ipu_prg_list_mutex);
 421         list_del(&prg->list);
 422         mutex_unlock(&ipu_prg_list_mutex);
 423
 424         return 0;
 425 }
 426
 427 #ifdef CONFIG_PM
 428 static int prg_suspend(struct device *dev)
 429 {
 430         struct ipu_prg *prg = dev_get_drvdata(dev);
 431
 432         clk_disable_unprepare(prg->clk_axi);
 433         clk_disable_unprepare(prg->clk_ipg);
 434
 435         return 0;
 436 }
 437
 438 static int prg_resume(struct device *dev)
 439 {
 440         struct ipu_prg *prg = dev_get_drvdata(dev);
 441         int ret;
 442
 443         ret = clk_prepare_enable(prg->clk_ipg);
 444         if (ret)
 445                 return ret;
 446
 447         ret = clk_prepare_enable(prg->clk_axi);
 448         if (ret) {
 449                 clk_disable_unprepare(prg->clk_ipg);
 450                 return ret;
 451         }
 452
 453         return 0;
 454 }
 455 #endif
 456
 457 static const struct dev_pm_ops prg_pm_ops = {
 458         SET_RUNTIME_PM_OPS(prg_suspend, prg_resume, NULL)
 459 };
 460
 461 static const struct of_device_id ipu_prg_dt_ids[] = {
 462         { .compatible = "fsl,imx6qp-prg", },
 463         { /* sentinel */ },
 464 };
 465
 466 struct platform_driver ipu_prg_drv = {
 467         .probe          = ipu_prg_probe,
 468         .remove         = ipu_prg_remove,
 469         .driver         = {
 470                 .name   = "imx-ipu-prg",
 471                 .pm     = &prg_pm_ops,
 472                 .of_match_table = ipu_prg_dt_ids,
 473         },
 474 };