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Linux 4.16.11
[linux/fpc-iii.git] / drivers / iio / accel / mxc4005.c
blob58099e40d717e3e53e102c701834db611fbcb3ad
1 /*
2 * 3-axis accelerometer driver for MXC4005XC Memsic sensor
3 *
4 * Copyright (c) 2014, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16 #include <linux/module.h>
17 #include <linux/i2c.h>
18 #include <linux/iio/iio.h>
19 #include <linux/acpi.h>
20 #include <linux/regmap.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/trigger.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/triggered_buffer.h>
25 #include <linux/iio/trigger_consumer.h>
26
27 #define MXC4005_DRV_NAME "mxc4005"
28 #define MXC4005_IRQ_NAME "mxc4005_event"
29 #define MXC4005_REGMAP_NAME "mxc4005_regmap"
30
31 #define MXC4005_REG_XOUT_UPPER 0x03
32 #define MXC4005_REG_XOUT_LOWER 0x04
33 #define MXC4005_REG_YOUT_UPPER 0x05
34 #define MXC4005_REG_YOUT_LOWER 0x06
35 #define MXC4005_REG_ZOUT_UPPER 0x07
36 #define MXC4005_REG_ZOUT_LOWER 0x08
37
38 #define MXC4005_REG_INT_MASK1 0x0B
39 #define MXC4005_REG_INT_MASK1_BIT_DRDYE 0x01
40
41 #define MXC4005_REG_INT_CLR1 0x01
42 #define MXC4005_REG_INT_CLR1_BIT_DRDYC 0x01
43
44 #define MXC4005_REG_CONTROL 0x0D
45 #define MXC4005_REG_CONTROL_MASK_FSR GENMASK(6, 5)
46 #define MXC4005_CONTROL_FSR_SHIFT 5
47
48 #define MXC4005_REG_DEVICE_ID 0x0E
49
50 enum mxc4005_axis {
51 AXIS_X,
52 AXIS_Y,
53 AXIS_Z,
54 };
55
56 enum mxc4005_range {
57 MXC4005_RANGE_2G,
58 MXC4005_RANGE_4G,
59 MXC4005_RANGE_8G,
60 };
61
62 struct mxc4005_data {
63 struct device *dev;
64 struct mutex mutex;
65 struct regmap *regmap;
66 struct iio_trigger *dready_trig;
67 __be16 buffer[8];
68 bool trigger_enabled;
69 };
70
71 /*
72 * MXC4005 can operate in the following ranges:
73 * +/- 2G, 4G, 8G (the default +/-2G)
74 *
75 * (2 + 2) * 9.81 / (2^12 - 1) = 0.009582
76 * (4 + 4) * 9.81 / (2^12 - 1) = 0.019164
77 * (8 + 8) * 9.81 / (2^12 - 1) = 0.038329
78 */
79 static const struct {
80 u8 range;
81 int scale;
82 } mxc4005_scale_table[] = {
83 {MXC4005_RANGE_2G, 9582},
84 {MXC4005_RANGE_4G, 19164},
85 {MXC4005_RANGE_8G, 38329},
86 };
87
88
89 static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329");
90
91 static struct attribute *mxc4005_attributes[] = {
92 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
93 NULL,
94 };
95
96 static const struct attribute_group mxc4005_attrs_group = {
97 .attrs = mxc4005_attributes,
98 };
99
100 static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg)
101 {
102 switch (reg) {
103 case MXC4005_REG_XOUT_UPPER:
104 case MXC4005_REG_XOUT_LOWER:
105 case MXC4005_REG_YOUT_UPPER:
106 case MXC4005_REG_YOUT_LOWER:
107 case MXC4005_REG_ZOUT_UPPER:
108 case MXC4005_REG_ZOUT_LOWER:
109 case MXC4005_REG_DEVICE_ID:
110 case MXC4005_REG_CONTROL:
111 return true;
112 default:
113 return false;
114 }
115 }
116
117 static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg)
118 {
119 switch (reg) {
120 case MXC4005_REG_INT_CLR1:
121 case MXC4005_REG_INT_MASK1:
122 case MXC4005_REG_CONTROL:
123 return true;
124 default:
125 return false;
126 }
127 }
128
129 static const struct regmap_config mxc4005_regmap_config = {
130 .name = MXC4005_REGMAP_NAME,
131
132 .reg_bits = 8,
133 .val_bits = 8,
134
135 .max_register = MXC4005_REG_DEVICE_ID,
136
137 .readable_reg = mxc4005_is_readable_reg,
138 .writeable_reg = mxc4005_is_writeable_reg,
139 };
140
141 static int mxc4005_read_xyz(struct mxc4005_data *data)
142 {
143 int ret;
144
145 ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER,
146 (u8 *) data->buffer, sizeof(data->buffer));
147 if (ret < 0) {
148 dev_err(data->dev, "failed to read axes\n");
149 return ret;
150 }
151
152 return 0;
153 }
154
155 static int mxc4005_read_axis(struct mxc4005_data *data,
156 unsigned int addr)
157 {
158 __be16 reg;
159 int ret;
160
161 ret = regmap_bulk_read(data->regmap, addr, (u8 *) &reg, sizeof(reg));
162 if (ret < 0) {
163 dev_err(data->dev, "failed to read reg %02x\n", addr);
164 return ret;
165 }
166
167 return be16_to_cpu(reg);
168 }
169
170 static int mxc4005_read_scale(struct mxc4005_data *data)
171 {
172 unsigned int reg;
173 int ret;
174 int i;
175
176 ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, &reg);
177 if (ret < 0) {
178 dev_err(data->dev, "failed to read reg_control\n");
179 return ret;
180 }
181
182 i = reg >> MXC4005_CONTROL_FSR_SHIFT;
183
184 if (i < 0 || i >= ARRAY_SIZE(mxc4005_scale_table))
185 return -EINVAL;
186
187 return mxc4005_scale_table[i].scale;
188 }
189
190 static int mxc4005_set_scale(struct mxc4005_data *data, int val)
191 {
192 unsigned int reg;
193 int i;
194 int ret;
195
196 for (i = 0; i < ARRAY_SIZE(mxc4005_scale_table); i++) {
197 if (mxc4005_scale_table[i].scale == val) {
198 reg = i << MXC4005_CONTROL_FSR_SHIFT;
199 ret = regmap_update_bits(data->regmap,
200 MXC4005_REG_CONTROL,
201 MXC4005_REG_CONTROL_MASK_FSR,
202 reg);
203 if (ret < 0)
204 dev_err(data->dev,
205 "failed to write reg_control\n");
206 return ret;
207 }
208 }
209
210 return -EINVAL;
211 }
212
213 static int mxc4005_read_raw(struct iio_dev *indio_dev,
214 struct iio_chan_spec const *chan,
215 int *val, int *val2, long mask)
216 {
217 struct mxc4005_data *data = iio_priv(indio_dev);
218 int ret;
219
220 switch (mask) {
221 case IIO_CHAN_INFO_RAW:
222 switch (chan->type) {
223 case IIO_ACCEL:
224 if (iio_buffer_enabled(indio_dev))
225 return -EBUSY;
226
227 ret = mxc4005_read_axis(data, chan->address);
228 if (ret < 0)
229 return ret;
230 *val = sign_extend32(ret >> chan->scan_type.shift,
231 chan->scan_type.realbits - 1);
232 return IIO_VAL_INT;
233 default:
234 return -EINVAL;
235 }
236 case IIO_CHAN_INFO_SCALE:
237 ret = mxc4005_read_scale(data);
238 if (ret < 0)
239 return ret;
240
241 *val = 0;
242 *val2 = ret;
243 return IIO_VAL_INT_PLUS_MICRO;
244 default:
245 return -EINVAL;
246 }
247 }
248
249 static int mxc4005_write_raw(struct iio_dev *indio_dev,
250 struct iio_chan_spec const *chan,
251 int val, int val2, long mask)
252 {
253 struct mxc4005_data *data = iio_priv(indio_dev);
254
255 switch (mask) {
256 case IIO_CHAN_INFO_SCALE:
257 if (val != 0)
258 return -EINVAL;
259
260 return mxc4005_set_scale(data, val2);
261 default:
262 return -EINVAL;
263 }
264 }
265
266 static const struct iio_info mxc4005_info = {
267 .read_raw = mxc4005_read_raw,
268 .write_raw = mxc4005_write_raw,
269 .attrs = &mxc4005_attrs_group,
270 };
271
272 static const unsigned long mxc4005_scan_masks[] = {
273 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
274 0
275 };
276
277 #define MXC4005_CHANNEL(_axis, _addr) { \
278 .type = IIO_ACCEL, \
279 .modified = 1, \
280 .channel2 = IIO_MOD_##_axis, \
281 .address = _addr, \
282 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
283 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
284 .scan_index = AXIS_##_axis, \
285 .scan_type = { \
286 .sign = 's', \
287 .realbits = 12, \
288 .storagebits = 16, \
289 .shift = 4, \
290 .endianness = IIO_BE, \
291 }, \
292 }
293
294 static const struct iio_chan_spec mxc4005_channels[] = {
295 MXC4005_CHANNEL(X, MXC4005_REG_XOUT_UPPER),
296 MXC4005_CHANNEL(Y, MXC4005_REG_YOUT_UPPER),
297 MXC4005_CHANNEL(Z, MXC4005_REG_ZOUT_UPPER),
298 IIO_CHAN_SOFT_TIMESTAMP(3),
299 };
300
301 static irqreturn_t mxc4005_trigger_handler(int irq, void *private)
302 {
303 struct iio_poll_func *pf = private;
304 struct iio_dev *indio_dev = pf->indio_dev;
305 struct mxc4005_data *data = iio_priv(indio_dev);
306 int ret;
307
308 ret = mxc4005_read_xyz(data);
309 if (ret < 0)
310 goto err;
311
312 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
313 pf->timestamp);
314
315 err:
316 iio_trigger_notify_done(indio_dev->trig);
317
318 return IRQ_HANDLED;
319 }
320
321 static int mxc4005_clr_intr(struct mxc4005_data *data)
322 {
323 int ret;
324
325 /* clear interrupt */
326 ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1,
327 MXC4005_REG_INT_CLR1_BIT_DRDYC);
328 if (ret < 0) {
329 dev_err(data->dev, "failed to write to reg_int_clr1\n");
330 return ret;
331 }
332
333 return 0;
334 }
335
336 static int mxc4005_set_trigger_state(struct iio_trigger *trig,
337 bool state)
338 {
339 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
340 struct mxc4005_data *data = iio_priv(indio_dev);
341 int ret;
342
343 mutex_lock(&data->mutex);
344 if (state) {
345 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
346 MXC4005_REG_INT_MASK1_BIT_DRDYE);
347 } else {
348 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
349 ~MXC4005_REG_INT_MASK1_BIT_DRDYE);
350 }
351
352 if (ret < 0) {
353 mutex_unlock(&data->mutex);
354 dev_err(data->dev, "failed to update reg_int_mask1");
355 return ret;
356 }
357
358 data->trigger_enabled = state;
359 mutex_unlock(&data->mutex);
360
361 return 0;
362 }
363
364 static int mxc4005_trigger_try_reen(struct iio_trigger *trig)
365 {
366 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
367 struct mxc4005_data *data = iio_priv(indio_dev);
368
369 if (!data->dready_trig)
370 return 0;
371
372 return mxc4005_clr_intr(data);
373 }
374
375 static const struct iio_trigger_ops mxc4005_trigger_ops = {
376 .set_trigger_state = mxc4005_set_trigger_state,
377 .try_reenable = mxc4005_trigger_try_reen,
378 };
379
380 static int mxc4005_chip_init(struct mxc4005_data *data)
381 {
382 int ret;
383 unsigned int reg;
384
385 ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, &reg);
386 if (ret < 0) {
387 dev_err(data->dev, "failed to read chip id\n");
388 return ret;
389 }
390
391 dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg);
392
393 return 0;
394 }
395
396 static int mxc4005_probe(struct i2c_client *client,
397 const struct i2c_device_id *id)
398 {
399 struct mxc4005_data *data;
400 struct iio_dev *indio_dev;
401 struct regmap *regmap;
402 int ret;
403
404 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
405 if (!indio_dev)
406 return -ENOMEM;
407
408 regmap = devm_regmap_init_i2c(client, &mxc4005_regmap_config);
409 if (IS_ERR(regmap)) {
410 dev_err(&client->dev, "failed to initialize regmap\n");
411 return PTR_ERR(regmap);
412 }
413
414 data = iio_priv(indio_dev);
415 i2c_set_clientdata(client, indio_dev);
416 data->dev = &client->dev;
417 data->regmap = regmap;
418
419 ret = mxc4005_chip_init(data);
420 if (ret < 0) {
421 dev_err(&client->dev, "failed to initialize chip\n");
422 return ret;
423 }
424
425 mutex_init(&data->mutex);
426
427 indio_dev->dev.parent = &client->dev;
428 indio_dev->channels = mxc4005_channels;
429 indio_dev->num_channels = ARRAY_SIZE(mxc4005_channels);
430 indio_dev->available_scan_masks = mxc4005_scan_masks;
431 indio_dev->name = MXC4005_DRV_NAME;
432 indio_dev->modes = INDIO_DIRECT_MODE;
433 indio_dev->info = &mxc4005_info;
434
435 ret = iio_triggered_buffer_setup(indio_dev,
436 iio_pollfunc_store_time,
437 mxc4005_trigger_handler,
438 NULL);
439 if (ret < 0) {
440 dev_err(&client->dev,
441 "failed to setup iio triggered buffer\n");
442 return ret;
443 }
444
445 if (client->irq > 0) {
446 data->dready_trig = devm_iio_trigger_alloc(&client->dev,
447 "%s-dev%d",
448 indio_dev->name,
449 indio_dev->id);
450 if (!data->dready_trig)
451 return -ENOMEM;
452
453 ret = devm_request_threaded_irq(&client->dev, client->irq,
454 iio_trigger_generic_data_rdy_poll,
455 NULL,
456 IRQF_TRIGGER_FALLING |
457 IRQF_ONESHOT,
458 MXC4005_IRQ_NAME,
459 data->dready_trig);
460 if (ret) {
461 dev_err(&client->dev,
462 "failed to init threaded irq\n");
463 goto err_buffer_cleanup;
464 }
465
466 data->dready_trig->dev.parent = &client->dev;
467 data->dready_trig->ops = &mxc4005_trigger_ops;
468 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
469 indio_dev->trig = data->dready_trig;
470 iio_trigger_get(indio_dev->trig);
471 ret = iio_trigger_register(data->dready_trig);
472 if (ret) {
473 dev_err(&client->dev,
474 "failed to register trigger\n");
475 goto err_trigger_unregister;
476 }
477 }
478
479 ret = iio_device_register(indio_dev);
480 if (ret < 0) {
481 dev_err(&client->dev,
482 "unable to register iio device %d\n", ret);
483 goto err_buffer_cleanup;
484 }
485
486 return 0;
487
488 err_trigger_unregister:
489 iio_trigger_unregister(data->dready_trig);
490 err_buffer_cleanup:
491 iio_triggered_buffer_cleanup(indio_dev);
492
493 return ret;
494 }
495
496 static int mxc4005_remove(struct i2c_client *client)
497 {
498 struct iio_dev *indio_dev = i2c_get_clientdata(client);
499 struct mxc4005_data *data = iio_priv(indio_dev);
500
501 iio_device_unregister(indio_dev);
502
503 iio_triggered_buffer_cleanup(indio_dev);
504 if (data->dready_trig)
505 iio_trigger_unregister(data->dready_trig);
506
507 return 0;
508 }
509
510 static const struct acpi_device_id mxc4005_acpi_match[] = {
511 {"MXC4005", 0},
512 { },
513 };
514 MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match);
515
516 static const struct i2c_device_id mxc4005_id[] = {
517 {"mxc4005", 0},
518 { },
519 };
520 MODULE_DEVICE_TABLE(i2c, mxc4005_id);
521
522 static struct i2c_driver mxc4005_driver = {
523 .driver = {
524 .name = MXC4005_DRV_NAME,
525 .acpi_match_table = ACPI_PTR(mxc4005_acpi_match),
526 },
527 .probe = mxc4005_probe,
528 .remove = mxc4005_remove,
529 .id_table = mxc4005_id,
530 };
531
532 module_i2c_driver(mxc4005_driver);
533
534 MODULE_AUTHOR("Teodora Baluta <teodora.baluta@intel.com>");
535 MODULE_LICENSE("GPL v2");
536 MODULE_DESCRIPTION("MXC4005 3-axis accelerometer driver");
Linux with added FPC-III support