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Linux 4.16.11
[linux/fpc-iii.git] / drivers / iio / health / max30102.c
blob15ccadc74891f73dca409acb0806cb4136646da9
1 /*
2 * max30102.c - Support for MAX30102 heart rate and pulse oximeter sensor
3 *
4 * Copyright (C) 2017 Matt Ranostay <matt@ranostay.consulting>
5 *
6 * Support for MAX30105 optical particle sensor
7 * Copyright (C) 2017 Peter Meerwald-Stadler <pmeerw@pmeerw.net>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * 7-bit I2C chip address: 0x57
20 * TODO: proximity power saving feature
21 */
22
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/irq.h>
29 #include <linux/i2c.h>
30 #include <linux/mutex.h>
31 #include <linux/of.h>
32 #include <linux/regmap.h>
33 #include <linux/iio/iio.h>
34 #include <linux/iio/buffer.h>
35 #include <linux/iio/kfifo_buf.h>
36
37 #define MAX30102_REGMAP_NAME "max30102_regmap"
38 #define MAX30102_DRV_NAME "max30102"
39 #define MAX30102_PART_NUMBER 0x15
40
41 enum max30102_chip_id {
42 max30102,
43 max30105,
44 };
45
46 enum max3012_led_idx {
47 MAX30102_LED_RED,
48 MAX30102_LED_IR,
49 MAX30105_LED_GREEN,
50 };
51
52 #define MAX30102_REG_INT_STATUS 0x00
53 #define MAX30102_REG_INT_STATUS_PWR_RDY BIT(0)
54 #define MAX30102_REG_INT_STATUS_PROX_INT BIT(4)
55 #define MAX30102_REG_INT_STATUS_ALC_OVF BIT(5)
56 #define MAX30102_REG_INT_STATUS_PPG_RDY BIT(6)
57 #define MAX30102_REG_INT_STATUS_FIFO_RDY BIT(7)
58
59 #define MAX30102_REG_INT_ENABLE 0x02
60 #define MAX30102_REG_INT_ENABLE_PROX_INT_EN BIT(4)
61 #define MAX30102_REG_INT_ENABLE_ALC_OVF_EN BIT(5)
62 #define MAX30102_REG_INT_ENABLE_PPG_EN BIT(6)
63 #define MAX30102_REG_INT_ENABLE_FIFO_EN BIT(7)
64 #define MAX30102_REG_INT_ENABLE_MASK 0xf0
65 #define MAX30102_REG_INT_ENABLE_MASK_SHIFT 4
66
67 #define MAX30102_REG_FIFO_WR_PTR 0x04
68 #define MAX30102_REG_FIFO_OVR_CTR 0x05
69 #define MAX30102_REG_FIFO_RD_PTR 0x06
70 #define MAX30102_REG_FIFO_DATA 0x07
71 #define MAX30102_REG_FIFO_DATA_BYTES 3
72
73 #define MAX30102_REG_FIFO_CONFIG 0x08
74 #define MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES BIT(1)
75 #define MAX30102_REG_FIFO_CONFIG_AVG_SHIFT 5
76 #define MAX30102_REG_FIFO_CONFIG_AFULL BIT(0)
77
78 #define MAX30102_REG_MODE_CONFIG 0x09
79 #define MAX30102_REG_MODE_CONFIG_MODE_NONE 0x00
80 #define MAX30102_REG_MODE_CONFIG_MODE_HR 0x02 /* red LED */
81 #define MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2 0x03 /* red + IR LED */
82 #define MAX30102_REG_MODE_CONFIG_MODE_MULTI 0x07 /* multi-LED mode */
83 #define MAX30102_REG_MODE_CONFIG_MODE_MASK GENMASK(2, 0)
84 #define MAX30102_REG_MODE_CONFIG_PWR BIT(7)
85
86 #define MAX30102_REG_MODE_CONTROL_SLOT21 0x11 /* multi-LED control */
87 #define MAX30102_REG_MODE_CONTROL_SLOT43 0x12
88 #define MAX30102_REG_MODE_CONTROL_SLOT_MASK (GENMASK(6, 4) | GENMASK(2, 0))
89 #define MAX30102_REG_MODE_CONTROL_SLOT_SHIFT 4
90
91 #define MAX30102_REG_SPO2_CONFIG 0x0a
92 #define MAX30102_REG_SPO2_CONFIG_PULSE_411_US 0x03
93 #define MAX30102_REG_SPO2_CONFIG_SR_400HZ 0x03
94 #define MAX30102_REG_SPO2_CONFIG_SR_MASK 0x07
95 #define MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT 2
96 #define MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS BIT(0)
97 #define MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT 5
98
99 #define MAX30102_REG_RED_LED_CONFIG 0x0c
100 #define MAX30102_REG_IR_LED_CONFIG 0x0d
101 #define MAX30105_REG_GREEN_LED_CONFIG 0x0e
102
103 #define MAX30102_REG_TEMP_CONFIG 0x21
104 #define MAX30102_REG_TEMP_CONFIG_TEMP_EN BIT(0)
105
106 #define MAX30102_REG_TEMP_INTEGER 0x1f
107 #define MAX30102_REG_TEMP_FRACTION 0x20
108
109 #define MAX30102_REG_REV_ID 0xfe
110 #define MAX30102_REG_PART_ID 0xff
111
112 struct max30102_data {
113 struct i2c_client *client;
114 struct iio_dev *indio_dev;
115 struct mutex lock;
116 struct regmap *regmap;
117 enum max30102_chip_id chip_id;
118
119 u8 buffer[12];
120 __be32 processed_buffer[3]; /* 3 x 18-bit (padded to 32-bits) */
121 };
122
123 static const struct regmap_config max30102_regmap_config = {
124 .name = MAX30102_REGMAP_NAME,
125
126 .reg_bits = 8,
127 .val_bits = 8,
128 };
129
130 static const unsigned long max30102_scan_masks[] = {
131 BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
132 0
133 };
134
135 static const unsigned long max30105_scan_masks[] = {
136 BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
137 BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
138 BIT(MAX30105_LED_GREEN),
139 0
140 };
141
142 #define MAX30102_INTENSITY_CHANNEL(_si, _mod) { \
143 .type = IIO_INTENSITY, \
144 .channel2 = _mod, \
145 .modified = 1, \
146 .scan_index = _si, \
147 .scan_type = { \
148 .sign = 'u', \
149 .shift = 8, \
150 .realbits = 18, \
151 .storagebits = 32, \
152 .endianness = IIO_BE, \
153 }, \
154 }
155
156 static const struct iio_chan_spec max30102_channels[] = {
157 MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
158 MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
159 {
160 .type = IIO_TEMP,
161 .info_mask_separate =
162 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
163 .scan_index = -1,
164 },
165 };
166
167 static const struct iio_chan_spec max30105_channels[] = {
168 MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
169 MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
170 MAX30102_INTENSITY_CHANNEL(MAX30105_LED_GREEN, IIO_MOD_LIGHT_GREEN),
171 {
172 .type = IIO_TEMP,
173 .info_mask_separate =
174 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
175 .scan_index = -1,
176 },
177 };
178
179 static int max30102_set_power(struct max30102_data *data, bool en)
180 {
181 return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
182 MAX30102_REG_MODE_CONFIG_PWR,
183 en ? 0 : MAX30102_REG_MODE_CONFIG_PWR);
184 }
185
186 static int max30102_set_powermode(struct max30102_data *data, u8 mode, bool en)
187 {
188 u8 reg = mode;
189
190 if (!en)
191 reg |= MAX30102_REG_MODE_CONFIG_PWR;
192
193 return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
194 MAX30102_REG_MODE_CONFIG_PWR |
195 MAX30102_REG_MODE_CONFIG_MODE_MASK, reg);
196 }
197
198 #define MAX30102_MODE_CONTROL_LED_SLOTS(slot2, slot1) \
199 ((slot2 << MAX30102_REG_MODE_CONTROL_SLOT_SHIFT) | slot1)
200
201 static int max30102_buffer_postenable(struct iio_dev *indio_dev)
202 {
203 struct max30102_data *data = iio_priv(indio_dev);
204 int ret;
205 u8 reg;
206
207 switch (*indio_dev->active_scan_mask) {
208 case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR):
209 reg = MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2;
210 break;
211 case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
212 BIT(MAX30105_LED_GREEN):
213 ret = regmap_update_bits(data->regmap,
214 MAX30102_REG_MODE_CONTROL_SLOT21,
215 MAX30102_REG_MODE_CONTROL_SLOT_MASK,
216 MAX30102_MODE_CONTROL_LED_SLOTS(2, 1));
217 if (ret)
218 return ret;
219
220 ret = regmap_update_bits(data->regmap,
221 MAX30102_REG_MODE_CONTROL_SLOT43,
222 MAX30102_REG_MODE_CONTROL_SLOT_MASK,
223 MAX30102_MODE_CONTROL_LED_SLOTS(0, 3));
224 if (ret)
225 return ret;
226
227 reg = MAX30102_REG_MODE_CONFIG_MODE_MULTI;
228 break;
229 default:
230 return -EINVAL;
231 }
232
233 return max30102_set_powermode(data, reg, true);
234 }
235
236 static int max30102_buffer_predisable(struct iio_dev *indio_dev)
237 {
238 struct max30102_data *data = iio_priv(indio_dev);
239
240 return max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
241 false);
242 }
243
244 static const struct iio_buffer_setup_ops max30102_buffer_setup_ops = {
245 .postenable = max30102_buffer_postenable,
246 .predisable = max30102_buffer_predisable,
247 };
248
249 static inline int max30102_fifo_count(struct max30102_data *data)
250 {
251 unsigned int val;
252 int ret;
253
254 ret = regmap_read(data->regmap, MAX30102_REG_INT_STATUS, &val);
255 if (ret)
256 return ret;
257
258 /* FIFO has one sample slot left */
259 if (val & MAX30102_REG_INT_STATUS_FIFO_RDY)
260 return 1;
261
262 return 0;
263 }
264
265 #define MAX30102_COPY_DATA(i) \
266 memcpy(&data->processed_buffer[(i)], \
267 &buffer[(i) * MAX30102_REG_FIFO_DATA_BYTES], \
268 MAX30102_REG_FIFO_DATA_BYTES)
269
270 static int max30102_read_measurement(struct max30102_data *data,
271 unsigned int measurements)
272 {
273 int ret;
274 u8 *buffer = (u8 *) &data->buffer;
275
276 ret = i2c_smbus_read_i2c_block_data(data->client,
277 MAX30102_REG_FIFO_DATA,
278 measurements *
279 MAX30102_REG_FIFO_DATA_BYTES,
280 buffer);
281
282 switch (measurements) {
283 case 3:
284 MAX30102_COPY_DATA(2);
285 case 2: /* fall-through */
286 MAX30102_COPY_DATA(1);
287 case 1: /* fall-through */
288 MAX30102_COPY_DATA(0);
289 break;
290 default:
291 return -EINVAL;
292 }
293
294 return (ret == measurements * MAX30102_REG_FIFO_DATA_BYTES) ?
295 0 : -EINVAL;
296 }
297
298 static irqreturn_t max30102_interrupt_handler(int irq, void *private)
299 {
300 struct iio_dev *indio_dev = private;
301 struct max30102_data *data = iio_priv(indio_dev);
302 unsigned int measurements = bitmap_weight(indio_dev->active_scan_mask,
303 indio_dev->masklength);
304 int ret, cnt = 0;
305
306 mutex_lock(&data->lock);
307
308 while (cnt || (cnt = max30102_fifo_count(data)) > 0) {
309 ret = max30102_read_measurement(data, measurements);
310 if (ret)
311 break;
312
313 iio_push_to_buffers(data->indio_dev, data->processed_buffer);
314 cnt--;
315 }
316
317 mutex_unlock(&data->lock);
318
319 return IRQ_HANDLED;
320 }
321
322 static int max30102_get_current_idx(unsigned int val, int *reg)
323 {
324 /* each step is 0.200 mA */
325 *reg = val / 200;
326
327 return *reg > 0xff ? -EINVAL : 0;
328 }
329
330 static int max30102_led_init(struct max30102_data *data)
331 {
332 struct device *dev = &data->client->dev;
333 struct device_node *np = dev->of_node;
334 unsigned int val;
335 int reg, ret;
336
337 ret = of_property_read_u32(np, "maxim,red-led-current-microamp", &val);
338 if (ret) {
339 dev_info(dev, "no red-led-current-microamp set\n");
340
341 /* Default to 7 mA RED LED */
342 val = 7000;
343 }
344
345 ret = max30102_get_current_idx(val, &reg);
346 if (ret) {
347 dev_err(dev, "invalid RED LED current setting %d\n", val);
348 return ret;
349 }
350
351 ret = regmap_write(data->regmap, MAX30102_REG_RED_LED_CONFIG, reg);
352 if (ret)
353 return ret;
354
355 if (data->chip_id == max30105) {
356 ret = of_property_read_u32(np,
357 "maxim,green-led-current-microamp", &val);
358 if (ret) {
359 dev_info(dev, "no green-led-current-microamp set\n");
360
361 /* Default to 7 mA green LED */
362 val = 7000;
363 }
364
365 ret = max30102_get_current_idx(val, &reg);
366 if (ret) {
367 dev_err(dev, "invalid green LED current setting %d\n",
368 val);
369 return ret;
370 }
371
372 ret = regmap_write(data->regmap, MAX30105_REG_GREEN_LED_CONFIG,
373 reg);
374 if (ret)
375 return ret;
376 }
377
378 ret = of_property_read_u32(np, "maxim,ir-led-current-microamp", &val);
379 if (ret) {
380 dev_info(dev, "no ir-led-current-microamp set\n");
381
382 /* Default to 7 mA IR LED */
383 val = 7000;
384 }
385
386 ret = max30102_get_current_idx(val, &reg);
387 if (ret) {
388 dev_err(dev, "invalid IR LED current setting %d\n", val);
389 return ret;
390 }
391
392 return regmap_write(data->regmap, MAX30102_REG_IR_LED_CONFIG, reg);
393 }
394
395 static int max30102_chip_init(struct max30102_data *data)
396 {
397 int ret;
398
399 /* setup LED current settings */
400 ret = max30102_led_init(data);
401 if (ret)
402 return ret;
403
404 /* configure 18-bit HR + SpO2 readings at 400Hz */
405 ret = regmap_write(data->regmap, MAX30102_REG_SPO2_CONFIG,
406 (MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS
407 << MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT) |
408 (MAX30102_REG_SPO2_CONFIG_SR_400HZ
409 << MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT) |
410 MAX30102_REG_SPO2_CONFIG_PULSE_411_US);
411 if (ret)
412 return ret;
413
414 /* average 4 samples + generate FIFO interrupt */
415 ret = regmap_write(data->regmap, MAX30102_REG_FIFO_CONFIG,
416 (MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES
417 << MAX30102_REG_FIFO_CONFIG_AVG_SHIFT) |
418 MAX30102_REG_FIFO_CONFIG_AFULL);
419 if (ret)
420 return ret;
421
422 /* enable FIFO interrupt */
423 return regmap_update_bits(data->regmap, MAX30102_REG_INT_ENABLE,
424 MAX30102_REG_INT_ENABLE_MASK,
425 MAX30102_REG_INT_ENABLE_FIFO_EN);
426 }
427
428 static int max30102_read_temp(struct max30102_data *data, int *val)
429 {
430 int ret;
431 unsigned int reg;
432
433 ret = regmap_read(data->regmap, MAX30102_REG_TEMP_INTEGER, &reg);
434 if (ret < 0)
435 return ret;
436 *val = reg << 4;
437
438 ret = regmap_read(data->regmap, MAX30102_REG_TEMP_FRACTION, &reg);
439 if (ret < 0)
440 return ret;
441
442 *val |= reg & 0xf;
443 *val = sign_extend32(*val, 11);
444
445 return 0;
446 }
447
448 static int max30102_get_temp(struct max30102_data *data, int *val, bool en)
449 {
450 int ret;
451
452 if (en) {
453 ret = max30102_set_power(data, true);
454 if (ret)
455 return ret;
456 }
457
458 /* start acquisition */
459 ret = regmap_update_bits(data->regmap, MAX30102_REG_TEMP_CONFIG,
460 MAX30102_REG_TEMP_CONFIG_TEMP_EN,
461 MAX30102_REG_TEMP_CONFIG_TEMP_EN);
462 if (ret)
463 goto out;
464
465 msleep(35);
466 ret = max30102_read_temp(data, val);
467
468 out:
469 if (en)
470 max30102_set_power(data, false);
471
472 return ret;
473 }
474
475 static int max30102_read_raw(struct iio_dev *indio_dev,
476 struct iio_chan_spec const *chan,
477 int *val, int *val2, long mask)
478 {
479 struct max30102_data *data = iio_priv(indio_dev);
480 int ret = -EINVAL;
481
482 switch (mask) {
483 case IIO_CHAN_INFO_RAW:
484 /*
485 * Temperature reading can only be acquired when not in
486 * shutdown; leave shutdown briefly when buffer not running
487 */
488 mutex_lock(&indio_dev->mlock);
489 if (!iio_buffer_enabled(indio_dev))
490 ret = max30102_get_temp(data, val, true);
491 else
492 ret = max30102_get_temp(data, val, false);
493 mutex_unlock(&indio_dev->mlock);
494 if (ret)
495 return ret;
496
497 ret = IIO_VAL_INT;
498 break;
499 case IIO_CHAN_INFO_SCALE:
500 *val = 1000; /* 62.5 */
501 *val2 = 16;
502 ret = IIO_VAL_FRACTIONAL;
503 break;
504 }
505
506 return ret;
507 }
508
509 static const struct iio_info max30102_info = {
510 .read_raw = max30102_read_raw,
511 };
512
513 static int max30102_probe(struct i2c_client *client,
514 const struct i2c_device_id *id)
515 {
516 struct max30102_data *data;
517 struct iio_buffer *buffer;
518 struct iio_dev *indio_dev;
519 int ret;
520 unsigned int reg;
521
522 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
523 if (!indio_dev)
524 return -ENOMEM;
525
526 buffer = devm_iio_kfifo_allocate(&client->dev);
527 if (!buffer)
528 return -ENOMEM;
529
530 iio_device_attach_buffer(indio_dev, buffer);
531
532 indio_dev->name = MAX30102_DRV_NAME;
533 indio_dev->info = &max30102_info;
534 indio_dev->modes = (INDIO_BUFFER_SOFTWARE | INDIO_DIRECT_MODE);
535 indio_dev->setup_ops = &max30102_buffer_setup_ops;
536 indio_dev->dev.parent = &client->dev;
537
538 data = iio_priv(indio_dev);
539 data->indio_dev = indio_dev;
540 data->client = client;
541 data->chip_id = id->driver_data;
542
543 mutex_init(&data->lock);
544 i2c_set_clientdata(client, indio_dev);
545
546 switch (data->chip_id) {
547 case max30105:
548 indio_dev->channels = max30105_channels;
549 indio_dev->num_channels = ARRAY_SIZE(max30105_channels);
550 indio_dev->available_scan_masks = max30105_scan_masks;
551 break;
552 case max30102:
553 indio_dev->channels = max30102_channels;
554 indio_dev->num_channels = ARRAY_SIZE(max30102_channels);
555 indio_dev->available_scan_masks = max30102_scan_masks;
556 break;
557 default:
558 return -ENODEV;
559 }
560
561 data->regmap = devm_regmap_init_i2c(client, &max30102_regmap_config);
562 if (IS_ERR(data->regmap)) {
563 dev_err(&client->dev, "regmap initialization failed\n");
564 return PTR_ERR(data->regmap);
565 }
566
567 /* check part ID */
568 ret = regmap_read(data->regmap, MAX30102_REG_PART_ID, &reg);
569 if (ret)
570 return ret;
571 if (reg != MAX30102_PART_NUMBER)
572 return -ENODEV;
573
574 /* show revision ID */
575 ret = regmap_read(data->regmap, MAX30102_REG_REV_ID, &reg);
576 if (ret)
577 return ret;
578 dev_dbg(&client->dev, "max3010x revision %02x\n", reg);
579
580 /* clear mode setting, chip shutdown */
581 ret = max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
582 false);
583 if (ret)
584 return ret;
585
586 ret = max30102_chip_init(data);
587 if (ret)
588 return ret;
589
590 if (client->irq <= 0) {
591 dev_err(&client->dev, "no valid irq defined\n");
592 return -EINVAL;
593 }
594
595 ret = devm_request_threaded_irq(&client->dev, client->irq,
596 NULL, max30102_interrupt_handler,
597 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
598 "max30102_irq", indio_dev);
599 if (ret) {
600 dev_err(&client->dev, "request irq (%d) failed\n", client->irq);
601 return ret;
602 }
603
604 return iio_device_register(indio_dev);
605 }
606
607 static int max30102_remove(struct i2c_client *client)
608 {
609 struct iio_dev *indio_dev = i2c_get_clientdata(client);
610 struct max30102_data *data = iio_priv(indio_dev);
611
612 iio_device_unregister(indio_dev);
613 max30102_set_power(data, false);
614
615 return 0;
616 }
617
618 static const struct i2c_device_id max30102_id[] = {
619 { "max30102", max30102 },
620 { "max30105", max30105 },
621 {}
622 };
623 MODULE_DEVICE_TABLE(i2c, max30102_id);
624
625 static const struct of_device_id max30102_dt_ids[] = {
626 { .compatible = "maxim,max30102" },
627 { .compatible = "maxim,max30105" },
628 { }
629 };
630 MODULE_DEVICE_TABLE(of, max30102_dt_ids);
631
632 static struct i2c_driver max30102_driver = {
633 .driver = {
634 .name = MAX30102_DRV_NAME,
635 .of_match_table = of_match_ptr(max30102_dt_ids),
636 },
637 .probe = max30102_probe,
638 .remove = max30102_remove,
639 .id_table = max30102_id,
640 };
641 module_i2c_driver(max30102_driver);
642
643 MODULE_AUTHOR("Matt Ranostay <matt@ranostay.consulting>");
644 MODULE_DESCRIPTION("MAX30102 heart rate/pulse oximeter and MAX30105 particle sensor driver");
645 MODULE_LICENSE("GPL");
Linux with added FPC-III support