drivers/media/dvb-frontends/drxd_firm.h

   1 /*
   2  * drxd_firm.h
   3  *
   4  * Copyright (C) 2006-2007 Micronas
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 only, as published by the Free Software Foundation.
   9  *
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * To obtain the license, point your browser to
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #ifndef _DRXD_FIRM_H_
  21 #define _DRXD_FIRM_H_
  22
  23 #include <linux/types.h>
  24 #include "drxd_map_firm.h"
  25
  26 #define VERSION_MAJOR 1
  27 #define VERSION_MINOR 4
  28 #define VERSION_PATCH 23
  29
  30 #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
  31
  32 #define DRXD_MAX_RETRIES (1000)
  33 #define HI_I2C_DELAY     84
  34 #define HI_I2C_BRIDGE_DELAY   750
  35
  36 #define EQ_TD_TPS_PWR_UNKNOWN          0x00C0   /* Unknown configurations */
  37 #define EQ_TD_TPS_PWR_QPSK             0x016a
  38 #define EQ_TD_TPS_PWR_QAM16_ALPHAN     0x0195
  39 #define EQ_TD_TPS_PWR_QAM16_ALPHA1     0x0195
  40 #define EQ_TD_TPS_PWR_QAM16_ALPHA2     0x011E
  41 #define EQ_TD_TPS_PWR_QAM16_ALPHA4     0x01CE
  42 #define EQ_TD_TPS_PWR_QAM64_ALPHAN     0x019F
  43 #define EQ_TD_TPS_PWR_QAM64_ALPHA1     0x019F
  44 #define EQ_TD_TPS_PWR_QAM64_ALPHA2     0x00F8
  45 #define EQ_TD_TPS_PWR_QAM64_ALPHA4     0x014D
  46
  47 #define DRXD_DEF_AG_PWD_CONSUMER 0x000E
  48 #define DRXD_DEF_AG_PWD_PRO 0x0000
  49 #define DRXD_DEF_AG_AGC_SIO 0x0000
  50
  51 #define DRXD_FE_CTRL_MAX 1023
  52
  53 #define DRXD_OSCDEV_DO_SCAN  (16)
  54
  55 #define DRXD_OSCDEV_DONT_SCAN  (0)
  56
  57 #define DRXD_OSCDEV_STEP  (275)
  58
  59 #define DRXD_SCAN_TIMEOUT    (650)
  60
  61 #define DRXD_BANDWIDTH_8MHZ_IN_HZ  (0x8B8249L)
  62 #define DRXD_BANDWIDTH_7MHZ_IN_HZ  (0x7A1200L)
  63 #define DRXD_BANDWIDTH_6MHZ_IN_HZ  (0x68A1B6L)
  64
  65 #define IRLEN_COARSE_8K       (10)
  66 #define IRLEN_FINE_8K         (10)
  67 #define IRLEN_COARSE_2K       (7)
  68 #define IRLEN_FINE_2K         (9)
  69 #define DIFF_INVALID          (511)
  70 #define DIFF_TARGET           (4)
  71 #define DIFF_MARGIN           (1)
  72
  73 extern u8 DRXD_InitAtomicRead[];
  74 extern u8 DRXD_HiI2cPatch_1[];
  75 extern u8 DRXD_HiI2cPatch_3[];
  76
  77 extern u8 DRXD_InitSC[];
  78
  79 extern u8 DRXD_ResetCEFR[];
  80 extern u8 DRXD_InitFEA2_1[];
  81 extern u8 DRXD_InitFEA2_2[];
  82 extern u8 DRXD_InitCPA2[];
  83 extern u8 DRXD_InitCEA2[];
  84 extern u8 DRXD_InitEQA2[];
  85 extern u8 DRXD_InitECA2[];
  86 extern u8 DRXD_ResetECA2[];
  87 extern u8 DRXD_ResetECRAM[];
  88
  89 extern u8 DRXD_A2_microcode[];
  90 extern u32 DRXD_A2_microcode_length;
  91
  92 extern u8 DRXD_InitFEB1_1[];
  93 extern u8 DRXD_InitFEB1_2[];
  94 extern u8 DRXD_InitCPB1[];
  95 extern u8 DRXD_InitCEB1[];
  96 extern u8 DRXD_InitEQB1[];
  97 extern u8 DRXD_InitECB1[];
  98
  99 extern u8 DRXD_InitDiversityFront[];
 100 extern u8 DRXD_InitDiversityEnd[];
 101 extern u8 DRXD_DisableDiversity[];
 102 extern u8 DRXD_StartDiversityFront[];
 103 extern u8 DRXD_StartDiversityEnd[];
 104
 105 extern u8 DRXD_DiversityDelay8MHZ[];
 106 extern u8 DRXD_DiversityDelay6MHZ[];
 107
 108 extern u8 DRXD_B1_microcode[];
 109 extern u32 DRXD_B1_microcode_length;
 110
 111 #endif