2 * Realtek RTL2832 DVB-T demodulator driver
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
5 * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #ifndef RTL2832_PRIV_H
23 #define RTL2832_PRIV_H
25 #include <linux/regmap.h>
26 #include <linux/math64.h>
27 #include <linux/bitops.h>
29 #include <media/dvb_frontend.h>
30 #include <media/dvb_math.h>
34 struct rtl2832_platform_data
*pdata
;
35 struct i2c_client
*client
;
36 struct regmap_config regmap_config
;
37 struct regmap
*regmap
;
38 struct i2c_mux_core
*muxc
;
39 struct dvb_frontend fe
;
40 enum fe_status fe_status
;
41 u64 post_bit_error_prev
; /* for old DVBv3 read_ber() calculation */
45 struct delayed_work i2c_gate_work
;
46 unsigned long filters
; /* PID filter */
50 struct rtl2832_reg_entry
{
56 struct rtl2832_reg_value
{
61 /* Demod register bit names */
62 enum DVBT_REG_BIT_NAME
{
66 DVBT_RSD_BER_FAIL_VAL
,
127 DVBT_CFREQ_OFF_RATIO
,
162 DVBT_AGC_TARG_VAL_8_1
,
193 DVBT_MPEG_IO_OPT_2_2
,
194 DVBT_MPEG_IO_OPT_1_0
,
251 DVBT_REG_BIT_NAME_ITEM_TERMINATOR
,
254 static const struct rtl2832_reg_value rtl2832_tuner_init_fc2580
[] = {
255 {DVBT_DAGC_TRG_VAL
, 0x39},
256 {DVBT_AGC_TARG_VAL_0
, 0x0},
257 {DVBT_AGC_TARG_VAL_8_1
, 0x5a},
258 {DVBT_AAGC_LOOP_GAIN
, 0x16},
259 {DVBT_LOOP_GAIN2_3_0
, 0x6},
260 {DVBT_LOOP_GAIN2_4
, 0x1},
261 {DVBT_LOOP_GAIN3
, 0x16},
269 {DVBT_IF_AGC_MIN
, 0x80},
270 {DVBT_IF_AGC_MAX
, 0x7f},
271 {DVBT_RF_AGC_MIN
, 0x9c},
272 {DVBT_RF_AGC_MAX
, 0x7f},
273 {DVBT_POLAR_RF_AGC
, 0x0},
274 {DVBT_POLAR_IF_AGC
, 0x0},
275 {DVBT_AD7_SETTING
, 0xe9f4},
278 static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001
[] = {
279 {DVBT_DAGC_TRG_VAL
, 0x39},
280 {DVBT_AGC_TARG_VAL_0
, 0x0},
281 {DVBT_AGC_TARG_VAL_8_1
, 0x5a},
282 {DVBT_AAGC_LOOP_GAIN
, 0x16},
283 {DVBT_LOOP_GAIN2_3_0
, 0x6},
284 {DVBT_LOOP_GAIN2_4
, 0x1},
285 {DVBT_LOOP_GAIN3
, 0x16},
293 {DVBT_IF_AGC_MIN
, 0x80},
294 {DVBT_IF_AGC_MAX
, 0x7f},
295 {DVBT_RF_AGC_MIN
, 0x9c},
296 {DVBT_RF_AGC_MAX
, 0x7f},
297 {DVBT_POLAR_RF_AGC
, 0x0},
298 {DVBT_POLAR_IF_AGC
, 0x0},
299 {DVBT_AD7_SETTING
, 0xe9f4},
300 {DVBT_OPT_ADC_IQ
, 0x1},
303 {DVBT_SPEC_INV
, 0x0},
306 static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012
[] = {
307 {DVBT_DAGC_TRG_VAL
, 0x5a},
308 {DVBT_AGC_TARG_VAL_0
, 0x0},
309 {DVBT_AGC_TARG_VAL_8_1
, 0x5a},
310 {DVBT_AAGC_LOOP_GAIN
, 0x16},
311 {DVBT_LOOP_GAIN2_3_0
, 0x6},
312 {DVBT_LOOP_GAIN2_4
, 0x1},
313 {DVBT_LOOP_GAIN3
, 0x16},
321 {DVBT_IF_AGC_MIN
, 0x80},
322 {DVBT_IF_AGC_MAX
, 0x7f},
323 {DVBT_RF_AGC_MIN
, 0x80},
324 {DVBT_RF_AGC_MAX
, 0x7f},
325 {DVBT_POLAR_RF_AGC
, 0x0},
326 {DVBT_POLAR_IF_AGC
, 0x0},
327 {DVBT_AD7_SETTING
, 0xe9bf},
328 {DVBT_EN_GI_PGA
, 0x0},
329 {DVBT_THD_LOCK_UP
, 0x0},
330 {DVBT_THD_LOCK_DW
, 0x0},
331 {DVBT_THD_UP1
, 0x11},
332 {DVBT_THD_DW1
, 0xef},
333 {DVBT_INTER_CNT_LEN
, 0xc},
334 {DVBT_GI_PGA_STATE
, 0x0},
335 {DVBT_EN_AGC_PGA
, 0x1},
336 {DVBT_IF_AGC_MAN
, 0x0},
337 {DVBT_SPEC_INV
, 0x0},
340 static const struct rtl2832_reg_value rtl2832_tuner_init_e4000
[] = {
341 {DVBT_DAGC_TRG_VAL
, 0x5a},
342 {DVBT_AGC_TARG_VAL_0
, 0x0},
343 {DVBT_AGC_TARG_VAL_8_1
, 0x5a},
344 {DVBT_AAGC_LOOP_GAIN
, 0x18},
345 {DVBT_LOOP_GAIN2_3_0
, 0x8},
346 {DVBT_LOOP_GAIN2_4
, 0x1},
347 {DVBT_LOOP_GAIN3
, 0x18},
355 {DVBT_IF_AGC_MIN
, 0x80},
356 {DVBT_IF_AGC_MAX
, 0x7f},
357 {DVBT_RF_AGC_MIN
, 0x80},
358 {DVBT_RF_AGC_MAX
, 0x7f},
359 {DVBT_POLAR_RF_AGC
, 0x0},
360 {DVBT_POLAR_IF_AGC
, 0x0},
361 {DVBT_AD7_SETTING
, 0xe9d4},
362 {DVBT_EN_GI_PGA
, 0x0},
363 {DVBT_THD_LOCK_UP
, 0x0},
364 {DVBT_THD_LOCK_DW
, 0x0},
365 {DVBT_THD_UP1
, 0x14},
366 {DVBT_THD_DW1
, 0xec},
367 {DVBT_INTER_CNT_LEN
, 0xc},
368 {DVBT_GI_PGA_STATE
, 0x0},
369 {DVBT_EN_AGC_PGA
, 0x1},
372 {DVBT_REG_MONSEL
, 0x1},
374 {DVBT_REG_4MSEL
, 0x0},
375 {DVBT_SPEC_INV
, 0x0},
378 static const struct rtl2832_reg_value rtl2832_tuner_init_r820t
[] = {
379 {DVBT_DAGC_TRG_VAL
, 0x39},
380 {DVBT_AGC_TARG_VAL_0
, 0x0},
381 {DVBT_AGC_TARG_VAL_8_1
, 0x40},
382 {DVBT_AAGC_LOOP_GAIN
, 0x16},
383 {DVBT_LOOP_GAIN2_3_0
, 0x8},
384 {DVBT_LOOP_GAIN2_4
, 0x1},
385 {DVBT_LOOP_GAIN3
, 0x18},
393 {DVBT_IF_AGC_MIN
, 0x80},
394 {DVBT_IF_AGC_MAX
, 0x7f},
395 {DVBT_RF_AGC_MIN
, 0x80},
396 {DVBT_RF_AGC_MAX
, 0x7f},
397 {DVBT_POLAR_RF_AGC
, 0x0},
398 {DVBT_POLAR_IF_AGC
, 0x0},
399 {DVBT_AD7_SETTING
, 0xe9f4},
400 {DVBT_SPEC_INV
, 0x1},
403 static const struct rtl2832_reg_value rtl2832_tuner_init_si2157
[] = {
404 {DVBT_DAGC_TRG_VAL
, 0x39},
405 {DVBT_AGC_TARG_VAL_0
, 0x0},
406 {DVBT_AGC_TARG_VAL_8_1
, 0x40},
407 {DVBT_AAGC_LOOP_GAIN
, 0x16},
408 {DVBT_LOOP_GAIN2_3_0
, 0x8},
409 {DVBT_LOOP_GAIN2_4
, 0x1},
410 {DVBT_LOOP_GAIN3
, 0x18},
418 {DVBT_IF_AGC_MIN
, 0x80},
419 {DVBT_IF_AGC_MAX
, 0x7f},
420 {DVBT_RF_AGC_MIN
, 0x80},
421 {DVBT_RF_AGC_MAX
, 0x7f},
422 {DVBT_POLAR_RF_AGC
, 0x0},
423 {DVBT_POLAR_IF_AGC
, 0x0},
424 {DVBT_AD7_SETTING
, 0xe9f4},
425 {DVBT_SPEC_INV
, 0x0},
428 #endif /* RTL2832_PRIV_H */