drivers/media/pci/cx18/cx18-av-firmware.c

   1 /*
   2  *  cx18 ADEC firmware functions
   3  *
   4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   5  *  Copyright (C) 2008  Andy Walls <awalls@md.metrocast.net>
   6  *
   7  *  This program is free software; you can redistribute it and/or
   8  *  modify it under the terms of the GNU General Public License
   9  *  as published by the Free Software Foundation; either version 2
  10  *  of the License, or (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  */
  17
  18 #include "cx18-driver.h"
  19 #include "cx18-io.h"
  20 #include <linux/firmware.h>
  21
  22 #define CX18_AUDIO_ENABLE    0xc72014
  23 #define CX18_AI1_MUX_MASK    0x30
  24 #define CX18_AI1_MUX_I2S1    0x00
  25 #define CX18_AI1_MUX_I2S2    0x10
  26 #define CX18_AI1_MUX_843_I2S 0x20
  27 #define CX18_AI1_MUX_INVALID 0x30
  28
  29 #define FWFILE "v4l-cx23418-dig.fw"
  30
  31 static int cx18_av_verifyfw(struct cx18 *cx, const struct firmware *fw)
  32 {
  33         struct v4l2_subdev *sd = &cx->av_state.sd;
  34         int ret = 0;
  35         const u8 *data;
  36         u32 size;
  37         int addr;
  38         u32 expected, dl_control;
  39
  40         /* Ensure we put the 8051 in reset and enable firmware upload mode */
  41         dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
  42         do {
  43                 dl_control &= 0x00ffffff;
  44                 dl_control |= 0x0f000000;
  45                 cx18_av_write4_noretry(cx, CXADEC_DL_CTL, dl_control);
  46                 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
  47         } while ((dl_control & 0xff000000) != 0x0f000000);
  48
  49         /* Read and auto increment until at address 0x0000 */
  50         while (dl_control & 0x3fff)
  51                 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
  52
  53         data = fw->data;
  54         size = fw->size;
  55         for (addr = 0; addr < size; addr++) {
  56                 dl_control &= 0xffff3fff; /* ignore top 2 bits of address */
  57                 expected = 0x0f000000 | ((u32)data[addr] << 16) | addr;
  58                 if (expected != dl_control) {
  59                         CX18_ERR_DEV(sd, "verification of %s firmware load failed: expected %#010x got %#010x\n",
  60                                      FWFILE, expected, dl_control);
  61                         ret = -EIO;
  62                         break;
  63                 }
  64                 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
  65         }
  66         if (ret == 0)
  67                 CX18_INFO_DEV(sd, "verified load of %s firmware (%d bytes)\n",
  68                               FWFILE, size);
  69         return ret;
  70 }
  71
  72 int cx18_av_loadfw(struct cx18 *cx)
  73 {
  74         struct v4l2_subdev *sd = &cx->av_state.sd;
  75         const struct firmware *fw = NULL;
  76         u32 size;
  77         u32 u, v;
  78         const u8 *ptr;
  79         int i;
  80         int retries1 = 0;
  81
  82         if (request_firmware(&fw, FWFILE, &cx->pci_dev->dev) != 0) {
  83                 CX18_ERR_DEV(sd, "unable to open firmware %s\n", FWFILE);
  84                 return -EINVAL;
  85         }
  86
  87         /* The firmware load often has byte errors, so allow for several
  88            retries, both at byte level and at the firmware load level. */
  89         while (retries1 < 5) {
  90                 cx18_av_write4_expect(cx, CXADEC_CHIP_CTRL, 0x00010000,
  91                                           0x00008430, 0xffffffff); /* cx25843 */
  92                 cx18_av_write_expect(cx, CXADEC_STD_DET_CTL, 0xf6, 0xf6, 0xff);
  93
  94                 /* Reset the Mako core, Register is alias of CXADEC_CHIP_CTRL */
  95                 cx18_av_write4_expect(cx, 0x8100, 0x00010000,
  96                                           0x00008430, 0xffffffff); /* cx25843 */
  97
  98                 /* Put the 8051 in reset and enable firmware upload */
  99                 cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000);
 100
 101                 ptr = fw->data;
 102                 size = fw->size;
 103
 104                 for (i = 0; i < size; i++) {
 105                         u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16);
 106                         u32 value = 0;
 107                         int retries2;
 108                         int unrec_err = 0;
 109
 110                         for (retries2 = 0; retries2 < CX18_MAX_MMIO_WR_RETRIES;
 111                              retries2++) {
 112                                 cx18_av_write4_noretry(cx, CXADEC_DL_CTL,
 113                                                        dl_control);
 114                                 udelay(10);
 115                                 value = cx18_av_read4(cx, CXADEC_DL_CTL);
 116                                 if (value == dl_control)
 117                                         break;
 118                                 /* Check if we can correct the byte by changing
 119                                    the address.  We can only write the lower
 120                                    address byte of the address. */
 121                                 if ((value & 0x3F00) != (dl_control & 0x3F00)) {
 122                                         unrec_err = 1;
 123                                         break;
 124                                 }
 125                         }
 126                         if (unrec_err || retries2 >= CX18_MAX_MMIO_WR_RETRIES)
 127                                 break;
 128                 }
 129                 if (i == size)
 130                         break;
 131                 retries1++;
 132         }
 133         if (retries1 >= 5) {
 134                 CX18_ERR_DEV(sd, "unable to load firmware %s\n", FWFILE);
 135                 release_firmware(fw);
 136                 return -EIO;
 137         }
 138
 139         cx18_av_write4_expect(cx, CXADEC_DL_CTL,
 140                                 0x03000000 | fw->size, 0x03000000, 0x13000000);
 141
 142         CX18_INFO_DEV(sd, "loaded %s firmware (%d bytes)\n", FWFILE, size);
 143
 144         if (cx18_av_verifyfw(cx, fw) == 0)
 145                 cx18_av_write4_expect(cx, CXADEC_DL_CTL,
 146                                 0x13000000 | fw->size, 0x13000000, 0x13000000);
 147
 148         /* Output to the 416 */
 149         cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x78000);
 150
 151         /* Audio input control 1 set to Sony mode */
 152         /* Audio output input 2 is 0 for slave operation input */
 153         /* 0xC4000914[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
 154         /* 0xC4000914[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
 155            after WS transition for first bit of audio word. */
 156         cx18_av_write4(cx, CXADEC_I2S_IN_CTL, 0x000000A0);
 157
 158         /* Audio output control 1 is set to Sony mode */
 159         /* Audio output control 2 is set to 1 for master mode */
 160         /* 0xC4000918[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
 161         /* 0xC4000918[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
 162            after WS transition for first bit of audio word. */
 163         /* 0xC4000918[8]: 0 = slave operation, 1 = master (SCK_OUT and WS_OUT
 164            are generated) */
 165         cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0);
 166
 167         /* set alt I2s master clock to /0x16 and enable alt divider i2s
 168            passthrough */
 169         cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687);
 170
 171         cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6,
 172                                                                   0x3F00FFFF);
 173         /* CxDevWrReg(CXADEC_STD_DET_CTL, 0x000000FF); */
 174
 175         /* Set bit 0 in register 0x9CC to signify that this is MiniMe. */
 176         /* Register 0x09CC is defined by the Merlin firmware, and doesn't
 177            have a name in the spec. */
 178         cx18_av_write4(cx, 0x09CC, 1);
 179
 180         v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
 181         /* If bit 11 is 1, clear bit 10 */
 182         if (v & 0x800)
 183                 cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE,
 184                                       0, 0x400);
 185
 186         /* Toggle the AI1 MUX */
 187         v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
 188         u = v & CX18_AI1_MUX_MASK;
 189         v &= ~CX18_AI1_MUX_MASK;
 190         if (u == CX18_AI1_MUX_843_I2S || u == CX18_AI1_MUX_INVALID) {
 191                 /* Switch to I2S1 */
 192                 v |= CX18_AI1_MUX_I2S1;
 193                 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
 194                                       v, CX18_AI1_MUX_MASK);
 195                 /* Switch back to the A/V decoder core I2S output */
 196                 v = (v & ~CX18_AI1_MUX_MASK) | CX18_AI1_MUX_843_I2S;
 197         } else {
 198                 /* Switch to the A/V decoder core I2S output */
 199                 v |= CX18_AI1_MUX_843_I2S;
 200                 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
 201                                       v, CX18_AI1_MUX_MASK);
 202                 /* Switch back to I2S1 or I2S2 */
 203                 v = (v & ~CX18_AI1_MUX_MASK) | u;
 204         }
 205         cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
 206                               v, CX18_AI1_MUX_MASK);
 207
 208         /* Enable WW auto audio standard detection */
 209         v = cx18_av_read4(cx, CXADEC_STD_DET_CTL);
 210         v |= 0xFF;   /* Auto by default */
 211         v |= 0x400;  /* Stereo by default */
 212         v |= 0x14000000;
 213         cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, v, v, 0x3F00FFFF);
 214
 215         release_firmware(fw);
 216         return 0;
 217 }
 218
 219 MODULE_FIRMWARE(FWFILE);