drivers/media/platform/vsp1/vsp1_pipe.c

   1 /*
   2  * vsp1_pipe.c  --  R-Car VSP1 Pipeline
   3  *
   4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/list.h>
  16 #include <linux/sched.h>
  17 #include <linux/wait.h>
  18
  19 #include <media/media-entity.h>
  20 #include <media/v4l2-subdev.h>
  21
  22 #include "vsp1.h"
  23 #include "vsp1_bru.h"
  24 #include "vsp1_dl.h"
  25 #include "vsp1_entity.h"
  26 #include "vsp1_hgo.h"
  27 #include "vsp1_hgt.h"
  28 #include "vsp1_pipe.h"
  29 #include "vsp1_rwpf.h"
  30 #include "vsp1_uds.h"
  31
  32 /* -----------------------------------------------------------------------------
  33  * Helper Functions
  34  */
  35
  36 static const struct vsp1_format_info vsp1_video_formats[] = {
  37         { V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32,
  38           VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  39           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  40           1, { 8, 0, 0 }, false, false, 1, 1, false },
  41         { V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
  42           VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  43           VI6_RPF_DSWAP_P_WDS,
  44           1, { 16, 0, 0 }, false, false, 1, 1, true },
  45         { V4L2_PIX_FMT_XRGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
  46           VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  47           VI6_RPF_DSWAP_P_WDS,
  48           1, { 16, 0, 0 }, false, false, 1, 1, false },
  49         { V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
  50           VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  51           VI6_RPF_DSWAP_P_WDS,
  52           1, { 16, 0, 0 }, false, false, 1, 1, true },
  53         { V4L2_PIX_FMT_XRGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
  54           VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  55           VI6_RPF_DSWAP_P_WDS,
  56           1, { 16, 0, 0 }, false, false, 1, 1, false },
  57         { V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32,
  58           VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  59           VI6_RPF_DSWAP_P_WDS,
  60           1, { 16, 0, 0 }, false, false, 1, 1, false },
  61         { V4L2_PIX_FMT_BGR24, MEDIA_BUS_FMT_ARGB8888_1X32,
  62           VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  63           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  64           1, { 24, 0, 0 }, false, false, 1, 1, false },
  65         { V4L2_PIX_FMT_RGB24, MEDIA_BUS_FMT_ARGB8888_1X32,
  66           VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  67           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  68           1, { 24, 0, 0 }, false, false, 1, 1, false },
  69         { V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
  70           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
  71           1, { 32, 0, 0 }, false, false, 1, 1, true },
  72         { V4L2_PIX_FMT_XBGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
  73           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
  74           1, { 32, 0, 0 }, false, false, 1, 1, false },
  75         { V4L2_PIX_FMT_ARGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
  76           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  77           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  78           1, { 32, 0, 0 }, false, false, 1, 1, true },
  79         { V4L2_PIX_FMT_XRGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
  80           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  81           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  82           1, { 32, 0, 0 }, false, false, 1, 1, false },
  83         { V4L2_PIX_FMT_HSV24, MEDIA_BUS_FMT_AHSV8888_1X32,
  84           VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  85           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  86           1, { 24, 0, 0 }, false, false, 1, 1, false },
  87         { V4L2_PIX_FMT_HSV32, MEDIA_BUS_FMT_AHSV8888_1X32,
  88           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  89           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  90           1, { 32, 0, 0 }, false, false, 1, 1, false },
  91         { V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32,
  92           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  93           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  94           1, { 16, 0, 0 }, false, false, 2, 1, false },
  95         { V4L2_PIX_FMT_VYUY, MEDIA_BUS_FMT_AYUV8_1X32,
  96           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  97           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  98           1, { 16, 0, 0 }, false, true, 2, 1, false },
  99         { V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_AYUV8_1X32,
 100           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 101           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 102           1, { 16, 0, 0 }, true, false, 2, 1, false },
 103         { V4L2_PIX_FMT_YVYU, MEDIA_BUS_FMT_AYUV8_1X32,
 104           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 105           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 106           1, { 16, 0, 0 }, true, true, 2, 1, false },
 107         { V4L2_PIX_FMT_NV12M, MEDIA_BUS_FMT_AYUV8_1X32,
 108           VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 109           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 110           2, { 8, 16, 0 }, false, false, 2, 2, false },
 111         { V4L2_PIX_FMT_NV21M, MEDIA_BUS_FMT_AYUV8_1X32,
 112           VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 113           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 114           2, { 8, 16, 0 }, false, true, 2, 2, false },
 115         { V4L2_PIX_FMT_NV16M, MEDIA_BUS_FMT_AYUV8_1X32,
 116           VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 117           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 118           2, { 8, 16, 0 }, false, false, 2, 1, false },
 119         { V4L2_PIX_FMT_NV61M, MEDIA_BUS_FMT_AYUV8_1X32,
 120           VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 121           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 122           2, { 8, 16, 0 }, false, true, 2, 1, false },
 123         { V4L2_PIX_FMT_YUV420M, MEDIA_BUS_FMT_AYUV8_1X32,
 124           VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 125           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 126           3, { 8, 8, 8 }, false, false, 2, 2, false },
 127         { V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32,
 128           VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 129           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 130           3, { 8, 8, 8 }, false, true, 2, 2, false },
 131         { V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32,
 132           VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 133           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 134           3, { 8, 8, 8 }, false, false, 2, 1, false },
 135         { V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32,
 136           VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 137           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 138           3, { 8, 8, 8 }, false, true, 2, 1, false },
 139         { V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32,
 140           VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 141           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 142           3, { 8, 8, 8 }, false, false, 1, 1, false },
 143         { V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32,
 144           VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 145           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 146           3, { 8, 8, 8 }, false, true, 1, 1, false },
 147 };
 148
 149 /**
 150  * vsp1_get_format_info - Retrieve format information for a 4CC
 151  * @vsp1: the VSP1 device
 152  * @fourcc: the format 4CC
 153  *
 154  * Return a pointer to the format information structure corresponding to the
 155  * given V4L2 format 4CC, or NULL if no corresponding format can be found.
 156  */
 157 const struct vsp1_format_info *vsp1_get_format_info(struct vsp1_device *vsp1,
 158                                                     u32 fourcc)
 159 {
 160         unsigned int i;
 161
 162         /* Special case, the VYUY and HSV formats are supported on Gen2 only. */
 163         if (vsp1->info->gen != 2) {
 164                 switch (fourcc) {
 165                 case V4L2_PIX_FMT_VYUY:
 166                 case V4L2_PIX_FMT_HSV24:
 167                 case V4L2_PIX_FMT_HSV32:
 168                         return NULL;
 169                 }
 170         }
 171
 172         for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) {
 173                 const struct vsp1_format_info *info = &vsp1_video_formats[i];
 174
 175                 if (info->fourcc == fourcc)
 176                         return info;
 177         }
 178
 179         return NULL;
 180 }
 181
 182 /* -----------------------------------------------------------------------------
 183  * Pipeline Management
 184  */
 185
 186 void vsp1_pipeline_reset(struct vsp1_pipeline *pipe)
 187 {
 188         unsigned int i;
 189
 190         if (pipe->bru) {
 191                 struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);
 192
 193                 for (i = 0; i < ARRAY_SIZE(bru->inputs); ++i)
 194                         bru->inputs[i].rpf = NULL;
 195         }
 196
 197         for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
 198                 if (pipe->inputs[i]) {
 199                         pipe->inputs[i]->pipe = NULL;
 200                         pipe->inputs[i] = NULL;
 201                 }
 202         }
 203
 204         if (pipe->output) {
 205                 pipe->output->pipe = NULL;
 206                 pipe->output = NULL;
 207         }
 208
 209         if (pipe->hgo) {
 210                 struct vsp1_hgo *hgo = to_hgo(&pipe->hgo->subdev);
 211
 212                 hgo->histo.pipe = NULL;
 213         }
 214
 215         if (pipe->hgt) {
 216                 struct vsp1_hgt *hgt = to_hgt(&pipe->hgt->subdev);
 217
 218                 hgt->histo.pipe = NULL;
 219         }
 220
 221         INIT_LIST_HEAD(&pipe->entities);
 222         pipe->state = VSP1_PIPELINE_STOPPED;
 223         pipe->buffers_ready = 0;
 224         pipe->num_inputs = 0;
 225         pipe->bru = NULL;
 226         pipe->hgo = NULL;
 227         pipe->hgt = NULL;
 228         pipe->lif = NULL;
 229         pipe->uds = NULL;
 230 }
 231
 232 void vsp1_pipeline_init(struct vsp1_pipeline *pipe)
 233 {
 234         mutex_init(&pipe->lock);
 235         spin_lock_init(&pipe->irqlock);
 236         init_waitqueue_head(&pipe->wq);
 237         kref_init(&pipe->kref);
 238
 239         INIT_LIST_HEAD(&pipe->entities);
 240         pipe->state = VSP1_PIPELINE_STOPPED;
 241 }
 242
 243 /* Must be called with the pipe irqlock held. */
 244 void vsp1_pipeline_run(struct vsp1_pipeline *pipe)
 245 {
 246         struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
 247
 248         if (pipe->state == VSP1_PIPELINE_STOPPED) {
 249                 vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index),
 250                            VI6_CMD_STRCMD);
 251                 pipe->state = VSP1_PIPELINE_RUNNING;
 252         }
 253
 254         pipe->buffers_ready = 0;
 255 }
 256
 257 bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe)
 258 {
 259         unsigned long flags;
 260         bool stopped;
 261
 262         spin_lock_irqsave(&pipe->irqlock, flags);
 263         stopped = pipe->state == VSP1_PIPELINE_STOPPED;
 264         spin_unlock_irqrestore(&pipe->irqlock, flags);
 265
 266         return stopped;
 267 }
 268
 269 int vsp1_pipeline_stop(struct vsp1_pipeline *pipe)
 270 {
 271         struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
 272         struct vsp1_entity *entity;
 273         unsigned long flags;
 274         int ret;
 275
 276         if (pipe->lif) {
 277                 /*
 278                  * When using display lists in continuous frame mode the only
 279                  * way to stop the pipeline is to reset the hardware.
 280                  */
 281                 ret = vsp1_reset_wpf(vsp1, pipe->output->entity.index);
 282                 if (ret == 0) {
 283                         spin_lock_irqsave(&pipe->irqlock, flags);
 284                         pipe->state = VSP1_PIPELINE_STOPPED;
 285                         spin_unlock_irqrestore(&pipe->irqlock, flags);
 286                 }
 287         } else {
 288                 /* Otherwise just request a stop and wait. */
 289                 spin_lock_irqsave(&pipe->irqlock, flags);
 290                 if (pipe->state == VSP1_PIPELINE_RUNNING)
 291                         pipe->state = VSP1_PIPELINE_STOPPING;
 292                 spin_unlock_irqrestore(&pipe->irqlock, flags);
 293
 294                 ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
 295                                          msecs_to_jiffies(500));
 296                 ret = ret == 0 ? -ETIMEDOUT : 0;
 297         }
 298
 299         list_for_each_entry(entity, &pipe->entities, list_pipe) {
 300                 if (entity->route && entity->route->reg)
 301                         vsp1_write(vsp1, entity->route->reg,
 302                                    VI6_DPR_NODE_UNUSED);
 303         }
 304
 305         if (pipe->hgo)
 306                 vsp1_write(vsp1, VI6_DPR_HGO_SMPPT,
 307                            (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
 308                            (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));
 309
 310         if (pipe->hgt)
 311                 vsp1_write(vsp1, VI6_DPR_HGT_SMPPT,
 312                            (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
 313                            (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));
 314
 315         v4l2_subdev_call(&pipe->output->entity.subdev, video, s_stream, 0);
 316
 317         return ret;
 318 }
 319
 320 bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe)
 321 {
 322         unsigned int mask;
 323
 324         mask = ((1 << pipe->num_inputs) - 1) << 1;
 325         if (!pipe->lif)
 326                 mask |= 1 << 0;
 327
 328         return pipe->buffers_ready == mask;
 329 }
 330
 331 void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
 332 {
 333         bool completed;
 334
 335         if (pipe == NULL)
 336                 return;
 337
 338         /*
 339          * If the DL commit raced with the frame end interrupt, the commit ends
 340          * up being postponed by one frame. @completed represents whether the
 341          * active frame was finished or postponed.
 342          */
 343         completed = vsp1_dlm_irq_frame_end(pipe->output->dlm);
 344
 345         if (pipe->hgo)
 346                 vsp1_hgo_frame_end(pipe->hgo);
 347
 348         if (pipe->hgt)
 349                 vsp1_hgt_frame_end(pipe->hgt);
 350
 351         /*
 352          * Regardless of frame completion we still need to notify the pipe
 353          * frame_end to account for vblank events.
 354          */
 355         if (pipe->frame_end)
 356                 pipe->frame_end(pipe, completed);
 357
 358         pipe->sequence++;
 359 }
 360
 361 /*
 362  * Propagate the alpha value through the pipeline.
 363  *
 364  * As the UDS has restricted scaling capabilities when the alpha component needs
 365  * to be scaled, we disable alpha scaling when the UDS input has a fixed alpha
 366  * value. The UDS then outputs a fixed alpha value which needs to be programmed
 367  * from the input RPF alpha.
 368  */
 369 void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
 370                                    struct vsp1_dl_list *dl, unsigned int alpha)
 371 {
 372         if (!pipe->uds)
 373                 return;
 374
 375         /*
 376          * The BRU and BRS background color has a fixed alpha value set to 255,
 377          * the output alpha value is thus always equal to 255.
 378          */
 379         if (pipe->uds_input->type == VSP1_ENTITY_BRU ||
 380             pipe->uds_input->type == VSP1_ENTITY_BRS)
 381                 alpha = 255;
 382
 383         vsp1_uds_set_alpha(pipe->uds, dl, alpha);
 384 }
 385
 386 /*
 387  * Propagate the partition calculations through the pipeline
 388  *
 389  * Work backwards through the pipe, allowing each entity to update the partition
 390  * parameters based on its configuration, and the entity connected to its
 391  * source. Each entity must produce the partition required for the previous
 392  * entity in the pipeline.
 393  */
 394 void vsp1_pipeline_propagate_partition(struct vsp1_pipeline *pipe,
 395                                        struct vsp1_partition *partition,
 396                                        unsigned int index,
 397                                        struct vsp1_partition_window *window)
 398 {
 399         struct vsp1_entity *entity;
 400
 401         list_for_each_entry_reverse(entity, &pipe->entities, list_pipe) {
 402                 if (entity->ops->partition)
 403                         entity->ops->partition(entity, pipe, partition, index,
 404                                                window);
 405         }
 406 }
 407
 408 void vsp1_pipelines_suspend(struct vsp1_device *vsp1)
 409 {
 410         unsigned long flags;
 411         unsigned int i;
 412         int ret;
 413
 414         /*
 415          * To avoid increasing the system suspend time needlessly, loop over the
 416          * pipelines twice, first to set them all to the stopping state, and
 417          * then to wait for the stop to complete.
 418          */
 419         for (i = 0; i < vsp1->info->wpf_count; ++i) {
 420                 struct vsp1_rwpf *wpf = vsp1->wpf[i];
 421                 struct vsp1_pipeline *pipe;
 422
 423                 if (wpf == NULL)
 424                         continue;
 425
 426                 pipe = wpf->pipe;
 427                 if (pipe == NULL)
 428                         continue;
 429
 430                 spin_lock_irqsave(&pipe->irqlock, flags);
 431                 if (pipe->state == VSP1_PIPELINE_RUNNING)
 432                         pipe->state = VSP1_PIPELINE_STOPPING;
 433                 spin_unlock_irqrestore(&pipe->irqlock, flags);
 434         }
 435
 436         for (i = 0; i < vsp1->info->wpf_count; ++i) {
 437                 struct vsp1_rwpf *wpf = vsp1->wpf[i];
 438                 struct vsp1_pipeline *pipe;
 439
 440                 if (wpf == NULL)
 441                         continue;
 442
 443                 pipe = wpf->pipe;
 444                 if (pipe == NULL)
 445                         continue;
 446
 447                 ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
 448                                          msecs_to_jiffies(500));
 449                 if (ret == 0)
 450                         dev_warn(vsp1->dev, "pipeline %u stop timeout\n",
 451                                  wpf->entity.index);
 452         }
 453 }
 454
 455 void vsp1_pipelines_resume(struct vsp1_device *vsp1)
 456 {
 457         unsigned long flags;
 458         unsigned int i;
 459
 460         /* Resume all running pipelines. */
 461         for (i = 0; i < vsp1->info->wpf_count; ++i) {
 462                 struct vsp1_rwpf *wpf = vsp1->wpf[i];
 463                 struct vsp1_pipeline *pipe;
 464
 465                 if (wpf == NULL)
 466                         continue;
 467
 468                 pipe = wpf->pipe;
 469                 if (pipe == NULL)
 470                         continue;
 471
 472                 spin_lock_irqsave(&pipe->irqlock, flags);
 473                 if (vsp1_pipeline_ready(pipe))
 474                         vsp1_pipeline_run(pipe);
 475                 spin_unlock_irqrestore(&pipe->irqlock, flags);
 476         }
 477 }