drivers/misc/cxl/cxl.h

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #ifndef _CXL_H_
  11 #define _CXL_H_
  12
  13 #include <linux/interrupt.h>
  14 #include <linux/semaphore.h>
  15 #include <linux/device.h>
  16 #include <linux/types.h>
  17 #include <linux/cdev.h>
  18 #include <linux/pid.h>
  19 #include <linux/io.h>
  20 #include <linux/pci.h>
  21 #include <linux/fs.h>
  22 #include <asm/cputable.h>
  23 #include <asm/mmu.h>
  24 #include <asm/reg.h>
  25 #include <misc/cxl-base.h>
  26
  27 #include <misc/cxl.h>
  28 #include <uapi/misc/cxl.h>
  29
  30 extern uint cxl_verbose;
  31
  32 #define CXL_TIMEOUT 5
  33
  34 /*
  35  * Bump version each time a user API change is made, whether it is
  36  * backwards compatible ot not.
  37  */
  38 #define CXL_API_VERSION 3
  39 #define CXL_API_VERSION_COMPATIBLE 1
  40
  41 /*
  42  * Opaque types to avoid accidentally passing registers for the wrong MMIO
  43  *
  44  * At the end of the day, I'm not married to using typedef here, but it might
  45  * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
  46  * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
  47  *
  48  * I'm quite happy if these are changed back to #defines before upstreaming, it
  49  * should be little more than a regexp search+replace operation in this file.
  50  */
  51 typedef struct {
  52         const int x;
  53 } cxl_p1_reg_t;
  54 typedef struct {
  55         const int x;
  56 } cxl_p1n_reg_t;
  57 typedef struct {
  58         const int x;
  59 } cxl_p2n_reg_t;
  60 #define cxl_reg_off(reg) \
  61         (reg.x)
  62
  63 /* Memory maps. Ref CXL Appendix A */
  64
  65 /* PSL Privilege 1 Memory Map */
  66 /* Configuration and Control area - CAIA 1&2 */
  67 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
  68 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
  69 static const cxl_p1_reg_t CXL_PSL_KEY1    = {0x0010};
  70 static const cxl_p1_reg_t CXL_PSL_KEY2    = {0x0018};
  71 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
  72 /* Downloading */
  73 static const cxl_p1_reg_t CXL_PSL_DLCNTL  = {0x0060};
  74 static const cxl_p1_reg_t CXL_PSL_DLADDR  = {0x0068};
  75
  76 /* PSL Lookaside Buffer Management Area - CAIA 1 */
  77 static const cxl_p1_reg_t CXL_PSL_LBISEL  = {0x0080};
  78 static const cxl_p1_reg_t CXL_PSL_SLBIE   = {0x0088};
  79 static const cxl_p1_reg_t CXL_PSL_SLBIA   = {0x0090};
  80 static const cxl_p1_reg_t CXL_PSL_TLBIE   = {0x00A0};
  81 static const cxl_p1_reg_t CXL_PSL_TLBIA   = {0x00A8};
  82 static const cxl_p1_reg_t CXL_PSL_AFUSEL  = {0x00B0};
  83
  84 /* 0x00C0:7EFF Implementation dependent area */
  85 /* PSL registers - CAIA 1 */
  86 static const cxl_p1_reg_t CXL_PSL_FIR1      = {0x0100};
  87 static const cxl_p1_reg_t CXL_PSL_FIR2      = {0x0108};
  88 static const cxl_p1_reg_t CXL_PSL_Timebase  = {0x0110};
  89 static const cxl_p1_reg_t CXL_PSL_VERSION   = {0x0118};
  90 static const cxl_p1_reg_t CXL_PSL_RESLCKTO  = {0x0128};
  91 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
  92 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL  = {0x0148};
  93 static const cxl_p1_reg_t CXL_PSL_DSNDCTL   = {0x0150};
  94 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
  95 static const cxl_p1_reg_t CXL_PSL_TRACE     = {0x0170};
  96 /* XSL registers (Mellanox CX4) */
  97 static const cxl_p1_reg_t CXL_XSL_Timebase  = {0x0100};
  98 static const cxl_p1_reg_t CXL_XSL_TB_CTLSTAT = {0x0108};
  99 static const cxl_p1_reg_t CXL_XSL_FEC       = {0x0158};
 100 static const cxl_p1_reg_t CXL_XSL_DSNCTL    = {0x0168};
 101 /* PSL registers - CAIA 2 */
 102 static const cxl_p1_reg_t CXL_PSL9_CONTROL  = {0x0020};
 103 static const cxl_p1_reg_t CXL_XSL9_INV      = {0x0110};
 104 static const cxl_p1_reg_t CXL_XSL9_DBG      = {0x0130};
 105 static const cxl_p1_reg_t CXL_XSL9_DEF      = {0x0140};
 106 static const cxl_p1_reg_t CXL_XSL9_DSNCTL   = {0x0168};
 107 static const cxl_p1_reg_t CXL_PSL9_FIR1     = {0x0300};
 108 static const cxl_p1_reg_t CXL_PSL9_FIR_MASK = {0x0308};
 109 static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};
 110 static const cxl_p1_reg_t CXL_PSL9_DEBUG    = {0x0320};
 111 static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};
 112 static const cxl_p1_reg_t CXL_PSL9_DSNDCTL  = {0x0350};
 113 static const cxl_p1_reg_t CXL_PSL9_TB_CTLSTAT = {0x0340};
 114 static const cxl_p1_reg_t CXL_PSL9_TRACECFG = {0x0368};
 115 static const cxl_p1_reg_t CXL_PSL9_APCDEDALLOC = {0x0378};
 116 static const cxl_p1_reg_t CXL_PSL9_APCDEDTYPE = {0x0380};
 117 static const cxl_p1_reg_t CXL_PSL9_TNR_ADDR = {0x0388};
 118 static const cxl_p1_reg_t CXL_PSL9_CTCCFG = {0x0390};
 119 static const cxl_p1_reg_t CXL_PSL9_GP_CT = {0x0398};
 120 static const cxl_p1_reg_t CXL_XSL9_IERAT = {0x0588};
 121 static const cxl_p1_reg_t CXL_XSL9_ILPP  = {0x0590};
 122
 123 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
 124 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
 125
 126 /* PSL Slice Privilege 1 Memory Map */
 127 /* Configuration Area - CAIA 1&2 */
 128 static const cxl_p1n_reg_t CXL_PSL_SR_An          = {0x00};
 129 static const cxl_p1n_reg_t CXL_PSL_LPID_An        = {0x08};
 130 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An       = {0x10};
 131 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An    = {0x18};
 132 static const cxl_p1n_reg_t CXL_PSL_ID_An          = {0x20};
 133 static const cxl_p1n_reg_t CXL_PSL_SERR_An        = {0x28};
 134 /* Memory Management and Lookaside Buffer Management - CAIA 1*/
 135 static const cxl_p1n_reg_t CXL_PSL_SDR_An         = {0x30};
 136 /* Memory Management and Lookaside Buffer Management - CAIA 1&2 */
 137 static const cxl_p1n_reg_t CXL_PSL_AMOR_An        = {0x38};
 138 /* Pointer Area - CAIA 1&2 */
 139 static const cxl_p1n_reg_t CXL_HAURP_An           = {0x80};
 140 static const cxl_p1n_reg_t CXL_PSL_SPAP_An        = {0x88};
 141 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An       = {0x90};
 142 /* Control Area - CAIA 1&2 */
 143 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An       = {0xA0};
 144 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An     = {0xA8};
 145 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
 146 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An  = {0xB8};
 147 /* 0xC0:FF Implementation Dependent Area - CAIA 1&2 */
 148 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An   = {0xC0};
 149 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An       = {0xC8};
 150 /* 0xC0:FF Implementation Dependent Area - CAIA 1 */
 151 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A     = {0xD0};
 152 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A      = {0xD8};
 153 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A        = {0xE0};
 154 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE    = {0xE8};
 155
 156 /* PSL Slice Privilege 2 Memory Map */
 157 /* Configuration and Control Area - CAIA 1&2 */
 158 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
 159 static const cxl_p2n_reg_t CXL_CSRP_An        = {0x008};
 160 /* Configuration and Control Area - CAIA 1 */
 161 static const cxl_p2n_reg_t CXL_AURP0_An       = {0x010};
 162 static const cxl_p2n_reg_t CXL_AURP1_An       = {0x018};
 163 static const cxl_p2n_reg_t CXL_SSTP0_An       = {0x020};
 164 static const cxl_p2n_reg_t CXL_SSTP1_An       = {0x028};
 165 /* Configuration and Control Area - CAIA 1 */
 166 static const cxl_p2n_reg_t CXL_PSL_AMR_An     = {0x030};
 167 /* Segment Lookaside Buffer Management - CAIA 1 */
 168 static const cxl_p2n_reg_t CXL_SLBIE_An       = {0x040};
 169 static const cxl_p2n_reg_t CXL_SLBIA_An       = {0x048};
 170 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
 171 /* Interrupt Registers - CAIA 1&2 */
 172 static const cxl_p2n_reg_t CXL_PSL_DSISR_An   = {0x060};
 173 static const cxl_p2n_reg_t CXL_PSL_DAR_An     = {0x068};
 174 static const cxl_p2n_reg_t CXL_PSL_DSR_An     = {0x070};
 175 static const cxl_p2n_reg_t CXL_PSL_TFC_An     = {0x078};
 176 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
 177 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
 178 /* AFU Registers - CAIA 1&2 */
 179 static const cxl_p2n_reg_t CXL_AFU_Cntl_An    = {0x090};
 180 static const cxl_p2n_reg_t CXL_AFU_ERR_An     = {0x098};
 181 /* Work Element Descriptor - CAIA 1&2 */
 182 static const cxl_p2n_reg_t CXL_PSL_WED_An     = {0x0A0};
 183 /* 0x0C0:FFF Implementation Dependent Area */
 184
 185 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
 186 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
 187 #define CXL_PSL_SPAP_Size_Shift 4
 188 #define CXL_PSL_SPAP_V    0x0000000000000001ULL
 189
 190 /****** CXL_PSL_Control ****************************************************/
 191 #define CXL_PSL_Control_tb              (0x1ull << (63-63))
 192 #define CXL_PSL_Control_Fr              (0x1ull << (63-31))
 193 #define CXL_PSL_Control_Fs_MASK         (0x3ull << (63-29))
 194 #define CXL_PSL_Control_Fs_Complete     (0x3ull << (63-29))
 195
 196 /****** CXL_PSL_DLCNTL *****************************************************/
 197 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
 198 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
 199 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
 200 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
 201 #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
 202 #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
 203
 204 /****** CXL_PSL_SR_An ******************************************************/
 205 #define CXL_PSL_SR_An_SF  MSR_SF            /* 64bit */
 206 #define CXL_PSL_SR_An_TA  (1ull << (63-1))  /* Tags active,   GA1: 0 */
 207 #define CXL_PSL_SR_An_HV  MSR_HV            /* Hypervisor,    GA1: 0 */
 208 #define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
 209 #define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
 210 #define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
 211 #define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
 212 #define CXL_PSL_SR_An_PR  MSR_PR            /* Problem state, GA1: 1 */
 213 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
 214 #define CXL_PSL_SR_An_TC  (1ull << (63-54)) /* Page Table secondary hash */
 215 #define CXL_PSL_SR_An_US  (1ull << (63-56)) /* User state,    GA1: X */
 216 #define CXL_PSL_SR_An_SC  (1ull << (63-58)) /* Segment Table secondary hash */
 217 #define CXL_PSL_SR_An_R   MSR_DR            /* Relocate,      GA1: 1 */
 218 #define CXL_PSL_SR_An_MP  (1ull << (63-62)) /* Master Process */
 219 #define CXL_PSL_SR_An_LE  (1ull << (63-63)) /* Little Endian */
 220
 221 /****** CXL_PSL_ID_An ****************************************************/
 222 #define CXL_PSL_ID_An_F (1ull << (63-31))
 223 #define CXL_PSL_ID_An_L (1ull << (63-30))
 224
 225 /****** CXL_PSL_SERR_An ****************************************************/
 226 #define CXL_PSL_SERR_An_afuto   (1ull << (63-0))
 227 #define CXL_PSL_SERR_An_afudis  (1ull << (63-1))
 228 #define CXL_PSL_SERR_An_afuov   (1ull << (63-2))
 229 #define CXL_PSL_SERR_An_badsrc  (1ull << (63-3))
 230 #define CXL_PSL_SERR_An_badctx  (1ull << (63-4))
 231 #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
 232 #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
 233 #define CXL_PSL_SERR_An_afupar  (1ull << (63-7))
 234 #define CXL_PSL_SERR_An_afudup  (1ull << (63-8))
 235 #define CXL_PSL_SERR_An_IRQS    ( \
 236         CXL_PSL_SERR_An_afuto | CXL_PSL_SERR_An_afudis | CXL_PSL_SERR_An_afuov | \
 237         CXL_PSL_SERR_An_badsrc | CXL_PSL_SERR_An_badctx | CXL_PSL_SERR_An_llcmdis | \
 238         CXL_PSL_SERR_An_llcmdto | CXL_PSL_SERR_An_afupar | CXL_PSL_SERR_An_afudup)
 239 #define CXL_PSL_SERR_An_afuto_mask      (1ull << (63-32))
 240 #define CXL_PSL_SERR_An_afudis_mask     (1ull << (63-33))
 241 #define CXL_PSL_SERR_An_afuov_mask      (1ull << (63-34))
 242 #define CXL_PSL_SERR_An_badsrc_mask     (1ull << (63-35))
 243 #define CXL_PSL_SERR_An_badctx_mask     (1ull << (63-36))
 244 #define CXL_PSL_SERR_An_llcmdis_mask    (1ull << (63-37))
 245 #define CXL_PSL_SERR_An_llcmdto_mask    (1ull << (63-38))
 246 #define CXL_PSL_SERR_An_afupar_mask     (1ull << (63-39))
 247 #define CXL_PSL_SERR_An_afudup_mask     (1ull << (63-40))
 248 #define CXL_PSL_SERR_An_IRQ_MASKS       ( \
 249         CXL_PSL_SERR_An_afuto_mask | CXL_PSL_SERR_An_afudis_mask | CXL_PSL_SERR_An_afuov_mask | \
 250         CXL_PSL_SERR_An_badsrc_mask | CXL_PSL_SERR_An_badctx_mask | CXL_PSL_SERR_An_llcmdis_mask | \
 251         CXL_PSL_SERR_An_llcmdto_mask | CXL_PSL_SERR_An_afupar_mask | CXL_PSL_SERR_An_afudup_mask)
 252
 253 #define CXL_PSL_SERR_An_AE      (1ull << (63-30))
 254
 255 /****** CXL_PSL_SCNTL_An ****************************************************/
 256 #define CXL_PSL_SCNTL_An_CR          (0x1ull << (63-15))
 257 /* Programming Modes: */
 258 #define CXL_PSL_SCNTL_An_PM_MASK     (0xffffull << (63-31))
 259 #define CXL_PSL_SCNTL_An_PM_Shared   (0x0000ull << (63-31))
 260 #define CXL_PSL_SCNTL_An_PM_OS       (0x0001ull << (63-31))
 261 #define CXL_PSL_SCNTL_An_PM_Process  (0x0002ull << (63-31))
 262 #define CXL_PSL_SCNTL_An_PM_AFU      (0x0004ull << (63-31))
 263 #define CXL_PSL_SCNTL_An_PM_AFU_PBT  (0x0104ull << (63-31))
 264 /* Purge Status (ro) */
 265 #define CXL_PSL_SCNTL_An_Ps_MASK     (0x3ull << (63-39))
 266 #define CXL_PSL_SCNTL_An_Ps_Pending  (0x1ull << (63-39))
 267 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
 268 /* Purge */
 269 #define CXL_PSL_SCNTL_An_Pc          (0x1ull << (63-48))
 270 /* Suspend Status (ro) */
 271 #define CXL_PSL_SCNTL_An_Ss_MASK     (0x3ull << (63-55))
 272 #define CXL_PSL_SCNTL_An_Ss_Pending  (0x1ull << (63-55))
 273 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
 274 /* Suspend Control */
 275 #define CXL_PSL_SCNTL_An_Sc          (0x1ull << (63-63))
 276
 277 /* AFU Slice Enable Status (ro) */
 278 #define CXL_AFU_Cntl_An_ES_MASK     (0x7ull << (63-2))
 279 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
 280 #define CXL_AFU_Cntl_An_ES_Enabled  (0x4ull << (63-2))
 281 /* AFU Slice Enable */
 282 #define CXL_AFU_Cntl_An_E           (0x1ull << (63-3))
 283 /* AFU Slice Reset status (ro) */
 284 #define CXL_AFU_Cntl_An_RS_MASK     (0x3ull << (63-5))
 285 #define CXL_AFU_Cntl_An_RS_Pending  (0x1ull << (63-5))
 286 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
 287 /* AFU Slice Reset */
 288 #define CXL_AFU_Cntl_An_RA          (0x1ull << (63-7))
 289
 290 /****** CXL_SSTP0/1_An ******************************************************/
 291 /* These top bits are for the segment that CONTAINS the segment table */
 292 #define CXL_SSTP0_An_B_SHIFT    SLB_VSID_SSIZE_SHIFT
 293 #define CXL_SSTP0_An_KS             (1ull << (63-2))
 294 #define CXL_SSTP0_An_KP             (1ull << (63-3))
 295 #define CXL_SSTP0_An_N              (1ull << (63-4))
 296 #define CXL_SSTP0_An_L              (1ull << (63-5))
 297 #define CXL_SSTP0_An_C              (1ull << (63-6))
 298 #define CXL_SSTP0_An_TA             (1ull << (63-7))
 299 #define CXL_SSTP0_An_LP_SHIFT                (63-9)  /* 2 Bits */
 300 /* And finally, the virtual address & size of the segment table: */
 301 #define CXL_SSTP0_An_SegTableSize_SHIFT      (63-31) /* 12 Bits */
 302 #define CXL_SSTP0_An_SegTableSize_MASK \
 303         (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
 304 #define CXL_SSTP0_An_STVA_U_MASK   ((1ull << (63-49))-1)
 305 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
 306 #define CXL_SSTP1_An_V              (1ull << (63-63))
 307
 308 /****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/
 309 /* write: */
 310 #define CXL_SLBIE_C        PPC_BIT(36)         /* Class */
 311 #define CXL_SLBIE_SS       PPC_BITMASK(37, 38) /* Segment Size */
 312 #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
 313 #define CXL_SLBIE_TA       PPC_BIT(38)         /* Tags Active */
 314 /* read: */
 315 #define CXL_SLBIE_MAX      PPC_BITMASK(24, 31)
 316 #define CXL_SLBIE_PENDING  PPC_BITMASK(56, 63)
 317
 318 /****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/
 319 #define CXL_TLB_SLB_P          (1ull) /* Pending (read) */
 320
 321 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/
 322 #define CXL_TLB_SLB_IQ_ALL     (0ull) /* Inv qualifier */
 323 #define CXL_TLB_SLB_IQ_LPID    (1ull) /* Inv qualifier */
 324 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
 325
 326 /****** CXL_PSL_AFUSEL ******************************************************/
 327 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
 328
 329 /****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/
 330 #define CXL_PSL_DSISR_An_DS (1ull << (63-0))  /* Segment not found */
 331 #define CXL_PSL_DSISR_An_DM (1ull << (63-1))  /* PTE not found (See also: M) or protection fault */
 332 #define CXL_PSL_DSISR_An_ST (1ull << (63-2))  /* Segment Table PTE not found */
 333 #define CXL_PSL_DSISR_An_UR (1ull << (63-3))  /* AURP PTE not found */
 334 #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
 335 #define CXL_PSL_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
 336 #define CXL_PSL_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
 337 #define CXL_PSL_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
 338 #define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
 339 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
 340 #define CXL_PSL_DSISR_An_M  DSISR_NOHPTE      /* PTE not found */
 341 #define CXL_PSL_DSISR_An_P  DSISR_PROTFAULT   /* Storage protection violation */
 342 #define CXL_PSL_DSISR_An_A  (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
 343 #define CXL_PSL_DSISR_An_S  DSISR_ISSTORE     /* Access was afu_wr or afu_zero */
 344 #define CXL_PSL_DSISR_An_K  DSISR_KEYFAULT    /* Access not permitted by virtual page class key protection */
 345
 346 /****** CXL_PSL_DSISR_An - CAIA 2 ****************************************************/
 347 #define CXL_PSL9_DSISR_An_TF (1ull << (63-3))  /* Translation fault */
 348 #define CXL_PSL9_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
 349 #define CXL_PSL9_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
 350 #define CXL_PSL9_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
 351 #define CXL_PSL9_DSISR_An_S (1ull << (63-38))  /* TF for a write operation */
 352 #define CXL_PSL9_DSISR_PENDING (CXL_PSL9_DSISR_An_TF | CXL_PSL9_DSISR_An_PE | CXL_PSL9_DSISR_An_AE | CXL_PSL9_DSISR_An_OC)
 353 /*
 354  * NOTE: Bits 56:63 (Checkout Response Status) are valid when DSISR_An[TF] = 1
 355  * Status (0:7) Encoding
 356  */
 357 #define CXL_PSL9_DSISR_An_CO_MASK 0x00000000000000ffULL
 358 #define CXL_PSL9_DSISR_An_SF      0x0000000000000080ULL  /* Segment Fault                        0b10000000 */
 359 #define CXL_PSL9_DSISR_An_PF_SLR  0x0000000000000088ULL  /* PTE not found (Single Level Radix)   0b10001000 */
 360 #define CXL_PSL9_DSISR_An_PF_RGC  0x000000000000008CULL  /* PTE not found (Radix Guest (child))  0b10001100 */
 361 #define CXL_PSL9_DSISR_An_PF_RGP  0x0000000000000090ULL  /* PTE not found (Radix Guest (parent)) 0b10010000 */
 362 #define CXL_PSL9_DSISR_An_PF_HRH  0x0000000000000094ULL  /* PTE not found (HPT/Radix Host)       0b10010100 */
 363 #define CXL_PSL9_DSISR_An_PF_STEG 0x000000000000009CULL  /* PTE not found (STEG VA)              0b10011100 */
 364 #define CXL_PSL9_DSISR_An_URTCH   0x00000000000000B4ULL  /* Unsupported Radix Tree Configuration 0b10110100 */
 365
 366 /****** CXL_PSL_TFC_An ******************************************************/
 367 #define CXL_PSL_TFC_An_A  (1ull << (63-28)) /* Acknowledge non-translation fault */
 368 #define CXL_PSL_TFC_An_C  (1ull << (63-29)) /* Continue (abort transaction) */
 369 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
 370 #define CXL_PSL_TFC_An_R  (1ull << (63-31)) /* Restart PSL transaction */
 371
 372 /****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/
 373 #define CXL_XSL9_IERAT_MLPID    (1ull << (63-0))  /* Match LPID */
 374 #define CXL_XSL9_IERAT_MPID     (1ull << (63-1))  /* Match PID */
 375 #define CXL_XSL9_IERAT_PRS      (1ull << (63-4))  /* PRS bit for Radix invalidations */
 376 #define CXL_XSL9_IERAT_INVR     (1ull << (63-3))  /* Invalidate Radix */
 377 #define CXL_XSL9_IERAT_IALL     (1ull << (63-8))  /* Invalidate All */
 378 #define CXL_XSL9_IERAT_IINPROG  (1ull << (63-63)) /* Invalidate in progress */
 379
 380 /* cxl_process_element->software_status */
 381 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 -  0)) /* Valid */
 382 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
 383 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
 384 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
 385
 386 /****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
 387  * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
 388  * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
 389  * of the hang pulse frequency.
 390  */
 391 #define CXL_PSL_RXCTL_AFUHP_4S      0x7000000000000000ULL
 392
 393 /* SPA->sw_command_status */
 394 #define CXL_SPA_SW_CMD_MASK         0xffff000000000000ULL
 395 #define CXL_SPA_SW_CMD_TERMINATE    0x0001000000000000ULL
 396 #define CXL_SPA_SW_CMD_REMOVE       0x0002000000000000ULL
 397 #define CXL_SPA_SW_CMD_SUSPEND      0x0003000000000000ULL
 398 #define CXL_SPA_SW_CMD_RESUME       0x0004000000000000ULL
 399 #define CXL_SPA_SW_CMD_ADD          0x0005000000000000ULL
 400 #define CXL_SPA_SW_CMD_UPDATE       0x0006000000000000ULL
 401 #define CXL_SPA_SW_STATE_MASK       0x0000ffff00000000ULL
 402 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
 403 #define CXL_SPA_SW_STATE_REMOVED    0x0000000200000000ULL
 404 #define CXL_SPA_SW_STATE_SUSPENDED  0x0000000300000000ULL
 405 #define CXL_SPA_SW_STATE_RESUMED    0x0000000400000000ULL
 406 #define CXL_SPA_SW_STATE_ADDED      0x0000000500000000ULL
 407 #define CXL_SPA_SW_STATE_UPDATED    0x0000000600000000ULL
 408 #define CXL_SPA_SW_PSL_ID_MASK      0x00000000ffff0000ULL
 409 #define CXL_SPA_SW_LINK_MASK        0x000000000000ffffULL
 410
 411 #define CXL_MAX_SLICES 4
 412 #define MAX_AFU_MMIO_REGS 3
 413
 414 #define CXL_MODE_TIME_SLICED 0x4
 415 #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
 416
 417 #define CXL_DEV_MINORS 13   /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
 418 #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
 419 #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
 420
 421 #define CXL_PSL9_TRACEID_MAX 0xAU
 422 #define CXL_PSL9_TRACESTATE_FIN 0x3U
 423
 424 enum cxl_context_status {
 425         CLOSED,
 426         OPENED,
 427         STARTED
 428 };
 429
 430 enum prefault_modes {
 431         CXL_PREFAULT_NONE,
 432         CXL_PREFAULT_WED,
 433         CXL_PREFAULT_ALL,
 434 };
 435
 436 enum cxl_attrs {
 437         CXL_ADAPTER_ATTRS,
 438         CXL_AFU_MASTER_ATTRS,
 439         CXL_AFU_ATTRS,
 440 };
 441
 442 struct cxl_sste {
 443         __be64 esid_data;
 444         __be64 vsid_data;
 445 };
 446
 447 #define to_cxl_adapter(d) container_of(d, struct cxl, dev)
 448 #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
 449
 450 struct cxl_afu_native {
 451         void __iomem *p1n_mmio;
 452         void __iomem *afu_desc_mmio;
 453         irq_hw_number_t psl_hwirq;
 454         unsigned int psl_virq;
 455         struct mutex spa_mutex;
 456         /*
 457          * Only the first part of the SPA is used for the process element
 458          * linked list. The only other part that software needs to worry about
 459          * is sw_command_status, which we store a separate pointer to.
 460          * Everything else in the SPA is only used by hardware
 461          */
 462         struct cxl_process_element *spa;
 463         __be64 *sw_command_status;
 464         unsigned int spa_size;
 465         int spa_order;
 466         int spa_max_procs;
 467         u64 pp_offset;
 468 };
 469
 470 struct cxl_afu_guest {
 471         struct cxl_afu *parent;
 472         u64 handle;
 473         phys_addr_t p2n_phys;
 474         u64 p2n_size;
 475         int max_ints;
 476         bool handle_err;
 477         struct delayed_work work_err;
 478         int previous_state;
 479 };
 480
 481 struct cxl_afu {
 482         struct cxl_afu_native *native;
 483         struct cxl_afu_guest *guest;
 484         irq_hw_number_t serr_hwirq;
 485         unsigned int serr_virq;
 486         char *psl_irq_name;
 487         char *err_irq_name;
 488         void __iomem *p2n_mmio;
 489         phys_addr_t psn_phys;
 490         u64 pp_size;
 491
 492         struct cxl *adapter;
 493         struct device dev;
 494         struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
 495         struct device *chardev_s, *chardev_m, *chardev_d;
 496         struct idr contexts_idr;
 497         struct dentry *debugfs;
 498         struct mutex contexts_lock;
 499         spinlock_t afu_cntl_lock;
 500
 501         /* -1: AFU deconfigured/locked, >= 0: number of readers */
 502         atomic_t configured_state;
 503
 504         /* AFU error buffer fields and bin attribute for sysfs */
 505         u64 eb_len, eb_offset;
 506         struct bin_attribute attr_eb;
 507
 508         /* pointer to the vphb */
 509         struct pci_controller *phb;
 510
 511         int pp_irqs;
 512         int irqs_max;
 513         int num_procs;
 514         int max_procs_virtualised;
 515         int slice;
 516         int modes_supported;
 517         int current_mode;
 518         int crs_num;
 519         u64 crs_len;
 520         u64 crs_offset;
 521         struct list_head crs;
 522         enum prefault_modes prefault_mode;
 523         bool psa;
 524         bool pp_psa;
 525         bool enabled;
 526 };
 527
 528
 529 struct cxl_irq_name {
 530         struct list_head list;
 531         char *name;
 532 };
 533
 534 struct irq_avail {
 535         irq_hw_number_t offset;
 536         irq_hw_number_t range;
 537         unsigned long   *bitmap;
 538 };
 539
 540 /*
 541  * This is a cxl context.  If the PSL is in dedicated mode, there will be one
 542  * of these per AFU.  If in AFU directed there can be lots of these.
 543  */
 544 struct cxl_context {
 545         struct cxl_afu *afu;
 546
 547         /* Problem state MMIO */
 548         phys_addr_t psn_phys;
 549         u64 psn_size;
 550
 551         /* Used to unmap any mmaps when force detaching */
 552         struct address_space *mapping;
 553         struct mutex mapping_lock;
 554         struct page *ff_page;
 555         bool mmio_err_ff;
 556         bool kernelapi;
 557
 558         spinlock_t sste_lock; /* Protects segment table entries */
 559         struct cxl_sste *sstp;
 560         u64 sstp0, sstp1;
 561         unsigned int sst_size, sst_lru;
 562
 563         wait_queue_head_t wq;
 564         /* use mm context associated with this pid for ds faults */
 565         struct pid *pid;
 566         spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
 567         /* Only used in PR mode */
 568         u64 process_token;
 569
 570         /* driver private data */
 571         void *priv;
 572
 573         unsigned long *irq_bitmap; /* Accessed from IRQ context */
 574         struct cxl_irq_ranges irqs;
 575         struct list_head irq_names;
 576         u64 fault_addr;
 577         u64 fault_dsisr;
 578         u64 afu_err;
 579
 580         /*
 581          * This status and it's lock pretects start and detach context
 582          * from racing.  It also prevents detach from racing with
 583          * itself
 584          */
 585         enum cxl_context_status status;
 586         struct mutex status_mutex;
 587
 588
 589         /* XXX: Is it possible to need multiple work items at once? */
 590         struct work_struct fault_work;
 591         u64 dsisr;
 592         u64 dar;
 593
 594         struct cxl_process_element *elem;
 595
 596         /*
 597          * pe is the process element handle, assigned by this driver when the
 598          * context is initialized.
 599          *
 600          * external_pe is the PE shown outside of cxl.
 601          * On bare-metal, pe=external_pe, because we decide what the handle is.
 602          * In a guest, we only find out about the pe used by pHyp when the
 603          * context is attached, and that's the value we want to report outside
 604          * of cxl.
 605          */
 606         int pe;
 607         int external_pe;
 608
 609         u32 irq_count;
 610         bool pe_inserted;
 611         bool master;
 612         bool kernel;
 613         bool real_mode;
 614         bool pending_irq;
 615         bool pending_fault;
 616         bool pending_afu_err;
 617
 618         /* Used by AFU drivers for driver specific event delivery */
 619         struct cxl_afu_driver_ops *afu_driver_ops;
 620         atomic_t afu_driver_events;
 621
 622         struct rcu_head rcu;
 623
 624         /*
 625          * Only used when more interrupts are allocated via
 626          * pci_enable_msix_range than are supported in the default context, to
 627          * use additional contexts to overcome the limitation. i.e. Mellanox
 628          * CX4 only:
 629          */
 630         struct list_head extra_irq_contexts;
 631
 632         struct mm_struct *mm;
 633
 634         u16 tidr;
 635         bool assign_tidr;
 636 };
 637
 638 struct cxl_irq_info;
 639
 640 struct cxl_service_layer_ops {
 641         int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
 642         int (*invalidate_all)(struct cxl *adapter);
 643         int (*afu_regs_init)(struct cxl_afu *afu);
 644         int (*sanitise_afu_regs)(struct cxl_afu *afu);
 645         int (*register_serr_irq)(struct cxl_afu *afu);
 646         void (*release_serr_irq)(struct cxl_afu *afu);
 647         irqreturn_t (*handle_interrupt)(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
 648         irqreturn_t (*fail_irq)(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
 649         int (*activate_dedicated_process)(struct cxl_afu *afu);
 650         int (*attach_afu_directed)(struct cxl_context *ctx, u64 wed, u64 amr);
 651         int (*attach_dedicated_process)(struct cxl_context *ctx, u64 wed, u64 amr);
 652         void (*update_dedicated_ivtes)(struct cxl_context *ctx);
 653         void (*debugfs_add_adapter_regs)(struct cxl *adapter, struct dentry *dir);
 654         void (*debugfs_add_afu_regs)(struct cxl_afu *afu, struct dentry *dir);
 655         void (*psl_irq_dump_registers)(struct cxl_context *ctx);
 656         void (*err_irq_dump_registers)(struct cxl *adapter);
 657         void (*debugfs_stop_trace)(struct cxl *adapter);
 658         void (*write_timebase_ctrl)(struct cxl *adapter);
 659         u64 (*timebase_read)(struct cxl *adapter);
 660         int capi_mode;
 661         bool needs_reset_before_disable;
 662 };
 663
 664 struct cxl_native {
 665         u64 afu_desc_off;
 666         u64 afu_desc_size;
 667         void __iomem *p1_mmio;
 668         void __iomem *p2_mmio;
 669         irq_hw_number_t err_hwirq;
 670         unsigned int err_virq;
 671         u64 ps_off;
 672         const struct cxl_service_layer_ops *sl_ops;
 673 };
 674
 675 struct cxl_guest {
 676         struct platform_device *pdev;
 677         int irq_nranges;
 678         struct cdev cdev;
 679         irq_hw_number_t irq_base_offset;
 680         struct irq_avail *irq_avail;
 681         spinlock_t irq_alloc_lock;
 682         u64 handle;
 683         char *status;
 684         u16 vendor;
 685         u16 device;
 686         u16 subsystem_vendor;
 687         u16 subsystem;
 688 };
 689
 690 struct cxl {
 691         struct cxl_native *native;
 692         struct cxl_guest *guest;
 693         spinlock_t afu_list_lock;
 694         struct cxl_afu *afu[CXL_MAX_SLICES];
 695         struct device dev;
 696         struct dentry *trace;
 697         struct dentry *psl_err_chk;
 698         struct dentry *debugfs;
 699         char *irq_name;
 700         struct bin_attribute cxl_attr;
 701         int adapter_num;
 702         int user_irqs;
 703         int min_pe;
 704         u64 ps_size;
 705         u16 psl_rev;
 706         u16 base_image;
 707         u8 vsec_status;
 708         u8 caia_major;
 709         u8 caia_minor;
 710         u8 slices;
 711         bool user_image_loaded;
 712         bool perst_loads_image;
 713         bool perst_select_user;
 714         bool perst_same_image;
 715         bool psl_timebase_synced;
 716
 717         /*
 718          * number of contexts mapped on to this card. Possible values are:
 719          * >0: Number of contexts mapped and new one can be mapped.
 720          *  0: No active contexts and new ones can be mapped.
 721          * -1: No contexts mapped and new ones cannot be mapped.
 722          */
 723         atomic_t contexts_num;
 724 };
 725
 726 int cxl_pci_alloc_one_irq(struct cxl *adapter);
 727 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
 728 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
 729 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
 730 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
 731 int cxl_update_image_control(struct cxl *adapter);
 732 int cxl_pci_reset(struct cxl *adapter);
 733 void cxl_pci_release_afu(struct device *dev);
 734 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
 735
 736 /* common == phyp + powernv - CAIA 1&2 */
 737 struct cxl_process_element_common {
 738         __be32 tid;
 739         __be32 pid;
 740         __be64 csrp;
 741         union {
 742                 struct {
 743                         __be64 aurp0;
 744                         __be64 aurp1;
 745                         __be64 sstp0;
 746                         __be64 sstp1;
 747                 } psl8;  /* CAIA 1 */
 748                 struct {
 749                         u8     reserved2[8];
 750                         u8     reserved3[8];
 751                         u8     reserved4[8];
 752                         u8     reserved5[8];
 753                 } psl9;  /* CAIA 2 */
 754         } u;
 755         __be64 amr;
 756         u8     reserved6[4];
 757         __be64 wed;
 758 } __packed;
 759
 760 /* just powernv - CAIA 1&2 */
 761 struct cxl_process_element {
 762         __be64 sr;
 763         __be64 SPOffset;
 764         union {
 765                 __be64 sdr;          /* CAIA 1 */
 766                 u8     reserved1[8]; /* CAIA 2 */
 767         } u;
 768         __be64 haurp;
 769         __be32 ctxtime;
 770         __be16 ivte_offsets[4];
 771         __be16 ivte_ranges[4];
 772         __be32 lpid;
 773         struct cxl_process_element_common common;
 774         __be32 software_state;
 775 } __packed;
 776
 777 static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
 778 {
 779         struct pci_dev *pdev;
 780
 781         if (cpu_has_feature(CPU_FTR_HVMODE)) {
 782                 pdev = to_pci_dev(cxl->dev.parent);
 783                 return !pci_channel_offline(pdev);
 784         }
 785         return true;
 786 }
 787
 788 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
 789 {
 790         WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 791         return cxl->native->p1_mmio + cxl_reg_off(reg);
 792 }
 793
 794 static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
 795 {
 796         if (likely(cxl_adapter_link_ok(cxl, NULL)))
 797                 out_be64(_cxl_p1_addr(cxl, reg), val);
 798 }
 799
 800 static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
 801 {
 802         if (likely(cxl_adapter_link_ok(cxl, NULL)))
 803                 return in_be64(_cxl_p1_addr(cxl, reg));
 804         else
 805                 return ~0ULL;
 806 }
 807
 808 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 809 {
 810         WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 811         return afu->native->p1n_mmio + cxl_reg_off(reg);
 812 }
 813
 814 static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
 815 {
 816         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 817                 out_be64(_cxl_p1n_addr(afu, reg), val);
 818 }
 819
 820 static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 821 {
 822         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 823                 return in_be64(_cxl_p1n_addr(afu, reg));
 824         else
 825                 return ~0ULL;
 826 }
 827
 828 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 829 {
 830         return afu->p2n_mmio + cxl_reg_off(reg);
 831 }
 832
 833 static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
 834 {
 835         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 836                 out_be64(_cxl_p2n_addr(afu, reg), val);
 837 }
 838
 839 static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 840 {
 841         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 842                 return in_be64(_cxl_p2n_addr(afu, reg));
 843         else
 844                 return ~0ULL;
 845 }
 846
 847 static inline bool cxl_is_power8(void)
 848 {
 849         if ((pvr_version_is(PVR_POWER8E)) ||
 850             (pvr_version_is(PVR_POWER8NVL)) ||
 851             (pvr_version_is(PVR_POWER8)))
 852                 return true;
 853         return false;
 854 }
 855
 856 static inline bool cxl_is_power9(void)
 857 {
 858         if (pvr_version_is(PVR_POWER9))
 859                 return true;
 860         return false;
 861 }
 862
 863 static inline bool cxl_is_power9_dd1(void)
 864 {
 865         if ((pvr_version_is(PVR_POWER9)) &&
 866             cpu_has_feature(CPU_FTR_POWER9_DD1))
 867                 return true;
 868         return false;
 869 }
 870
 871 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
 872                                 loff_t off, size_t count);
 873
 874 /* Internal functions wrapped in cxl_base to allow PHB to call them */
 875 bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu);
 876 void _cxl_pci_disable_device(struct pci_dev *dev);
 877 int _cxl_next_msi_hwirq(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
 878 int _cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
 879 void _cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
 880
 881 struct cxl_calls {
 882         void (*cxl_slbia)(struct mm_struct *mm);
 883         bool (*cxl_pci_associate_default_context)(struct pci_dev *dev, struct cxl_afu *afu);
 884         void (*cxl_pci_disable_device)(struct pci_dev *dev);
 885         int (*cxl_next_msi_hwirq)(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
 886         int (*cxl_cx4_setup_msi_irqs)(struct pci_dev *pdev, int nvec, int type);
 887         void (*cxl_cx4_teardown_msi_irqs)(struct pci_dev *pdev);
 888
 889         struct module *owner;
 890 };
 891 int register_cxl_calls(struct cxl_calls *calls);
 892 void unregister_cxl_calls(struct cxl_calls *calls);
 893 int cxl_update_properties(struct device_node *dn, struct property *new_prop);
 894
 895 void cxl_remove_adapter_nr(struct cxl *adapter);
 896
 897 void cxl_release_spa(struct cxl_afu *afu);
 898
 899 dev_t cxl_get_dev(void);
 900 int cxl_file_init(void);
 901 void cxl_file_exit(void);
 902 int cxl_register_adapter(struct cxl *adapter);
 903 int cxl_register_afu(struct cxl_afu *afu);
 904 int cxl_chardev_d_afu_add(struct cxl_afu *afu);
 905 int cxl_chardev_m_afu_add(struct cxl_afu *afu);
 906 int cxl_chardev_s_afu_add(struct cxl_afu *afu);
 907 void cxl_chardev_afu_remove(struct cxl_afu *afu);
 908
 909 void cxl_context_detach_all(struct cxl_afu *afu);
 910 void cxl_context_free(struct cxl_context *ctx);
 911 void cxl_context_detach(struct cxl_context *ctx);
 912
 913 int cxl_sysfs_adapter_add(struct cxl *adapter);
 914 void cxl_sysfs_adapter_remove(struct cxl *adapter);
 915 int cxl_sysfs_afu_add(struct cxl_afu *afu);
 916 void cxl_sysfs_afu_remove(struct cxl_afu *afu);
 917 int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
 918 void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
 919
 920 struct cxl *cxl_alloc_adapter(void);
 921 struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
 922 int cxl_afu_select_best_mode(struct cxl_afu *afu);
 923
 924 int cxl_native_register_psl_irq(struct cxl_afu *afu);
 925 void cxl_native_release_psl_irq(struct cxl_afu *afu);
 926 int cxl_native_register_psl_err_irq(struct cxl *adapter);
 927 void cxl_native_release_psl_err_irq(struct cxl *adapter);
 928 int cxl_native_register_serr_irq(struct cxl_afu *afu);
 929 void cxl_native_release_serr_irq(struct cxl_afu *afu);
 930 int afu_register_irqs(struct cxl_context *ctx, u32 count);
 931 void afu_release_irqs(struct cxl_context *ctx, void *cookie);
 932 void afu_irq_name_free(struct cxl_context *ctx);
 933
 934 int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
 935 int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
 936 int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu);
 937 int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu);
 938 int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
 939 int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
 940 void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx);
 941 void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx);
 942
 943 #ifdef CONFIG_DEBUG_FS
 944
 945 int cxl_debugfs_init(void);
 946 void cxl_debugfs_exit(void);
 947 int cxl_debugfs_adapter_add(struct cxl *adapter);
 948 void cxl_debugfs_adapter_remove(struct cxl *adapter);
 949 int cxl_debugfs_afu_add(struct cxl_afu *afu);
 950 void cxl_debugfs_afu_remove(struct cxl_afu *afu);
 951 void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter, struct dentry *dir);
 952 void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, struct dentry *dir);
 953 void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter, struct dentry *dir);
 954 void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir);
 955 void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir);
 956
 957 #else /* CONFIG_DEBUG_FS */
 958
 959 static inline int __init cxl_debugfs_init(void)
 960 {
 961         return 0;
 962 }
 963
 964 static inline void cxl_debugfs_exit(void)
 965 {
 966 }
 967
 968 static inline int cxl_debugfs_adapter_add(struct cxl *adapter)
 969 {
 970         return 0;
 971 }
 972
 973 static inline void cxl_debugfs_adapter_remove(struct cxl *adapter)
 974 {
 975 }
 976
 977 static inline int cxl_debugfs_afu_add(struct cxl_afu *afu)
 978 {
 979         return 0;
 980 }
 981
 982 static inline void cxl_debugfs_afu_remove(struct cxl_afu *afu)
 983 {
 984 }
 985
 986 static inline void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter,
 987                                                     struct dentry *dir)
 988 {
 989 }
 990
 991 static inline void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter,
 992                                                     struct dentry *dir)
 993 {
 994 }
 995
 996 static inline void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter,
 997                                                     struct dentry *dir)
 998 {
 999 }
1000
1001 static inline void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir)
1002 {
1003 }
1004
1005 static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir)
1006 {
1007 }
1008
1009 #endif /* CONFIG_DEBUG_FS */
1010
1011 void cxl_handle_fault(struct work_struct *work);
1012 void cxl_prefault(struct cxl_context *ctx, u64 wed);
1013 int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar);
1014
1015 struct cxl *get_cxl_adapter(int num);
1016 int cxl_alloc_sst(struct cxl_context *ctx);
1017 void cxl_dump_debug_buffer(void *addr, size_t size);
1018
1019 void init_cxl_native(void);
1020
1021 struct cxl_context *cxl_context_alloc(void);
1022 int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master);
1023 void cxl_context_set_mapping(struct cxl_context *ctx,
1024                         struct address_space *mapping);
1025 void cxl_context_free(struct cxl_context *ctx);
1026 int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
1027 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
1028                          irq_handler_t handler, void *cookie, const char *name);
1029 void cxl_unmap_irq(unsigned int virq, void *cookie);
1030 int __detach_context(struct cxl_context *ctx);
1031
1032 /*
1033  * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
1034  * in PAPR.
1035  * Field pid_tid is now 'reserved' because it's no more used on bare-metal.
1036  * On a guest environment, PSL_PID_An is located on the upper 32 bits and
1037  * PSL_TID_An register in the lower 32 bits.
1038  */
1039 struct cxl_irq_info {
1040         u64 dsisr;
1041         u64 dar;
1042         u64 dsr;
1043         u64 reserved;
1044         u64 afu_err;
1045         u64 errstat;
1046         u64 proc_handle;
1047         u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
1048 };
1049
1050 void cxl_assign_psn_space(struct cxl_context *ctx);
1051 int cxl_invalidate_all_psl9(struct cxl *adapter);
1052 int cxl_invalidate_all_psl8(struct cxl *adapter);
1053 irqreturn_t cxl_irq_psl9(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1054 irqreturn_t cxl_irq_psl8(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1055 irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
1056 int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
1057                         void *cookie, irq_hw_number_t *dest_hwirq,
1058                         unsigned int *dest_virq, const char *name);
1059
1060 int cxl_check_error(struct cxl_afu *afu);
1061 int cxl_afu_slbia(struct cxl_afu *afu);
1062 int cxl_data_cache_flush(struct cxl *adapter);
1063 int cxl_afu_disable(struct cxl_afu *afu);
1064 int cxl_psl_purge(struct cxl_afu *afu);
1065 int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
1066                           u32 *phb_index, u64 *capp_unit_id);
1067 int cxl_slot_is_switched(struct pci_dev *dev);
1068 int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg);
1069 u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9);
1070
1071 void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);
1072 void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx);
1073 void cxl_native_err_irq_dump_regs_psl8(struct cxl *adapter);
1074 void cxl_native_err_irq_dump_regs_psl9(struct cxl *adapter);
1075 int cxl_pci_vphb_add(struct cxl_afu *afu);
1076 void cxl_pci_vphb_remove(struct cxl_afu *afu);
1077 void cxl_release_mapping(struct cxl_context *ctx);
1078
1079 extern struct pci_driver cxl_pci_driver;
1080 extern struct platform_driver cxl_of_driver;
1081 int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
1082
1083 int afu_open(struct inode *inode, struct file *file);
1084 int afu_release(struct inode *inode, struct file *file);
1085 long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
1086 int afu_mmap(struct file *file, struct vm_area_struct *vm);
1087 __poll_t afu_poll(struct file *file, struct poll_table_struct *poll);
1088 ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
1089 extern const struct file_operations afu_fops;
1090
1091 struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
1092 void cxl_guest_remove_adapter(struct cxl *adapter);
1093 int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
1094 int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
1095 ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
1096 ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
1097 int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
1098 void cxl_guest_remove_afu(struct cxl_afu *afu);
1099 int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
1100 int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
1101 int cxl_guest_add_chardev(struct cxl *adapter);
1102 void cxl_guest_remove_chardev(struct cxl *adapter);
1103 void cxl_guest_reload_module(struct cxl *adapter);
1104 int cxl_of_probe(struct platform_device *pdev);
1105
1106 struct cxl_backend_ops {
1107         struct module *module;
1108         int (*adapter_reset)(struct cxl *adapter);
1109         int (*alloc_one_irq)(struct cxl *adapter);
1110         void (*release_one_irq)(struct cxl *adapter, int hwirq);
1111         int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
1112                                 struct cxl *adapter, unsigned int num);
1113         void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
1114                                 struct cxl *adapter);
1115         int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
1116                         unsigned int virq);
1117         irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
1118                                         u64 dsisr, u64 errstat);
1119         irqreturn_t (*psl_interrupt)(int irq, void *data);
1120         int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
1121         void (*irq_wait)(struct cxl_context *ctx);
1122         int (*attach_process)(struct cxl_context *ctx, bool kernel,
1123                         u64 wed, u64 amr);
1124         int (*detach_process)(struct cxl_context *ctx);
1125         void (*update_ivtes)(struct cxl_context *ctx);
1126         bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
1127         bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
1128         void (*release_afu)(struct device *dev);
1129         ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
1130                                 loff_t off, size_t count);
1131         int (*afu_check_and_enable)(struct cxl_afu *afu);
1132         int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
1133         int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
1134         int (*afu_reset)(struct cxl_afu *afu);
1135         int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
1136         int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
1137         int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
1138         int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
1139         int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
1140         int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
1141         int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
1142         ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
1143 };
1144 extern const struct cxl_backend_ops cxl_native_ops;
1145 extern const struct cxl_backend_ops cxl_guest_ops;
1146 extern const struct cxl_backend_ops *cxl_ops;
1147
1148 /* check if the given pci_dev is on the the cxl vphb bus */
1149 bool cxl_pci_is_vphb_device(struct pci_dev *dev);
1150
1151 /* decode AFU error bits in the PSL register PSL_SERR_An */
1152 void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
1153
1154 /*
1155  * Increments the number of attached contexts on an adapter.
1156  * In case an adapter_context_lock is taken the return -EBUSY.
1157  */
1158 int cxl_adapter_context_get(struct cxl *adapter);
1159
1160 /* Decrements the number of attached contexts on an adapter */
1161 void cxl_adapter_context_put(struct cxl *adapter);
1162
1163 /* If no active contexts then prevents contexts from being attached */
1164 int cxl_adapter_context_lock(struct cxl *adapter);
1165
1166 /* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
1167 void cxl_adapter_context_unlock(struct cxl *adapter);
1168
1169 /* Increases the reference count to "struct mm_struct" */
1170 void cxl_context_mm_count_get(struct cxl_context *ctx);
1171
1172 /* Decrements the reference count to "struct mm_struct" */
1173 void cxl_context_mm_count_put(struct cxl_context *ctx);
1174
1175 #endif