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Linux 4.16.11
[linux/fpc-iii.git] / drivers / misc / cxl / pci.c
blob758842f65a1b372ea8aecf48fe8a58d738dba0d7
1 /*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10 #include <linux/pci_regs.h>
11 #include <linux/pci_ids.h>
12 #include <linux/device.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/sort.h>
17 #include <linux/pci.h>
18 #include <linux/of.h>
19 #include <linux/delay.h>
20 #include <asm/opal.h>
21 #include <asm/msi_bitmap.h>
22 #include <asm/pnv-pci.h>
23 #include <asm/io.h>
24 #include <asm/reg.h>
25
26 #include "cxl.h"
27 #include <misc/cxl.h>
28
29
30 #define CXL_PCI_VSEC_ID 0x1280
31 #define CXL_VSEC_MIN_SIZE 0x80
32
33 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
34 { \
35 pci_read_config_word(dev, vsec + 0x6, dest); \
36 *dest >>= 4; \
37 }
38 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
39 pci_read_config_byte(dev, vsec + 0x8, dest)
40
41 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
42 pci_read_config_byte(dev, vsec + 0x9, dest)
43 #define CXL_STATUS_SECOND_PORT 0x80
44 #define CXL_STATUS_MSI_X_FULL 0x40
45 #define CXL_STATUS_MSI_X_SINGLE 0x20
46 #define CXL_STATUS_FLASH_RW 0x08
47 #define CXL_STATUS_FLASH_RO 0x04
48 #define CXL_STATUS_LOADABLE_AFU 0x02
49 #define CXL_STATUS_LOADABLE_PSL 0x01
50 /* If we see these features we won't try to use the card */
51 #define CXL_UNSUPPORTED_FEATURES \
52 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
53
54 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
55 pci_read_config_byte(dev, vsec + 0xa, dest)
56 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
57 pci_write_config_byte(dev, vsec + 0xa, val)
58 #define CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, vsec, val) \
59 pci_bus_write_config_byte(bus, devfn, vsec + 0xa, val)
60 #define CXL_VSEC_PROTOCOL_MASK 0xe0
61 #define CXL_VSEC_PROTOCOL_1024TB 0x80
62 #define CXL_VSEC_PROTOCOL_512TB 0x40
63 #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8/9 uses this */
64 #define CXL_VSEC_PROTOCOL_ENABLE 0x01
65
66 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
67 pci_read_config_word(dev, vsec + 0xc, dest)
68 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
69 pci_read_config_byte(dev, vsec + 0xe, dest)
70 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
71 pci_read_config_byte(dev, vsec + 0xf, dest)
72 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
73 pci_read_config_word(dev, vsec + 0x10, dest)
74
75 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
76 pci_read_config_byte(dev, vsec + 0x13, dest)
77 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
78 pci_write_config_byte(dev, vsec + 0x13, val)
79 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
80 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
81 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
82
83 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
84 pci_read_config_dword(dev, vsec + 0x20, dest)
85 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
86 pci_read_config_dword(dev, vsec + 0x24, dest)
87 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
88 pci_read_config_dword(dev, vsec + 0x28, dest)
89 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
90 pci_read_config_dword(dev, vsec + 0x2c, dest)
91
92
93 /* This works a little different than the p1/p2 register accesses to make it
94 * easier to pull out individual fields */
95 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
96 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
97 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
98 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
99
100 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
101 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
102 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
103 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
104 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
105 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
106 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
107 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
108 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
109 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
110 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
111 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
112 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
113 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
114 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
115 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
116 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
117 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
118 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
119 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
120
121 static const struct pci_device_id cxl_pci_tbl[] = {
122 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
123 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
124 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
125 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
126 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), },
127 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), },
128 { }
129 };
130 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
131
132
133 /*
134 * Mostly using these wrappers to avoid confusion:
135 * priv 1 is BAR2, while priv 2 is BAR0
136 */
137 static inline resource_size_t p1_base(struct pci_dev *dev)
138 {
139 return pci_resource_start(dev, 2);
140 }
141
142 static inline resource_size_t p1_size(struct pci_dev *dev)
143 {
144 return pci_resource_len(dev, 2);
145 }
146
147 static inline resource_size_t p2_base(struct pci_dev *dev)
148 {
149 return pci_resource_start(dev, 0);
150 }
151
152 static inline resource_size_t p2_size(struct pci_dev *dev)
153 {
154 return pci_resource_len(dev, 0);
155 }
156
157 static int find_cxl_vsec(struct pci_dev *dev)
158 {
159 int vsec = 0;
160 u16 val;
161
162 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
163 pci_read_config_word(dev, vsec + 0x4, &val);
164 if (val == CXL_PCI_VSEC_ID)
165 return vsec;
166 }
167 return 0;
168
169 }
170
171 static void dump_cxl_config_space(struct pci_dev *dev)
172 {
173 int vsec;
174 u32 val;
175
176 dev_info(&dev->dev, "dump_cxl_config_space\n");
177
178 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
179 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
181 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
183 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
184 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
185 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
186 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
187 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
188 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
189 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
190
191 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
192 p1_base(dev), p1_size(dev));
193 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
194 p2_base(dev), p2_size(dev));
195 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
196 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
197
198 if (!(vsec = find_cxl_vsec(dev)))
199 return;
200
201 #define show_reg(name, what) \
202 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
203
204 pci_read_config_dword(dev, vsec + 0x0, &val);
205 show_reg("Cap ID", (val >> 0) & 0xffff);
206 show_reg("Cap Ver", (val >> 16) & 0xf);
207 show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
208 pci_read_config_dword(dev, vsec + 0x4, &val);
209 show_reg("VSEC ID", (val >> 0) & 0xffff);
210 show_reg("VSEC Rev", (val >> 16) & 0xf);
211 show_reg("VSEC Length", (val >> 20) & 0xfff);
212 pci_read_config_dword(dev, vsec + 0x8, &val);
213 show_reg("Num AFUs", (val >> 0) & 0xff);
214 show_reg("Status", (val >> 8) & 0xff);
215 show_reg("Mode Control", (val >> 16) & 0xff);
216 show_reg("Reserved", (val >> 24) & 0xff);
217 pci_read_config_dword(dev, vsec + 0xc, &val);
218 show_reg("PSL Rev", (val >> 0) & 0xffff);
219 show_reg("CAIA Ver", (val >> 16) & 0xffff);
220 pci_read_config_dword(dev, vsec + 0x10, &val);
221 show_reg("Base Image Rev", (val >> 0) & 0xffff);
222 show_reg("Reserved", (val >> 16) & 0x0fff);
223 show_reg("Image Control", (val >> 28) & 0x3);
224 show_reg("Reserved", (val >> 30) & 0x1);
225 show_reg("Image Loaded", (val >> 31) & 0x1);
226
227 pci_read_config_dword(dev, vsec + 0x14, &val);
228 show_reg("Reserved", val);
229 pci_read_config_dword(dev, vsec + 0x18, &val);
230 show_reg("Reserved", val);
231 pci_read_config_dword(dev, vsec + 0x1c, &val);
232 show_reg("Reserved", val);
233
234 pci_read_config_dword(dev, vsec + 0x20, &val);
235 show_reg("AFU Descriptor Offset", val);
236 pci_read_config_dword(dev, vsec + 0x24, &val);
237 show_reg("AFU Descriptor Size", val);
238 pci_read_config_dword(dev, vsec + 0x28, &val);
239 show_reg("Problem State Offset", val);
240 pci_read_config_dword(dev, vsec + 0x2c, &val);
241 show_reg("Problem State Size", val);
242
243 pci_read_config_dword(dev, vsec + 0x30, &val);
244 show_reg("Reserved", val);
245 pci_read_config_dword(dev, vsec + 0x34, &val);
246 show_reg("Reserved", val);
247 pci_read_config_dword(dev, vsec + 0x38, &val);
248 show_reg("Reserved", val);
249 pci_read_config_dword(dev, vsec + 0x3c, &val);
250 show_reg("Reserved", val);
251
252 pci_read_config_dword(dev, vsec + 0x40, &val);
253 show_reg("PSL Programming Port", val);
254 pci_read_config_dword(dev, vsec + 0x44, &val);
255 show_reg("PSL Programming Control", val);
256
257 pci_read_config_dword(dev, vsec + 0x48, &val);
258 show_reg("Reserved", val);
259 pci_read_config_dword(dev, vsec + 0x4c, &val);
260 show_reg("Reserved", val);
261
262 pci_read_config_dword(dev, vsec + 0x50, &val);
263 show_reg("Flash Address Register", val);
264 pci_read_config_dword(dev, vsec + 0x54, &val);
265 show_reg("Flash Size Register", val);
266 pci_read_config_dword(dev, vsec + 0x58, &val);
267 show_reg("Flash Status/Control Register", val);
268 pci_read_config_dword(dev, vsec + 0x58, &val);
269 show_reg("Flash Data Port", val);
270
271 #undef show_reg
272 }
273
274 static void dump_afu_descriptor(struct cxl_afu *afu)
275 {
276 u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
277 int i;
278
279 #define show_reg(name, what) \
280 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
281
282 val = AFUD_READ_INFO(afu);
283 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
284 show_reg("num_of_processes", AFUD_NUM_PROCS(val));
285 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
286 show_reg("req_prog_mode", val & 0xffffULL);
287 afu_cr_num = AFUD_NUM_CRS(val);
288
289 val = AFUD_READ(afu, 0x8);
290 show_reg("Reserved", val);
291 val = AFUD_READ(afu, 0x10);
292 show_reg("Reserved", val);
293 val = AFUD_READ(afu, 0x18);
294 show_reg("Reserved", val);
295
296 val = AFUD_READ_CR(afu);
297 show_reg("Reserved", (val >> (63-7)) & 0xff);
298 show_reg("AFU_CR_len", AFUD_CR_LEN(val));
299 afu_cr_len = AFUD_CR_LEN(val) * 256;
300
301 val = AFUD_READ_CR_OFF(afu);
302 afu_cr_off = val;
303 show_reg("AFU_CR_offset", val);
304
305 val = AFUD_READ_PPPSA(afu);
306 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
307 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
308
309 val = AFUD_READ_PPPSA_OFF(afu);
310 show_reg("PerProcessPSA_offset", val);
311
312 val = AFUD_READ_EB(afu);
313 show_reg("Reserved", (val >> (63-7)) & 0xff);
314 show_reg("AFU_EB_len", AFUD_EB_LEN(val));
315
316 val = AFUD_READ_EB_OFF(afu);
317 show_reg("AFU_EB_offset", val);
318
319 for (i = 0; i < afu_cr_num; i++) {
320 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
321 show_reg("CR Vendor", val & 0xffff);
322 show_reg("CR Device", (val >> 16) & 0xffff);
323 }
324 #undef show_reg
325 }
326
327 #define P8_CAPP_UNIT0_ID 0xBA
328 #define P8_CAPP_UNIT1_ID 0XBE
329 #define P9_CAPP_UNIT0_ID 0xC0
330 #define P9_CAPP_UNIT1_ID 0xE0
331
332 static int get_phb_index(struct device_node *np, u32 *phb_index)
333 {
334 if (of_property_read_u32(np, "ibm,phb-index", phb_index))
335 return -ENODEV;
336 return 0;
337 }
338
339 static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
340 {
341 /*
342 * POWER 8:
343 * - For chips other than POWER8NVL, we only have CAPP 0,
344 * irrespective of which PHB is used.
345 * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
346 * CAPP 1 is attached to PHB1.
347 */
348 if (cxl_is_power8()) {
349 if (!pvr_version_is(PVR_POWER8NVL))
350 return P8_CAPP_UNIT0_ID;
351
352 if (phb_index == 0)
353 return P8_CAPP_UNIT0_ID;
354
355 if (phb_index == 1)
356 return P8_CAPP_UNIT1_ID;
357 }
358
359 /*
360 * POWER 9:
361 * PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
362 * PEC1 (PHB1 - PHB2). No capi mode
363 * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
364 */
365 if (cxl_is_power9()) {
366 if (phb_index == 0)
367 return P9_CAPP_UNIT0_ID;
368
369 if (phb_index == 3)
370 return P9_CAPP_UNIT1_ID;
371 }
372
373 return 0;
374 }
375
376 int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
377 u32 *phb_index, u64 *capp_unit_id)
378 {
379 int rc;
380 struct device_node *np;
381 const __be32 *prop;
382
383 if (!(np = pnv_pci_get_phb_node(dev)))
384 return -ENODEV;
385
386 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
387 np = of_get_next_parent(np);
388 if (!np)
389 return -ENODEV;
390
391 *chipid = be32_to_cpup(prop);
392
393 rc = get_phb_index(np, phb_index);
394 if (rc) {
395 pr_err("cxl: invalid phb index\n");
396 return rc;
397 }
398
399 *capp_unit_id = get_capp_unit_id(np, *phb_index);
400 of_node_put(np);
401 if (!*capp_unit_id) {
402 pr_err("cxl: invalid capp unit id (phb_index: %d)\n",
403 *phb_index);
404 return -ENODEV;
405 }
406
407 return 0;
408 }
409
410 int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg)
411 {
412 u64 xsl_dsnctl;
413
414 /*
415 * CAPI Identifier bits [0:7]
416 * bit 61:60 MSI bits --> 0
417 * bit 59 TVT selector --> 0
418 */
419
420 /*
421 * Tell XSL where to route data to.
422 * The field chipid should match the PHB CAPI_CMPM register
423 */
424 xsl_dsnctl = ((u64)0x2 << (63-7)); /* Bit 57 */
425 xsl_dsnctl |= (capp_unit_id << (63-15));
426
427 /* nMMU_ID Defaults to: b’000001001’*/
428 xsl_dsnctl |= ((u64)0x09 << (63-28));
429
430 if (!(cxl_is_power9_dd1())) {
431 /*
432 * Used to identify CAPI packets which should be sorted into
433 * the Non-Blocking queues by the PHB. This field should match
434 * the PHB PBL_NBW_CMPM register
435 * nbwind=0x03, bits [57:58], must include capi indicator.
436 * Not supported on P9 DD1.
437 */
438 xsl_dsnctl |= ((u64)0x03 << (63-47));
439
440 /*
441 * Upper 16b address bits of ASB_Notify messages sent to the
442 * system. Need to match the PHB’s ASN Compare/Mask Register.
443 * Not supported on P9 DD1.
444 */
445 xsl_dsnctl |= ((u64)0x04 << (63-55));
446 }
447
448 *reg = xsl_dsnctl;
449 return 0;
450 }
451
452 static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
453 struct pci_dev *dev)
454 {
455 u64 xsl_dsnctl, psl_fircntl;
456 u64 chipid;
457 u32 phb_index;
458 u64 capp_unit_id;
459 int rc;
460
461 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
462 if (rc)
463 return rc;
464
465 rc = cxl_get_xsl9_dsnctl(capp_unit_id, &xsl_dsnctl);
466 if (rc)
467 return rc;
468
469 cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
470
471 /* Set fir_cntl to recommended value for production env */
472 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
473 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
474 psl_fircntl |= 0x1ULL; /* ce_thresh */
475 cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
476
477 /* Setup the PSL to transmit packets on the PCIe before the
478 * CAPP is enabled
479 */
480 cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000002A10ULL);
481
482 /*
483 * A response to an ASB_Notify request is returned by the
484 * system as an MMIO write to the address defined in
485 * the PSL_TNR_ADDR register.
486 * keep the Reset Value: 0x00020000E0000000
487 */
488
489 /* Enable XSL rty limit */
490 cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);
491
492 /* Change XSL_INV dummy read threshold */
493 cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);
494
495 if (phb_index == 3) {
496 /* disable machines 31-47 and 20-27 for DMA */
497 cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);
498 }
499
500 /* Snoop machines */
501 cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);
502
503 if (cxl_is_power9_dd1()) {
504 /* Disabling deadlock counter CAR */
505 cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);
506 } else
507 cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x4000000000000000ULL);
508
509 return 0;
510 }
511
512 static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
513 {
514 u64 psl_dsnctl, psl_fircntl;
515 u64 chipid;
516 u32 phb_index;
517 u64 capp_unit_id;
518 int rc;
519
520 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
521 if (rc)
522 return rc;
523
524 psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
525 psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
526 /* Tell PSL where to route data to */
527 psl_dsnctl |= (chipid << (63-5));
528 psl_dsnctl |= (capp_unit_id << (63-13));
529
530 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
531 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
532 /* snoop write mask */
533 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
534 /* set fir_cntl to recommended value for production env */
535 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
536 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
537 psl_fircntl |= 0x1ULL; /* ce_thresh */
538 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
539 /* for debugging with trace arrays */
540 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
541
542 return 0;
543 }
544
545 static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_dev *dev)
546 {
547 u64 xsl_dsnctl;
548 u64 chipid;
549 u32 phb_index;
550 u64 capp_unit_id;
551 int rc;
552
553 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
554 if (rc)
555 return rc;
556
557 /* Tell XSL where to route data to */
558 xsl_dsnctl = 0x0000600000000000ULL | (chipid << (63-5));
559 xsl_dsnctl |= (capp_unit_id << (63-13));
560 cxl_p1_write(adapter, CXL_XSL_DSNCTL, xsl_dsnctl);
561
562 return 0;
563 }
564
565 /* PSL & XSL */
566 #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
567 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
568 /* For the PSL this is a multiple for 0 < n <= 7: */
569 #define PSL_2048_250MHZ_CYCLES 1
570
571 static void write_timebase_ctrl_psl9(struct cxl *adapter)
572 {
573 cxl_p1_write(adapter, CXL_PSL9_TB_CTLSTAT,
574 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
575 }
576
577 static void write_timebase_ctrl_psl8(struct cxl *adapter)
578 {
579 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
580 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
581 }
582
583 /* XSL */
584 #define TBSYNC_ENA (1ULL << 63)
585 /* For the XSL this is 2**n * 2000 clocks for 0 < n <= 6: */
586 #define XSL_2000_CLOCKS 1
587 #define XSL_4000_CLOCKS 2
588 #define XSL_8000_CLOCKS 3
589
590 static void write_timebase_ctrl_xsl(struct cxl *adapter)
591 {
592 cxl_p1_write(adapter, CXL_XSL_TB_CTLSTAT,
593 TBSYNC_ENA |
594 TBSYNC_CAL(3) |
595 TBSYNC_CNT(XSL_4000_CLOCKS));
596 }
597
598 static u64 timebase_read_psl9(struct cxl *adapter)
599 {
600 return cxl_p1_read(adapter, CXL_PSL9_Timebase);
601 }
602
603 static u64 timebase_read_psl8(struct cxl *adapter)
604 {
605 return cxl_p1_read(adapter, CXL_PSL_Timebase);
606 }
607
608 static u64 timebase_read_xsl(struct cxl *adapter)
609 {
610 return cxl_p1_read(adapter, CXL_XSL_Timebase);
611 }
612
613 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
614 {
615 u64 psl_tb;
616 int delta;
617 unsigned int retry = 0;
618 struct device_node *np;
619
620 adapter->psl_timebase_synced = false;
621
622 if (!(np = pnv_pci_get_phb_node(dev)))
623 return;
624
625 /* Do not fail when CAPP timebase sync is not supported by OPAL */
626 of_node_get(np);
627 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
628 of_node_put(np);
629 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
630 return;
631 }
632 of_node_put(np);
633
634 /*
635 * Setup PSL Timebase Control and Status register
636 * with the recommended Timebase Sync Count value
637 */
638 adapter->native->sl_ops->write_timebase_ctrl(adapter);
639
640 /* Enable PSL Timebase */
641 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
642 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
643
644 /* Wait until CORE TB and PSL TB difference <= 16usecs */
645 do {
646 msleep(1);
647 if (retry++ > 5) {
648 dev_info(&dev->dev, "PSL timebase can't synchronize\n");
649 return;
650 }
651 psl_tb = adapter->native->sl_ops->timebase_read(adapter);
652 delta = mftb() - psl_tb;
653 if (delta < 0)
654 delta = -delta;
655 } while (tb_to_ns(delta) > 16000);
656
657 adapter->psl_timebase_synced = true;
658 return;
659 }
660
661 static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
662 {
663 return 0;
664 }
665
666 static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
667 {
668 /* read/write masks for this slice */
669 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
670 /* APC read/write masks for this slice */
671 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
672 /* for debugging with trace arrays */
673 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
674 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
675
676 return 0;
677 }
678
679 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
680 unsigned int virq)
681 {
682 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
683
684 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
685 }
686
687 int cxl_update_image_control(struct cxl *adapter)
688 {
689 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
690 int rc;
691 int vsec;
692 u8 image_state;
693
694 if (!(vsec = find_cxl_vsec(dev))) {
695 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
696 return -ENODEV;
697 }
698
699 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
700 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
701 return rc;
702 }
703
704 if (adapter->perst_loads_image)
705 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
706 else
707 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
708
709 if (adapter->perst_select_user)
710 image_state |= CXL_VSEC_PERST_SELECT_USER;
711 else
712 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
713
714 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
715 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
716 return rc;
717 }
718
719 return 0;
720 }
721
722 int cxl_pci_alloc_one_irq(struct cxl *adapter)
723 {
724 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
725
726 return pnv_cxl_alloc_hwirqs(dev, 1);
727 }
728
729 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
730 {
731 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
732
733 return pnv_cxl_release_hwirqs(dev, hwirq, 1);
734 }
735
736 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
737 struct cxl *adapter, unsigned int num)
738 {
739 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
740
741 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
742 }
743
744 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
745 struct cxl *adapter)
746 {
747 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
748
749 pnv_cxl_release_hwirq_ranges(irqs, dev);
750 }
751
752 static int setup_cxl_bars(struct pci_dev *dev)
753 {
754 /* Safety check in case we get backported to < 3.17 without M64 */
755 if ((p1_base(dev) < 0x100000000ULL) ||
756 (p2_base(dev) < 0x100000000ULL)) {
757 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
758 return -ENODEV;
759 }
760
761 /*
762 * BAR 4/5 has a special meaning for CXL and must be programmed with a
763 * special value corresponding to the CXL protocol address range.
764 * For POWER 8/9 that means bits 48:49 must be set to 10
765 */
766 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
767 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
768
769 return 0;
770 }
771
772 #ifdef CONFIG_CXL_BIMODAL
773
774 struct cxl_switch_work {
775 struct pci_dev *dev;
776 struct work_struct work;
777 int vsec;
778 int mode;
779 };
780
781 static void switch_card_to_cxl(struct work_struct *work)
782 {
783 struct cxl_switch_work *switch_work =
784 container_of(work, struct cxl_switch_work, work);
785 struct pci_dev *dev = switch_work->dev;
786 struct pci_bus *bus = dev->bus;
787 struct pci_controller *hose = pci_bus_to_host(bus);
788 struct pci_dev *bridge;
789 struct pnv_php_slot *php_slot;
790 unsigned int devfn;
791 u8 val;
792 int rc;
793
794 dev_info(&bus->dev, "cxl: Preparing for mode switch...\n");
795 bridge = list_first_entry_or_null(&hose->bus->devices, struct pci_dev,
796 bus_list);
797 if (!bridge) {
798 dev_WARN(&bus->dev, "cxl: Couldn't find root port!\n");
799 goto err_dev_put;
800 }
801
802 php_slot = pnv_php_find_slot(pci_device_to_OF_node(bridge));
803 if (!php_slot) {
804 dev_err(&bus->dev, "cxl: Failed to find slot hotplug "
805 "information. You may need to upgrade "
806 "skiboot. Aborting.\n");
807 goto err_dev_put;
808 }
809
810 rc = CXL_READ_VSEC_MODE_CONTROL(dev, switch_work->vsec, &val);
811 if (rc) {
812 dev_err(&bus->dev, "cxl: Failed to read CAPI mode control: %i\n", rc);
813 goto err_dev_put;
814 }
815 devfn = dev->devfn;
816
817 /* Release the reference obtained in cxl_check_and_switch_mode() */
818 pci_dev_put(dev);
819
820 dev_dbg(&bus->dev, "cxl: Removing PCI devices from kernel\n");
821 pci_lock_rescan_remove();
822 pci_hp_remove_devices(bridge->subordinate);
823 pci_unlock_rescan_remove();
824
825 /* Switch the CXL protocol on the card */
826 if (switch_work->mode == CXL_BIMODE_CXL) {
827 dev_info(&bus->dev, "cxl: Switching card to CXL mode\n");
828 val &= ~CXL_VSEC_PROTOCOL_MASK;
829 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
830 rc = pnv_cxl_enable_phb_kernel_api(hose, true);
831 if (rc) {
832 dev_err(&bus->dev, "cxl: Failed to enable kernel API"
833 " on real PHB, aborting\n");
834 goto err_free_work;
835 }
836 } else {
837 dev_WARN(&bus->dev, "cxl: Switching card to PCI mode not supported!\n");
838 goto err_free_work;
839 }
840
841 rc = CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, switch_work->vsec, val);
842 if (rc) {
843 dev_err(&bus->dev, "cxl: Failed to configure CXL protocol: %i\n", rc);
844 goto err_free_work;
845 }
846
847 /*
848 * The CAIA spec (v1.1, Section 10.6 Bi-modal Device Support) states
849 * we must wait 100ms after this mode switch before touching PCIe config
850 * space.
851 */
852 msleep(100);
853
854 /*
855 * Hot reset to cause the card to come back in cxl mode. A
856 * OPAL_RESET_PCI_LINK would be sufficient, but currently lacks support
857 * in skiboot, so we use a hot reset instead.
858 *
859 * We call pci_set_pcie_reset_state() on the bridge, as a CAPI card is
860 * guaranteed to sit directly under the root port, and setting the reset
861 * state on a device directly under the root port is equivalent to doing
862 * it on the root port iself.
863 */
864 dev_info(&bus->dev, "cxl: Configuration write complete, resetting card\n");
865 pci_set_pcie_reset_state(bridge, pcie_hot_reset);
866 pci_set_pcie_reset_state(bridge, pcie_deassert_reset);
867
868 dev_dbg(&bus->dev, "cxl: Offlining slot\n");
869 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_OFFLINE);
870 if (rc) {
871 dev_err(&bus->dev, "cxl: OPAL offlining call failed: %i\n", rc);
872 goto err_free_work;
873 }
874
875 dev_dbg(&bus->dev, "cxl: Onlining and probing slot\n");
876 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_ONLINE);
877 if (rc) {
878 dev_err(&bus->dev, "cxl: OPAL onlining call failed: %i\n", rc);
879 goto err_free_work;
880 }
881
882 pci_lock_rescan_remove();
883 pci_hp_add_devices(bridge->subordinate);
884 pci_unlock_rescan_remove();
885
886 dev_info(&bus->dev, "cxl: CAPI mode switch completed\n");
887 kfree(switch_work);
888 return;
889
890 err_dev_put:
891 /* Release the reference obtained in cxl_check_and_switch_mode() */
892 pci_dev_put(dev);
893 err_free_work:
894 kfree(switch_work);
895 }
896
897 int cxl_check_and_switch_mode(struct pci_dev *dev, int mode, int vsec)
898 {
899 struct cxl_switch_work *work;
900 u8 val;
901 int rc;
902
903 if (!cpu_has_feature(CPU_FTR_HVMODE))
904 return -ENODEV;
905
906 if (!vsec) {
907 vsec = find_cxl_vsec(dev);
908 if (!vsec) {
909 dev_info(&dev->dev, "CXL VSEC not found\n");
910 return -ENODEV;
911 }
912 }
913
914 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
915 if (rc) {
916 dev_err(&dev->dev, "Failed to read current mode control: %i", rc);
917 return rc;
918 }
919
920 if (mode == CXL_BIMODE_PCI) {
921 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
922 dev_info(&dev->dev, "Card is already in PCI mode\n");
923 return 0;
924 }
925 /*
926 * TODO: Before it's safe to switch the card back to PCI mode
927 * we need to disable the CAPP and make sure any cachelines the
928 * card holds have been flushed out. Needs skiboot support.
929 */
930 dev_WARN(&dev->dev, "CXL mode switch to PCI unsupported!\n");
931 return -EIO;
932 }
933
934 if (val & CXL_VSEC_PROTOCOL_ENABLE) {
935 dev_info(&dev->dev, "Card is already in CXL mode\n");
936 return 0;
937 }
938
939 dev_info(&dev->dev, "Card is in PCI mode, scheduling kernel thread "
940 "to switch to CXL mode\n");
941
942 work = kmalloc(sizeof(struct cxl_switch_work), GFP_KERNEL);
943 if (!work)
944 return -ENOMEM;
945
946 pci_dev_get(dev);
947 work->dev = dev;
948 work->vsec = vsec;
949 work->mode = mode;
950 INIT_WORK(&work->work, switch_card_to_cxl);
951
952 schedule_work(&work->work);
953
954 /*
955 * We return a failure now to abort the driver init. Once the
956 * link has been cycled and the card is in cxl mode we will
957 * come back (possibly using the generic cxl driver), but
958 * return success as the card should then be in cxl mode.
959 *
960 * TODO: What if the card comes back in PCI mode even after
961 * the switch? Don't want to spin endlessly.
962 */
963 return -EBUSY;
964 }
965 EXPORT_SYMBOL_GPL(cxl_check_and_switch_mode);
966
967 #endif /* CONFIG_CXL_BIMODAL */
968
969 static int setup_cxl_protocol_area(struct pci_dev *dev)
970 {
971 u8 val;
972 int rc;
973 int vsec = find_cxl_vsec(dev);
974
975 if (!vsec) {
976 dev_info(&dev->dev, "CXL VSEC not found\n");
977 return -ENODEV;
978 }
979
980 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
981 if (rc) {
982 dev_err(&dev->dev, "Failed to read current mode control: %i\n", rc);
983 return rc;
984 }
985
986 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
987 dev_err(&dev->dev, "Card not in CAPI mode!\n");
988 return -EIO;
989 }
990
991 if ((val & CXL_VSEC_PROTOCOL_MASK) != CXL_VSEC_PROTOCOL_256TB) {
992 val &= ~CXL_VSEC_PROTOCOL_MASK;
993 val |= CXL_VSEC_PROTOCOL_256TB;
994 rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val);
995 if (rc) {
996 dev_err(&dev->dev, "Failed to set CXL protocol area: %i\n", rc);
997 return rc;
998 }
999 }
1000
1001 return 0;
1002 }
1003
1004 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1005 {
1006 u64 p1n_base, p2n_base, afu_desc;
1007 const u64 p1n_size = 0x100;
1008 const u64 p2n_size = 0x1000;
1009
1010 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
1011 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
1012 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
1013 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
1014
1015 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
1016 goto err;
1017 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
1018 goto err1;
1019 if (afu_desc) {
1020 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
1021 goto err2;
1022 }
1023
1024 return 0;
1025 err2:
1026 iounmap(afu->p2n_mmio);
1027 err1:
1028 iounmap(afu->native->p1n_mmio);
1029 err:
1030 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
1031 return -ENOMEM;
1032 }
1033
1034 static void pci_unmap_slice_regs(struct cxl_afu *afu)
1035 {
1036 if (afu->p2n_mmio) {
1037 iounmap(afu->p2n_mmio);
1038 afu->p2n_mmio = NULL;
1039 }
1040 if (afu->native->p1n_mmio) {
1041 iounmap(afu->native->p1n_mmio);
1042 afu->native->p1n_mmio = NULL;
1043 }
1044 if (afu->native->afu_desc_mmio) {
1045 iounmap(afu->native->afu_desc_mmio);
1046 afu->native->afu_desc_mmio = NULL;
1047 }
1048 }
1049
1050 void cxl_pci_release_afu(struct device *dev)
1051 {
1052 struct cxl_afu *afu = to_cxl_afu(dev);
1053
1054 pr_devel("%s\n", __func__);
1055
1056 idr_destroy(&afu->contexts_idr);
1057 cxl_release_spa(afu);
1058
1059 kfree(afu->native);
1060 kfree(afu);
1061 }
1062
1063 /* Expects AFU struct to have recently been zeroed out */
1064 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
1065 {
1066 u64 val;
1067
1068 val = AFUD_READ_INFO(afu);
1069 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
1070 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
1071 afu->crs_num = AFUD_NUM_CRS(val);
1072
1073 if (AFUD_AFU_DIRECTED(val))
1074 afu->modes_supported |= CXL_MODE_DIRECTED;
1075 if (AFUD_DEDICATED_PROCESS(val))
1076 afu->modes_supported |= CXL_MODE_DEDICATED;
1077 if (AFUD_TIME_SLICED(val))
1078 afu->modes_supported |= CXL_MODE_TIME_SLICED;
1079
1080 val = AFUD_READ_PPPSA(afu);
1081 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
1082 afu->psa = AFUD_PPPSA_PSA(val);
1083 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
1084 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
1085
1086 val = AFUD_READ_CR(afu);
1087 afu->crs_len = AFUD_CR_LEN(val) * 256;
1088 afu->crs_offset = AFUD_READ_CR_OFF(afu);
1089
1090
1091 /* eb_len is in multiple of 4K */
1092 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
1093 afu->eb_offset = AFUD_READ_EB_OFF(afu);
1094
1095 /* eb_off is 4K aligned so lower 12 bits are always zero */
1096 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
1097 dev_warn(&afu->dev,
1098 "Invalid AFU error buffer offset %Lx\n",
1099 afu->eb_offset);
1100 dev_info(&afu->dev,
1101 "Ignoring AFU error buffer in the descriptor\n");
1102 /* indicate that no afu buffer exists */
1103 afu->eb_len = 0;
1104 }
1105
1106 return 0;
1107 }
1108
1109 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
1110 {
1111 int i, rc;
1112 u32 val;
1113
1114 if (afu->psa && afu->adapter->ps_size <
1115 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
1116 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
1117 return -ENODEV;
1118 }
1119
1120 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
1121 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
1122
1123 for (i = 0; i < afu->crs_num; i++) {
1124 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
1125 if (rc || val == 0) {
1126 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
1127 return -EINVAL;
1128 }
1129 }
1130
1131 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
1132 /*
1133 * We could also check this for the dedicated process model
1134 * since the architecture indicates it should be set to 1, but
1135 * in that case we ignore the value and I'd rather not risk
1136 * breaking any existing dedicated process AFUs that left it as
1137 * 0 (not that I'm aware of any). It is clearly an error for an
1138 * AFU directed AFU to set this to 0, and would have previously
1139 * triggered a bug resulting in the maximum not being enforced
1140 * at all since idr_alloc treats 0 as no maximum.
1141 */
1142 dev_err(&afu->dev, "AFU does not support any processes\n");
1143 return -EINVAL;
1144 }
1145
1146 return 0;
1147 }
1148
1149 static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
1150 {
1151 u64 reg;
1152
1153 /*
1154 * Clear out any regs that contain either an IVTE or address or may be
1155 * waiting on an acknowledgment to try to be a bit safer as we bring
1156 * it online
1157 */
1158 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1159 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1160 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1161 if (cxl_ops->afu_reset(afu))
1162 return -EIO;
1163 if (cxl_afu_disable(afu))
1164 return -EIO;
1165 if (cxl_psl_purge(afu))
1166 return -EIO;
1167 }
1168 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1169 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1170 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1171 if (reg) {
1172 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1173 if (reg & CXL_PSL9_DSISR_An_TF)
1174 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1175 else
1176 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1177 }
1178 if (afu->adapter->native->sl_ops->register_serr_irq) {
1179 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1180 if (reg) {
1181 if (reg & ~0x000000007fffffff)
1182 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1183 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1184 }
1185 }
1186 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1187 if (reg) {
1188 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1189 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1190 }
1191
1192 return 0;
1193 }
1194
1195 static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
1196 {
1197 u64 reg;
1198
1199 /*
1200 * Clear out any regs that contain either an IVTE or address or may be
1201 * waiting on an acknowledgement to try to be a bit safer as we bring
1202 * it online
1203 */
1204 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1205 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1206 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1207 if (cxl_ops->afu_reset(afu))
1208 return -EIO;
1209 if (cxl_afu_disable(afu))
1210 return -EIO;
1211 if (cxl_psl_purge(afu))
1212 return -EIO;
1213 }
1214 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1215 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
1216 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
1217 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1218 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
1219 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
1220 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
1221 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
1222 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
1223 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
1224 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
1225 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1226 if (reg) {
1227 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1228 if (reg & CXL_PSL_DSISR_TRANS)
1229 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1230 else
1231 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1232 }
1233 if (afu->adapter->native->sl_ops->register_serr_irq) {
1234 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1235 if (reg) {
1236 if (reg & ~0xffff)
1237 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1238 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1239 }
1240 }
1241 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1242 if (reg) {
1243 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1244 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1245 }
1246
1247 return 0;
1248 }
1249
1250 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
1251 /*
1252 * afu_eb_read:
1253 * Called from sysfs and reads the afu error info buffer. The h/w only supports
1254 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
1255 * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
1256 */
1257 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
1258 loff_t off, size_t count)
1259 {
1260 loff_t aligned_start, aligned_end;
1261 size_t aligned_length;
1262 void *tbuf;
1263 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1264
1265 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1266 return 0;
1267
1268 /* calculate aligned read window */
1269 count = min((size_t)(afu->eb_len - off), count);
1270 aligned_start = round_down(off, 8);
1271 aligned_end = round_up(off + count, 8);
1272 aligned_length = aligned_end - aligned_start;
1273
1274 /* max we can copy in one read is PAGE_SIZE */
1275 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
1276 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
1277 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1278 }
1279
1280 /* use bounce buffer for copy */
1281 tbuf = (void *)__get_free_page(GFP_KERNEL);
1282 if (!tbuf)
1283 return -ENOMEM;
1284
1285 /* perform aligned read from the mmio region */
1286 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
1287 memcpy(buf, tbuf + (off & 0x7), count);
1288
1289 free_page((unsigned long)tbuf);
1290
1291 return count;
1292 }
1293
1294 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1295 {
1296 int rc;
1297
1298 if ((rc = pci_map_slice_regs(afu, adapter, dev)))
1299 return rc;
1300
1301 if (adapter->native->sl_ops->sanitise_afu_regs) {
1302 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1303 if (rc)
1304 goto err1;
1305 }
1306
1307 /* We need to reset the AFU before we can read the AFU descriptor */
1308 if ((rc = cxl_ops->afu_reset(afu)))
1309 goto err1;
1310
1311 if (cxl_verbose)
1312 dump_afu_descriptor(afu);
1313
1314 if ((rc = cxl_read_afu_descriptor(afu)))
1315 goto err1;
1316
1317 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
1318 goto err1;
1319
1320 if (adapter->native->sl_ops->afu_regs_init)
1321 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1322 goto err1;
1323
1324 if (adapter->native->sl_ops->register_serr_irq)
1325 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1326 goto err1;
1327
1328 if ((rc = cxl_native_register_psl_irq(afu)))
1329 goto err2;
1330
1331 atomic_set(&afu->configured_state, 0);
1332 return 0;
1333
1334 err2:
1335 if (adapter->native->sl_ops->release_serr_irq)
1336 adapter->native->sl_ops->release_serr_irq(afu);
1337 err1:
1338 pci_unmap_slice_regs(afu);
1339 return rc;
1340 }
1341
1342 static void pci_deconfigure_afu(struct cxl_afu *afu)
1343 {
1344 /*
1345 * It's okay to deconfigure when AFU is already locked, otherwise wait
1346 * until there are no readers
1347 */
1348 if (atomic_read(&afu->configured_state) != -1) {
1349 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1350 schedule();
1351 }
1352 cxl_native_release_psl_irq(afu);
1353 if (afu->adapter->native->sl_ops->release_serr_irq)
1354 afu->adapter->native->sl_ops->release_serr_irq(afu);
1355 pci_unmap_slice_regs(afu);
1356 }
1357
1358 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
1359 {
1360 struct cxl_afu *afu;
1361 int rc = -ENOMEM;
1362
1363 afu = cxl_alloc_afu(adapter, slice);
1364 if (!afu)
1365 return -ENOMEM;
1366
1367 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1368 if (!afu->native)
1369 goto err_free_afu;
1370
1371 mutex_init(&afu->native->spa_mutex);
1372
1373 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1374 if (rc)
1375 goto err_free_native;
1376
1377 rc = pci_configure_afu(afu, adapter, dev);
1378 if (rc)
1379 goto err_free_native;
1380
1381 /* Don't care if this fails */
1382 cxl_debugfs_afu_add(afu);
1383
1384 /*
1385 * After we call this function we must not free the afu directly, even
1386 * if it returns an error!
1387 */
1388 if ((rc = cxl_register_afu(afu)))
1389 goto err_put1;
1390
1391 if ((rc = cxl_sysfs_afu_add(afu)))
1392 goto err_put1;
1393
1394 adapter->afu[afu->slice] = afu;
1395
1396 if ((rc = cxl_pci_vphb_add(afu)))
1397 dev_info(&afu->dev, "Can't register vPHB\n");
1398
1399 return 0;
1400
1401 err_put1:
1402 pci_deconfigure_afu(afu);
1403 cxl_debugfs_afu_remove(afu);
1404 device_unregister(&afu->dev);
1405 return rc;
1406
1407 err_free_native:
1408 kfree(afu->native);
1409 err_free_afu:
1410 kfree(afu);
1411 return rc;
1412
1413 }
1414
1415 static void cxl_pci_remove_afu(struct cxl_afu *afu)
1416 {
1417 pr_devel("%s\n", __func__);
1418
1419 if (!afu)
1420 return;
1421
1422 cxl_pci_vphb_remove(afu);
1423 cxl_sysfs_afu_remove(afu);
1424 cxl_debugfs_afu_remove(afu);
1425
1426 spin_lock(&afu->adapter->afu_list_lock);
1427 afu->adapter->afu[afu->slice] = NULL;
1428 spin_unlock(&afu->adapter->afu_list_lock);
1429
1430 cxl_context_detach_all(afu);
1431 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1432
1433 pci_deconfigure_afu(afu);
1434 device_unregister(&afu->dev);
1435 }
1436
1437 int cxl_pci_reset(struct cxl *adapter)
1438 {
1439 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1440 int rc;
1441
1442 if (adapter->perst_same_image) {
1443 dev_warn(&dev->dev,
1444 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
1445 return -EINVAL;
1446 }
1447
1448 dev_info(&dev->dev, "CXL reset\n");
1449
1450 /*
1451 * The adapter is about to be reset, so ignore errors.
1452 * Not supported on P9 DD1
1453 */
1454 if ((cxl_is_power8()) || (!(cxl_is_power9_dd1())))
1455 cxl_data_cache_flush(adapter);
1456
1457 /* pcie_warm_reset requests a fundamental pci reset which includes a
1458 * PERST assert/deassert. PERST triggers a loading of the image
1459 * if "user" or "factory" is selected in sysfs */
1460 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
1461 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1462 return rc;
1463 }
1464
1465 return rc;
1466 }
1467
1468 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
1469 {
1470 if (pci_request_region(dev, 2, "priv 2 regs"))
1471 goto err1;
1472 if (pci_request_region(dev, 0, "priv 1 regs"))
1473 goto err2;
1474
1475 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
1476 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
1477
1478 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
1479 goto err3;
1480
1481 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
1482 goto err4;
1483
1484 return 0;
1485
1486 err4:
1487 iounmap(adapter->native->p1_mmio);
1488 adapter->native->p1_mmio = NULL;
1489 err3:
1490 pci_release_region(dev, 0);
1491 err2:
1492 pci_release_region(dev, 2);
1493 err1:
1494 return -ENOMEM;
1495 }
1496
1497 static void cxl_unmap_adapter_regs(struct cxl *adapter)
1498 {
1499 if (adapter->native->p1_mmio) {
1500 iounmap(adapter->native->p1_mmio);
1501 adapter->native->p1_mmio = NULL;
1502 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1503 }
1504 if (adapter->native->p2_mmio) {
1505 iounmap(adapter->native->p2_mmio);
1506 adapter->native->p2_mmio = NULL;
1507 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1508 }
1509 }
1510
1511 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
1512 {
1513 int vsec;
1514 u32 afu_desc_off, afu_desc_size;
1515 u32 ps_off, ps_size;
1516 u16 vseclen;
1517 u8 image_state;
1518
1519 if (!(vsec = find_cxl_vsec(dev))) {
1520 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
1521 return -ENODEV;
1522 }
1523
1524 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1525 if (vseclen < CXL_VSEC_MIN_SIZE) {
1526 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
1527 return -EINVAL;
1528 }
1529
1530 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1531 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1532 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1533 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1534 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1535 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1536 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1537 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1538 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
1539
1540 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1541 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1542 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1543 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1544 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
1545
1546 /* Convert everything to bytes, because there is NO WAY I'd look at the
1547 * code a month later and forget what units these are in ;-) */
1548 adapter->native->ps_off = ps_off * 64 * 1024;
1549 adapter->ps_size = ps_size * 64 * 1024;
1550 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1551 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
1552
1553 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1554 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1555
1556 return 0;
1557 }
1558
1559 /*
1560 * Workaround a PCIe Host Bridge defect on some cards, that can cause
1561 * malformed Transaction Layer Packet (TLP) errors to be erroneously
1562 * reported. Mask this error in the Uncorrectable Error Mask Register.
1563 *
1564 * The upper nibble of the PSL revision is used to distinguish between
1565 * different cards. The affected ones have it set to 0.
1566 */
1567 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1568 {
1569 int aer;
1570 u32 data;
1571
1572 if (adapter->psl_rev & 0xf000)
1573 return;
1574 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1575 return;
1576 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1577 if (data & PCI_ERR_UNC_MALF_TLP)
1578 if (data & PCI_ERR_UNC_INTN)
1579 return;
1580 data |= PCI_ERR_UNC_MALF_TLP;
1581 data |= PCI_ERR_UNC_INTN;
1582 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1583 }
1584
1585 static bool cxl_compatible_caia_version(struct cxl *adapter)
1586 {
1587 if (cxl_is_power8() && (adapter->caia_major == 1))
1588 return true;
1589
1590 if (cxl_is_power9() && (adapter->caia_major == 2))
1591 return true;
1592
1593 return false;
1594 }
1595
1596 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1597 {
1598 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1599 return -EBUSY;
1600
1601 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
1602 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
1603 return -EINVAL;
1604 }
1605
1606 if (!cxl_compatible_caia_version(adapter)) {
1607 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
1608 adapter->caia_major);
1609 return -ENODEV;
1610 }
1611
1612 if (!adapter->slices) {
1613 /* Once we support dynamic reprogramming we can use the card if
1614 * it supports loadable AFUs */
1615 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
1616 return -EINVAL;
1617 }
1618
1619 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
1620 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
1621 return -EINVAL;
1622 }
1623
1624 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
1625 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
1626 "available in BAR2: 0x%llx > 0x%llx\n",
1627 adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
1628 return -EINVAL;
1629 }
1630
1631 return 0;
1632 }
1633
1634 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1635 {
1636 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1637 }
1638
1639 static void cxl_release_adapter(struct device *dev)
1640 {
1641 struct cxl *adapter = to_cxl_adapter(dev);
1642
1643 pr_devel("cxl_release_adapter\n");
1644
1645 cxl_remove_adapter_nr(adapter);
1646
1647 kfree(adapter->native);
1648 kfree(adapter);
1649 }
1650
1651 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1652
1653 static int sanitise_adapter_regs(struct cxl *adapter)
1654 {
1655 int rc = 0;
1656
1657 /* Clear PSL tberror bit by writing 1 to it */
1658 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
1659
1660 if (adapter->native->sl_ops->invalidate_all) {
1661 /* do not invalidate ERAT entries when not reloading on PERST */
1662 if (cxl_is_power9() && (adapter->perst_loads_image))
1663 return 0;
1664 rc = adapter->native->sl_ops->invalidate_all(adapter);
1665 }
1666
1667 return rc;
1668 }
1669
1670 /* This should contain *only* operations that can safely be done in
1671 * both creation and recovery.
1672 */
1673 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
1674 {
1675 int rc;
1676
1677 adapter->dev.parent = &dev->dev;
1678 adapter->dev.release = cxl_release_adapter;
1679 pci_set_drvdata(dev, adapter);
1680
1681 rc = pci_enable_device(dev);
1682 if (rc) {
1683 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1684 return rc;
1685 }
1686
1687 if ((rc = cxl_read_vsec(adapter, dev)))
1688 return rc;
1689
1690 if ((rc = cxl_vsec_looks_ok(adapter, dev)))
1691 return rc;
1692
1693 cxl_fixup_malformed_tlp(adapter, dev);
1694
1695 if ((rc = setup_cxl_bars(dev)))
1696 return rc;
1697
1698 if ((rc = setup_cxl_protocol_area(dev)))
1699 return rc;
1700
1701 if ((rc = cxl_update_image_control(adapter)))
1702 return rc;
1703
1704 if ((rc = cxl_map_adapter_regs(adapter, dev)))
1705 return rc;
1706
1707 if ((rc = sanitise_adapter_regs(adapter)))
1708 goto err;
1709
1710 if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
1711 goto err;
1712
1713 /* Required for devices using CAPP DMA mode, harmless for others */
1714 pci_set_master(dev);
1715
1716 if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
1717 goto err;
1718
1719 /* If recovery happened, the last step is to turn on snooping.
1720 * In the non-recovery case this has no effect */
1721 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1722 goto err;
1723
1724 /* Ignore error, adapter init is not dependant on timebase sync */
1725 cxl_setup_psl_timebase(adapter, dev);
1726
1727 if ((rc = cxl_native_register_psl_err_irq(adapter)))
1728 goto err;
1729
1730 return 0;
1731
1732 err:
1733 cxl_unmap_adapter_regs(adapter);
1734 return rc;
1735
1736 }
1737
1738 static void cxl_deconfigure_adapter(struct cxl *adapter)
1739 {
1740 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1741
1742 cxl_native_release_psl_err_irq(adapter);
1743 cxl_unmap_adapter_regs(adapter);
1744
1745 pci_disable_device(pdev);
1746 }
1747
1748 static void cxl_stop_trace_psl9(struct cxl *adapter)
1749 {
1750 int traceid;
1751 u64 trace_state, trace_mask;
1752 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1753
1754 /* read each tracearray state and issue mmio to stop them is needed */
1755 for (traceid = 0; traceid <= CXL_PSL9_TRACEID_MAX; ++traceid) {
1756 trace_state = cxl_p1_read(adapter, CXL_PSL9_CTCCFG);
1757 trace_mask = (0x3ULL << (62 - traceid * 2));
1758 trace_state = (trace_state & trace_mask) >> (62 - traceid * 2);
1759 dev_dbg(&dev->dev, "cxl: Traceid-%d trace_state=0x%0llX\n",
1760 traceid, trace_state);
1761
1762 /* issue mmio if the trace array isn't in FIN state */
1763 if (trace_state != CXL_PSL9_TRACESTATE_FIN)
1764 cxl_p1_write(adapter, CXL_PSL9_TRACECFG,
1765 0x8400000000000000ULL | traceid);
1766 }
1767 }
1768
1769 static void cxl_stop_trace_psl8(struct cxl *adapter)
1770 {
1771 int slice;
1772
1773 /* Stop the trace */
1774 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x8000000000000017LL);
1775
1776 /* Stop the slice traces */
1777 spin_lock(&adapter->afu_list_lock);
1778 for (slice = 0; slice < adapter->slices; slice++) {
1779 if (adapter->afu[slice])
1780 cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE,
1781 0x8000000000000000LL);
1782 }
1783 spin_unlock(&adapter->afu_list_lock);
1784 }
1785
1786 static const struct cxl_service_layer_ops psl9_ops = {
1787 .adapter_regs_init = init_implementation_adapter_regs_psl9,
1788 .invalidate_all = cxl_invalidate_all_psl9,
1789 .afu_regs_init = init_implementation_afu_regs_psl9,
1790 .sanitise_afu_regs = sanitise_afu_regs_psl9,
1791 .register_serr_irq = cxl_native_register_serr_irq,
1792 .release_serr_irq = cxl_native_release_serr_irq,
1793 .handle_interrupt = cxl_irq_psl9,
1794 .fail_irq = cxl_fail_irq_psl,
1795 .activate_dedicated_process = cxl_activate_dedicated_process_psl9,
1796 .attach_afu_directed = cxl_attach_afu_directed_psl9,
1797 .attach_dedicated_process = cxl_attach_dedicated_process_psl9,
1798 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9,
1799 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
1800 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
1801 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
1802 .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9,
1803 .debugfs_stop_trace = cxl_stop_trace_psl9,
1804 .write_timebase_ctrl = write_timebase_ctrl_psl9,
1805 .timebase_read = timebase_read_psl9,
1806 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1807 .needs_reset_before_disable = true,
1808 };
1809
1810 static const struct cxl_service_layer_ops psl8_ops = {
1811 .adapter_regs_init = init_implementation_adapter_regs_psl8,
1812 .invalidate_all = cxl_invalidate_all_psl8,
1813 .afu_regs_init = init_implementation_afu_regs_psl8,
1814 .sanitise_afu_regs = sanitise_afu_regs_psl8,
1815 .register_serr_irq = cxl_native_register_serr_irq,
1816 .release_serr_irq = cxl_native_release_serr_irq,
1817 .handle_interrupt = cxl_irq_psl8,
1818 .fail_irq = cxl_fail_irq_psl,
1819 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1820 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1821 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1822 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1823 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
1824 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
1825 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
1826 .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl8,
1827 .debugfs_stop_trace = cxl_stop_trace_psl8,
1828 .write_timebase_ctrl = write_timebase_ctrl_psl8,
1829 .timebase_read = timebase_read_psl8,
1830 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1831 .needs_reset_before_disable = true,
1832 };
1833
1834 static const struct cxl_service_layer_ops xsl_ops = {
1835 .adapter_regs_init = init_implementation_adapter_regs_xsl,
1836 .invalidate_all = cxl_invalidate_all_psl8,
1837 .sanitise_afu_regs = sanitise_afu_regs_psl8,
1838 .handle_interrupt = cxl_irq_psl8,
1839 .fail_irq = cxl_fail_irq_psl,
1840 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1841 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1842 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1843 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1844 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_xsl,
1845 .write_timebase_ctrl = write_timebase_ctrl_xsl,
1846 .timebase_read = timebase_read_xsl,
1847 .capi_mode = OPAL_PHB_CAPI_MODE_DMA,
1848 };
1849
1850 static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1851 {
1852 if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) {
1853 /* Mellanox CX-4 */
1854 dev_info(&dev->dev, "Device uses an XSL\n");
1855 adapter->native->sl_ops = &xsl_ops;
1856 adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */
1857 } else {
1858 if (cxl_is_power8()) {
1859 dev_info(&dev->dev, "Device uses a PSL8\n");
1860 adapter->native->sl_ops = &psl8_ops;
1861 } else {
1862 dev_info(&dev->dev, "Device uses a PSL9\n");
1863 adapter->native->sl_ops = &psl9_ops;
1864 }
1865 }
1866 }
1867
1868
1869 static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
1870 {
1871 struct cxl *adapter;
1872 int rc;
1873
1874 adapter = cxl_alloc_adapter();
1875 if (!adapter)
1876 return ERR_PTR(-ENOMEM);
1877
1878 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1879 if (!adapter->native) {
1880 rc = -ENOMEM;
1881 goto err_release;
1882 }
1883
1884 set_sl_ops(adapter, dev);
1885
1886 /* Set defaults for parameters which need to persist over
1887 * configure/reconfigure
1888 */
1889 adapter->perst_loads_image = true;
1890 adapter->perst_same_image = false;
1891
1892 rc = cxl_configure_adapter(adapter, dev);
1893 if (rc) {
1894 pci_disable_device(dev);
1895 goto err_release;
1896 }
1897
1898 /* Don't care if this one fails: */
1899 cxl_debugfs_adapter_add(adapter);
1900
1901 /*
1902 * After we call this function we must not free the adapter directly,
1903 * even if it returns an error!
1904 */
1905 if ((rc = cxl_register_adapter(adapter)))
1906 goto err_put1;
1907
1908 if ((rc = cxl_sysfs_adapter_add(adapter)))
1909 goto err_put1;
1910
1911 /* Release the context lock as adapter is configured */
1912 cxl_adapter_context_unlock(adapter);
1913
1914 return adapter;
1915
1916 err_put1:
1917 /* This should mirror cxl_remove_adapter, except without the
1918 * sysfs parts
1919 */
1920 cxl_debugfs_adapter_remove(adapter);
1921 cxl_deconfigure_adapter(adapter);
1922 device_unregister(&adapter->dev);
1923 return ERR_PTR(rc);
1924
1925 err_release:
1926 cxl_release_adapter(&adapter->dev);
1927 return ERR_PTR(rc);
1928 }
1929
1930 static void cxl_pci_remove_adapter(struct cxl *adapter)
1931 {
1932 pr_devel("cxl_remove_adapter\n");
1933
1934 cxl_sysfs_adapter_remove(adapter);
1935 cxl_debugfs_adapter_remove(adapter);
1936
1937 /*
1938 * Flush adapter datacache as its about to be removed.
1939 * Not supported on P9 DD1.
1940 */
1941 if ((cxl_is_power8()) || (!(cxl_is_power9_dd1())))
1942 cxl_data_cache_flush(adapter);
1943
1944 cxl_deconfigure_adapter(adapter);
1945
1946 device_unregister(&adapter->dev);
1947 }
1948
1949 #define CXL_MAX_PCIEX_PARENT 2
1950
1951 int cxl_slot_is_switched(struct pci_dev *dev)
1952 {
1953 struct device_node *np;
1954 int depth = 0;
1955 const __be32 *prop;
1956
1957 if (!(np = pci_device_to_OF_node(dev))) {
1958 pr_err("cxl: np = NULL\n");
1959 return -ENODEV;
1960 }
1961 of_node_get(np);
1962 while (np) {
1963 np = of_get_next_parent(np);
1964 prop = of_get_property(np, "device_type", NULL);
1965 if (!prop || strcmp((char *)prop, "pciex"))
1966 break;
1967 depth++;
1968 }
1969 of_node_put(np);
1970 return (depth > CXL_MAX_PCIEX_PARENT);
1971 }
1972
1973 bool cxl_slot_is_supported(struct pci_dev *dev, int flags)
1974 {
1975 if (!cpu_has_feature(CPU_FTR_HVMODE))
1976 return false;
1977
1978 if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) {
1979 /*
1980 * CAPP DMA mode is technically supported on regular P8, but
1981 * will EEH if the card attempts to access memory < 4GB, which
1982 * we cannot realistically avoid. We might be able to work
1983 * around the issue, but until then return unsupported:
1984 */
1985 return false;
1986 }
1987
1988 if (cxl_slot_is_switched(dev))
1989 return false;
1990
1991 /*
1992 * XXX: This gets a little tricky on regular P8 (not POWER8NVL) since
1993 * the CAPP can be connected to PHB 0, 1 or 2 on a first come first
1994 * served basis, which is racy to check from here. If we need to
1995 * support this in future we might need to consider having this
1996 * function effectively reserve it ahead of time.
1997 *
1998 * Currently, the only user of this API is the Mellanox CX4, which is
1999 * only supported on P8NVL due to the above mentioned limitation of
2000 * CAPP DMA mode and therefore does not need to worry about this. If the
2001 * issue with CAPP DMA mode is later worked around on P8 we might need
2002 * to revisit this.
2003 */
2004
2005 return true;
2006 }
2007 EXPORT_SYMBOL_GPL(cxl_slot_is_supported);
2008
2009
2010 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
2011 {
2012 struct cxl *adapter;
2013 int slice;
2014 int rc;
2015
2016 if (cxl_pci_is_vphb_device(dev)) {
2017 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
2018 return -ENODEV;
2019 }
2020
2021 if (cxl_slot_is_switched(dev)) {
2022 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
2023 return -ENODEV;
2024 }
2025
2026 if (cxl_is_power9() && !radix_enabled()) {
2027 dev_info(&dev->dev, "Only Radix mode supported\n");
2028 return -ENODEV;
2029 }
2030
2031 if (cxl_verbose)
2032 dump_cxl_config_space(dev);
2033
2034 adapter = cxl_pci_init_adapter(dev);
2035 if (IS_ERR(adapter)) {
2036 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
2037 return PTR_ERR(adapter);
2038 }
2039
2040 for (slice = 0; slice < adapter->slices; slice++) {
2041 if ((rc = pci_init_afu(adapter, slice, dev))) {
2042 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
2043 continue;
2044 }
2045
2046 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
2047 if (rc)
2048 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
2049 }
2050
2051 if (pnv_pci_on_cxl_phb(dev) && adapter->slices >= 1)
2052 pnv_cxl_phb_set_peer_afu(dev, adapter->afu[0]);
2053
2054 return 0;
2055 }
2056
2057 static void cxl_remove(struct pci_dev *dev)
2058 {
2059 struct cxl *adapter = pci_get_drvdata(dev);
2060 struct cxl_afu *afu;
2061 int i;
2062
2063 /*
2064 * Lock to prevent someone grabbing a ref through the adapter list as
2065 * we are removing it
2066 */
2067 for (i = 0; i < adapter->slices; i++) {
2068 afu = adapter->afu[i];
2069 cxl_pci_remove_afu(afu);
2070 }
2071 cxl_pci_remove_adapter(adapter);
2072 }
2073
2074 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
2075 pci_channel_state_t state)
2076 {
2077 struct pci_dev *afu_dev;
2078 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
2079 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
2080
2081 /* There should only be one entry, but go through the list
2082 * anyway
2083 */
2084 if (afu->phb == NULL)
2085 return result;
2086
2087 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2088 if (!afu_dev->driver)
2089 continue;
2090
2091 afu_dev->error_state = state;
2092
2093 if (afu_dev->driver->err_handler)
2094 afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
2095 state);
2096 /* Disconnect trumps all, NONE trumps NEED_RESET */
2097 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2098 result = PCI_ERS_RESULT_DISCONNECT;
2099 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
2100 (result == PCI_ERS_RESULT_NEED_RESET))
2101 result = PCI_ERS_RESULT_NONE;
2102 }
2103 return result;
2104 }
2105
2106 static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
2107 pci_channel_state_t state)
2108 {
2109 struct cxl *adapter = pci_get_drvdata(pdev);
2110 struct cxl_afu *afu;
2111 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET, afu_result;
2112 int i;
2113
2114 /* At this point, we could still have an interrupt pending.
2115 * Let's try to get them out of the way before they do
2116 * anything we don't like.
2117 */
2118 schedule();
2119
2120 /* If we're permanently dead, give up. */
2121 if (state == pci_channel_io_perm_failure) {
2122 for (i = 0; i < adapter->slices; i++) {
2123 afu = adapter->afu[i];
2124 /*
2125 * Tell the AFU drivers; but we don't care what they
2126 * say, we're going away.
2127 */
2128 cxl_vphb_error_detected(afu, state);
2129 }
2130 return PCI_ERS_RESULT_DISCONNECT;
2131 }
2132
2133 /* Are we reflashing?
2134 *
2135 * If we reflash, we could come back as something entirely
2136 * different, including a non-CAPI card. As such, by default
2137 * we don't participate in the process. We'll be unbound and
2138 * the slot re-probed. (TODO: check EEH doesn't blindly rebind
2139 * us!)
2140 *
2141 * However, this isn't the entire story: for reliablity
2142 * reasons, we usually want to reflash the FPGA on PERST in
2143 * order to get back to a more reliable known-good state.
2144 *
2145 * This causes us a bit of a problem: if we reflash we can't
2146 * trust that we'll come back the same - we could have a new
2147 * image and been PERSTed in order to load that
2148 * image. However, most of the time we actually *will* come
2149 * back the same - for example a regular EEH event.
2150 *
2151 * Therefore, we allow the user to assert that the image is
2152 * indeed the same and that we should continue on into EEH
2153 * anyway.
2154 */
2155 if (adapter->perst_loads_image && !adapter->perst_same_image) {
2156 /* TODO take the PHB out of CXL mode */
2157 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
2158 return PCI_ERS_RESULT_NONE;
2159 }
2160
2161 /*
2162 * At this point, we want to try to recover. We'll always
2163 * need a complete slot reset: we don't trust any other reset.
2164 *
2165 * Now, we go through each AFU:
2166 * - We send the driver, if bound, an error_detected callback.
2167 * We expect it to clean up, but it can also tell us to give
2168 * up and permanently detach the card. To simplify things, if
2169 * any bound AFU driver doesn't support EEH, we give up on EEH.
2170 *
2171 * - We detach all contexts associated with the AFU. This
2172 * does not free them, but puts them into a CLOSED state
2173 * which causes any the associated files to return useful
2174 * errors to userland. It also unmaps, but does not free,
2175 * any IRQs.
2176 *
2177 * - We clean up our side: releasing and unmapping resources we hold
2178 * so we can wire them up again when the hardware comes back up.
2179 *
2180 * Driver authors should note:
2181 *
2182 * - Any contexts you create in your kernel driver (except
2183 * those associated with anonymous file descriptors) are
2184 * your responsibility to free and recreate. Likewise with
2185 * any attached resources.
2186 *
2187 * - We will take responsibility for re-initialising the
2188 * device context (the one set up for you in
2189 * cxl_pci_enable_device_hook and accessed through
2190 * cxl_get_context). If you've attached IRQs or other
2191 * resources to it, they remains yours to free.
2192 *
2193 * You can call the same functions to release resources as you
2194 * normally would: we make sure that these functions continue
2195 * to work when the hardware is down.
2196 *
2197 * Two examples:
2198 *
2199 * 1) If you normally free all your resources at the end of
2200 * each request, or if you use anonymous FDs, your
2201 * error_detected callback can simply set a flag to tell
2202 * your driver not to start any new calls. You can then
2203 * clear the flag in the resume callback.
2204 *
2205 * 2) If you normally allocate your resources on startup:
2206 * * Set a flag in error_detected as above.
2207 * * Let CXL detach your contexts.
2208 * * In slot_reset, free the old resources and allocate new ones.
2209 * * In resume, clear the flag to allow things to start.
2210 */
2211 for (i = 0; i < adapter->slices; i++) {
2212 afu = adapter->afu[i];
2213
2214 afu_result = cxl_vphb_error_detected(afu, state);
2215
2216 cxl_context_detach_all(afu);
2217 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
2218 pci_deconfigure_afu(afu);
2219
2220 /* Disconnect trumps all, NONE trumps NEED_RESET */
2221 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2222 result = PCI_ERS_RESULT_DISCONNECT;
2223 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
2224 (result == PCI_ERS_RESULT_NEED_RESET))
2225 result = PCI_ERS_RESULT_NONE;
2226 }
2227
2228 /* should take the context lock here */
2229 if (cxl_adapter_context_lock(adapter) != 0)
2230 dev_warn(&adapter->dev,
2231 "Couldn't take context lock with %d active-contexts\n",
2232 atomic_read(&adapter->contexts_num));
2233
2234 cxl_deconfigure_adapter(adapter);
2235
2236 return result;
2237 }
2238
2239 static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
2240 {
2241 struct cxl *adapter = pci_get_drvdata(pdev);
2242 struct cxl_afu *afu;
2243 struct cxl_context *ctx;
2244 struct pci_dev *afu_dev;
2245 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
2246 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
2247 int i;
2248
2249 if (cxl_configure_adapter(adapter, pdev))
2250 goto err;
2251
2252 /*
2253 * Unlock context activation for the adapter. Ideally this should be
2254 * done in cxl_pci_resume but cxlflash module tries to activate the
2255 * master context as part of slot_reset callback.
2256 */
2257 cxl_adapter_context_unlock(adapter);
2258
2259 for (i = 0; i < adapter->slices; i++) {
2260 afu = adapter->afu[i];
2261
2262 if (pci_configure_afu(afu, adapter, pdev))
2263 goto err;
2264
2265 if (cxl_afu_select_best_mode(afu))
2266 goto err;
2267
2268 if (afu->phb == NULL)
2269 continue;
2270
2271 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2272 /* Reset the device context.
2273 * TODO: make this less disruptive
2274 */
2275 ctx = cxl_get_context(afu_dev);
2276
2277 if (ctx && cxl_release_context(ctx))
2278 goto err;
2279
2280 ctx = cxl_dev_context_init(afu_dev);
2281 if (IS_ERR(ctx))
2282 goto err;
2283
2284 afu_dev->dev.archdata.cxl_ctx = ctx;
2285
2286 if (cxl_ops->afu_check_and_enable(afu))
2287 goto err;
2288
2289 afu_dev->error_state = pci_channel_io_normal;
2290
2291 /* If there's a driver attached, allow it to
2292 * chime in on recovery. Drivers should check
2293 * if everything has come back OK, but
2294 * shouldn't start new work until we call
2295 * their resume function.
2296 */
2297 if (!afu_dev->driver)
2298 continue;
2299
2300 if (afu_dev->driver->err_handler &&
2301 afu_dev->driver->err_handler->slot_reset)
2302 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
2303
2304 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2305 result = PCI_ERS_RESULT_DISCONNECT;
2306 }
2307 }
2308 return result;
2309
2310 err:
2311 /* All the bits that happen in both error_detected and cxl_remove
2312 * should be idempotent, so we don't need to worry about leaving a mix
2313 * of unconfigured and reconfigured resources.
2314 */
2315 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
2316 return PCI_ERS_RESULT_DISCONNECT;
2317 }
2318
2319 static void cxl_pci_resume(struct pci_dev *pdev)
2320 {
2321 struct cxl *adapter = pci_get_drvdata(pdev);
2322 struct cxl_afu *afu;
2323 struct pci_dev *afu_dev;
2324 int i;
2325
2326 /* Everything is back now. Drivers should restart work now.
2327 * This is not the place to be checking if everything came back up
2328 * properly, because there's no return value: do that in slot_reset.
2329 */
2330 for (i = 0; i < adapter->slices; i++) {
2331 afu = adapter->afu[i];
2332
2333 if (afu->phb == NULL)
2334 continue;
2335
2336 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2337 if (afu_dev->driver && afu_dev->driver->err_handler &&
2338 afu_dev->driver->err_handler->resume)
2339 afu_dev->driver->err_handler->resume(afu_dev);
2340 }
2341 }
2342 }
2343
2344 static const struct pci_error_handlers cxl_err_handler = {
2345 .error_detected = cxl_pci_error_detected,
2346 .slot_reset = cxl_pci_slot_reset,
2347 .resume = cxl_pci_resume,
2348 };
2349
2350 struct pci_driver cxl_pci_driver = {
2351 .name = "cxl-pci",
2352 .id_table = cxl_pci_tbl,
2353 .probe = cxl_probe,
2354 .remove = cxl_remove,
2355 .shutdown = cxl_remove,
2356 .err_handler = &cxl_err_handler,
2357 };
Linux with added FPC-III support