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Linux 4.16.11
[linux/fpc-iii.git] / drivers / mtd / spi-nor / cadence-quadspi.c
blob5872f31eaa60f91dae62bc1690e78aa97ca5c2a8
1 /*
2 * Driver for Cadence QSPI Controller
3 *
4 * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18 #include <linux/clk.h>
19 #include <linux/completion.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/errno.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/jiffies.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/mtd/spi-nor.h>
31 #include <linux/of_device.h>
32 #include <linux/of.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/sched.h>
36 #include <linux/spi/spi.h>
37 #include <linux/timer.h>
38
39 #define CQSPI_NAME "cadence-qspi"
40 #define CQSPI_MAX_CHIPSELECT 16
41
42 /* Quirks */
43 #define CQSPI_NEEDS_WR_DELAY BIT(0)
44
45 struct cqspi_st;
46
47 struct cqspi_flash_pdata {
48 struct spi_nor nor;
49 struct cqspi_st *cqspi;
50 u32 clk_rate;
51 u32 read_delay;
52 u32 tshsl_ns;
53 u32 tsd2d_ns;
54 u32 tchsh_ns;
55 u32 tslch_ns;
56 u8 inst_width;
57 u8 addr_width;
58 u8 data_width;
59 u8 cs;
60 bool registered;
61 bool use_direct_mode;
62 };
63
64 struct cqspi_st {
65 struct platform_device *pdev;
66
67 struct clk *clk;
68 unsigned int sclk;
69
70 void __iomem *iobase;
71 void __iomem *ahb_base;
72 resource_size_t ahb_size;
73 struct completion transfer_complete;
74 struct mutex bus_mutex;
75
76 int current_cs;
77 int current_page_size;
78 int current_erase_size;
79 int current_addr_width;
80 unsigned long master_ref_clk_hz;
81 bool is_decoded_cs;
82 u32 fifo_depth;
83 u32 fifo_width;
84 bool rclk_en;
85 u32 trigger_address;
86 u32 wr_delay;
87 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
88 };
89
90 /* Operation timeout value */
91 #define CQSPI_TIMEOUT_MS 500
92 #define CQSPI_READ_TIMEOUT_MS 10
93
94 /* Instruction type */
95 #define CQSPI_INST_TYPE_SINGLE 0
96 #define CQSPI_INST_TYPE_DUAL 1
97 #define CQSPI_INST_TYPE_QUAD 2
98
99 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
100 #define CQSPI_DUMMY_BYTES_MAX 4
101 #define CQSPI_DUMMY_CLKS_MAX 31
102
103 #define CQSPI_STIG_DATA_LEN_MAX 8
104
105 /* Register map */
106 #define CQSPI_REG_CONFIG 0x00
107 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
108 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7)
109 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
110 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
111 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
112 #define CQSPI_REG_CONFIG_BAUD_LSB 19
113 #define CQSPI_REG_CONFIG_IDLE_LSB 31
114 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
115 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
116
117 #define CQSPI_REG_RD_INSTR 0x04
118 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
119 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
120 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
121 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
122 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
123 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
124 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
125 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
126 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
127 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
128
129 #define CQSPI_REG_WR_INSTR 0x08
130 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
131 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
132 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
133
134 #define CQSPI_REG_DELAY 0x0C
135 #define CQSPI_REG_DELAY_TSLCH_LSB 0
136 #define CQSPI_REG_DELAY_TCHSH_LSB 8
137 #define CQSPI_REG_DELAY_TSD2D_LSB 16
138 #define CQSPI_REG_DELAY_TSHSL_LSB 24
139 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
140 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
141 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
142 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
143
144 #define CQSPI_REG_READCAPTURE 0x10
145 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
146 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
147 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
148
149 #define CQSPI_REG_SIZE 0x14
150 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
151 #define CQSPI_REG_SIZE_PAGE_LSB 4
152 #define CQSPI_REG_SIZE_BLOCK_LSB 16
153 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
154 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
155 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
156
157 #define CQSPI_REG_SRAMPARTITION 0x18
158 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
159
160 #define CQSPI_REG_DMA 0x20
161 #define CQSPI_REG_DMA_SINGLE_LSB 0
162 #define CQSPI_REG_DMA_BURST_LSB 8
163 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF
164 #define CQSPI_REG_DMA_BURST_MASK 0xFF
165
166 #define CQSPI_REG_REMAP 0x24
167 #define CQSPI_REG_MODE_BIT 0x28
168
169 #define CQSPI_REG_SDRAMLEVEL 0x2C
170 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
171 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
172 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
173 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
174
175 #define CQSPI_REG_IRQSTATUS 0x40
176 #define CQSPI_REG_IRQMASK 0x44
177
178 #define CQSPI_REG_INDIRECTRD 0x60
179 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
180 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
181 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
182
183 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
184 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
185 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
186
187 #define CQSPI_REG_CMDCTRL 0x90
188 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
189 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
190 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
191 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
192 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
193 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
194 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
195 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
196 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
197 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
198 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
199 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
200
201 #define CQSPI_REG_INDIRECTWR 0x70
202 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
203 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
204 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
205
206 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
207 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
208 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
209
210 #define CQSPI_REG_CMDADDRESS 0x94
211 #define CQSPI_REG_CMDREADDATALOWER 0xA0
212 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
213 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
214 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
215
216 /* Interrupt status bits */
217 #define CQSPI_REG_IRQ_MODE_ERR BIT(0)
218 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
219 #define CQSPI_REG_IRQ_IND_COMP BIT(2)
220 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
221 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
222 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
223 #define CQSPI_REG_IRQ_WATERMARK BIT(6)
224 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
225
226 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
227 CQSPI_REG_IRQ_IND_SRAM_FULL | \
228 CQSPI_REG_IRQ_IND_COMP)
229
230 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
231 CQSPI_REG_IRQ_WATERMARK | \
232 CQSPI_REG_IRQ_UNDERFLOW)
233
234 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF
235
236 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
237 {
238 unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
239 u32 val;
240
241 while (1) {
242 val = readl(reg);
243 if (clear)
244 val = ~val;
245 val &= mask;
246
247 if (val == mask)
248 return 0;
249
250 if (time_after(jiffies, end))
251 return -ETIMEDOUT;
252 }
253 }
254
255 static bool cqspi_is_idle(struct cqspi_st *cqspi)
256 {
257 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
258
259 return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
260 }
261
262 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
263 {
264 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
265
266 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
267 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
268 }
269
270 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
271 {
272 struct cqspi_st *cqspi = dev;
273 unsigned int irq_status;
274
275 /* Read interrupt status */
276 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
277
278 /* Clear interrupt */
279 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
280
281 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
282
283 if (irq_status)
284 complete(&cqspi->transfer_complete);
285
286 return IRQ_HANDLED;
287 }
288
289 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
290 {
291 struct cqspi_flash_pdata *f_pdata = nor->priv;
292 u32 rdreg = 0;
293
294 rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
295 rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
296 rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
297
298 return rdreg;
299 }
300
301 static int cqspi_wait_idle(struct cqspi_st *cqspi)
302 {
303 const unsigned int poll_idle_retry = 3;
304 unsigned int count = 0;
305 unsigned long timeout;
306
307 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
308 while (1) {
309 /*
310 * Read few times in succession to ensure the controller
311 * is indeed idle, that is, the bit does not transition
312 * low again.
313 */
314 if (cqspi_is_idle(cqspi))
315 count++;
316 else
317 count = 0;
318
319 if (count >= poll_idle_retry)
320 return 0;
321
322 if (time_after(jiffies, timeout)) {
323 /* Timeout, in busy mode. */
324 dev_err(&cqspi->pdev->dev,
325 "QSPI is still busy after %dms timeout.\n",
326 CQSPI_TIMEOUT_MS);
327 return -ETIMEDOUT;
328 }
329
330 cpu_relax();
331 }
332 }
333
334 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
335 {
336 void __iomem *reg_base = cqspi->iobase;
337 int ret;
338
339 /* Write the CMDCTRL without start execution. */
340 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
341 /* Start execute */
342 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
343 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
344
345 /* Polling for completion. */
346 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
347 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
348 if (ret) {
349 dev_err(&cqspi->pdev->dev,
350 "Flash command execution timed out.\n");
351 return ret;
352 }
353
354 /* Polling QSPI idle status. */
355 return cqspi_wait_idle(cqspi);
356 }
357
358 static int cqspi_command_read(struct spi_nor *nor,
359 const u8 *txbuf, const unsigned n_tx,
360 u8 *rxbuf, const unsigned n_rx)
361 {
362 struct cqspi_flash_pdata *f_pdata = nor->priv;
363 struct cqspi_st *cqspi = f_pdata->cqspi;
364 void __iomem *reg_base = cqspi->iobase;
365 unsigned int rdreg;
366 unsigned int reg;
367 unsigned int read_len;
368 int status;
369
370 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
371 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
372 n_rx, rxbuf);
373 return -EINVAL;
374 }
375
376 reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
377
378 rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
379 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
380
381 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
382
383 /* 0 means 1 byte. */
384 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
385 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
386 status = cqspi_exec_flash_cmd(cqspi, reg);
387 if (status)
388 return status;
389
390 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
391
392 /* Put the read value into rx_buf */
393 read_len = (n_rx > 4) ? 4 : n_rx;
394 memcpy(rxbuf, &reg, read_len);
395 rxbuf += read_len;
396
397 if (n_rx > 4) {
398 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
399
400 read_len = n_rx - read_len;
401 memcpy(rxbuf, &reg, read_len);
402 }
403
404 return 0;
405 }
406
407 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
408 const u8 *txbuf, const unsigned n_tx)
409 {
410 struct cqspi_flash_pdata *f_pdata = nor->priv;
411 struct cqspi_st *cqspi = f_pdata->cqspi;
412 void __iomem *reg_base = cqspi->iobase;
413 unsigned int reg;
414 unsigned int data;
415 int ret;
416
417 if (n_tx > 4 || (n_tx && !txbuf)) {
418 dev_err(nor->dev,
419 "Invalid input argument, cmdlen %d txbuf 0x%p\n",
420 n_tx, txbuf);
421 return -EINVAL;
422 }
423
424 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
425 if (n_tx) {
426 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
427 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
428 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
429 data = 0;
430 memcpy(&data, txbuf, n_tx);
431 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
432 }
433
434 ret = cqspi_exec_flash_cmd(cqspi, reg);
435 return ret;
436 }
437
438 static int cqspi_command_write_addr(struct spi_nor *nor,
439 const u8 opcode, const unsigned int addr)
440 {
441 struct cqspi_flash_pdata *f_pdata = nor->priv;
442 struct cqspi_st *cqspi = f_pdata->cqspi;
443 void __iomem *reg_base = cqspi->iobase;
444 unsigned int reg;
445
446 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
447 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
448 reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
449 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
450
451 writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
452
453 return cqspi_exec_flash_cmd(cqspi, reg);
454 }
455
456 static int cqspi_read_setup(struct spi_nor *nor)
457 {
458 struct cqspi_flash_pdata *f_pdata = nor->priv;
459 struct cqspi_st *cqspi = f_pdata->cqspi;
460 void __iomem *reg_base = cqspi->iobase;
461 unsigned int dummy_clk = 0;
462 unsigned int reg;
463
464 reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
465 reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
466
467 /* Setup dummy clock cycles */
468 dummy_clk = nor->read_dummy;
469 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
470 dummy_clk = CQSPI_DUMMY_CLKS_MAX;
471
472 if (dummy_clk / 8) {
473 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
474 /* Set mode bits high to ensure chip doesn't enter XIP */
475 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
476
477 /* Need to subtract the mode byte (8 clocks). */
478 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
479 dummy_clk -= 8;
480
481 if (dummy_clk)
482 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
483 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
484 }
485
486 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
487
488 /* Set address width */
489 reg = readl(reg_base + CQSPI_REG_SIZE);
490 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
491 reg |= (nor->addr_width - 1);
492 writel(reg, reg_base + CQSPI_REG_SIZE);
493 return 0;
494 }
495
496 static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
497 loff_t from_addr, const size_t n_rx)
498 {
499 struct cqspi_flash_pdata *f_pdata = nor->priv;
500 struct cqspi_st *cqspi = f_pdata->cqspi;
501 void __iomem *reg_base = cqspi->iobase;
502 void __iomem *ahb_base = cqspi->ahb_base;
503 unsigned int remaining = n_rx;
504 unsigned int mod_bytes = n_rx % 4;
505 unsigned int bytes_to_read = 0;
506 u8 *rxbuf_end = rxbuf + n_rx;
507 int ret = 0;
508
509 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
510 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
511
512 /* Clear all interrupts. */
513 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
514
515 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
516
517 reinit_completion(&cqspi->transfer_complete);
518 writel(CQSPI_REG_INDIRECTRD_START_MASK,
519 reg_base + CQSPI_REG_INDIRECTRD);
520
521 while (remaining > 0) {
522 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
523 msecs_to_jiffies
524 (CQSPI_READ_TIMEOUT_MS));
525
526 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
527
528 if (!ret && bytes_to_read == 0) {
529 dev_err(nor->dev, "Indirect read timeout, no bytes\n");
530 ret = -ETIMEDOUT;
531 goto failrd;
532 }
533
534 while (bytes_to_read != 0) {
535 unsigned int word_remain = round_down(remaining, 4);
536
537 bytes_to_read *= cqspi->fifo_width;
538 bytes_to_read = bytes_to_read > remaining ?
539 remaining : bytes_to_read;
540 bytes_to_read = round_down(bytes_to_read, 4);
541 /* Read 4 byte word chunks then single bytes */
542 if (bytes_to_read) {
543 ioread32_rep(ahb_base, rxbuf,
544 (bytes_to_read / 4));
545 } else if (!word_remain && mod_bytes) {
546 unsigned int temp = ioread32(ahb_base);
547
548 bytes_to_read = mod_bytes;
549 memcpy(rxbuf, &temp, min((unsigned int)
550 (rxbuf_end - rxbuf),
551 bytes_to_read));
552 }
553 rxbuf += bytes_to_read;
554 remaining -= bytes_to_read;
555 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
556 }
557
558 if (remaining > 0)
559 reinit_completion(&cqspi->transfer_complete);
560 }
561
562 /* Check indirect done status */
563 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
564 CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
565 if (ret) {
566 dev_err(nor->dev,
567 "Indirect read completion error (%i)\n", ret);
568 goto failrd;
569 }
570
571 /* Disable interrupt */
572 writel(0, reg_base + CQSPI_REG_IRQMASK);
573
574 /* Clear indirect completion status */
575 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
576
577 return 0;
578
579 failrd:
580 /* Disable interrupt */
581 writel(0, reg_base + CQSPI_REG_IRQMASK);
582
583 /* Cancel the indirect read */
584 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
585 reg_base + CQSPI_REG_INDIRECTRD);
586 return ret;
587 }
588
589 static int cqspi_write_setup(struct spi_nor *nor)
590 {
591 unsigned int reg;
592 struct cqspi_flash_pdata *f_pdata = nor->priv;
593 struct cqspi_st *cqspi = f_pdata->cqspi;
594 void __iomem *reg_base = cqspi->iobase;
595
596 /* Set opcode. */
597 reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
598 writel(reg, reg_base + CQSPI_REG_WR_INSTR);
599 reg = cqspi_calc_rdreg(nor, nor->program_opcode);
600 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
601
602 reg = readl(reg_base + CQSPI_REG_SIZE);
603 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
604 reg |= (nor->addr_width - 1);
605 writel(reg, reg_base + CQSPI_REG_SIZE);
606 return 0;
607 }
608
609 static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
610 const u8 *txbuf, const size_t n_tx)
611 {
612 const unsigned int page_size = nor->page_size;
613 struct cqspi_flash_pdata *f_pdata = nor->priv;
614 struct cqspi_st *cqspi = f_pdata->cqspi;
615 void __iomem *reg_base = cqspi->iobase;
616 unsigned int remaining = n_tx;
617 unsigned int write_bytes;
618 int ret;
619
620 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
621 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
622
623 /* Clear all interrupts. */
624 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
625
626 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
627
628 reinit_completion(&cqspi->transfer_complete);
629 writel(CQSPI_REG_INDIRECTWR_START_MASK,
630 reg_base + CQSPI_REG_INDIRECTWR);
631 /*
632 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
633 * Controller programming sequence, couple of cycles of
634 * QSPI_REF_CLK delay is required for the above bit to
635 * be internally synchronized by the QSPI module. Provide 5
636 * cycles of delay.
637 */
638 if (cqspi->wr_delay)
639 ndelay(cqspi->wr_delay);
640
641 while (remaining > 0) {
642 write_bytes = remaining > page_size ? page_size : remaining;
643 iowrite32_rep(cqspi->ahb_base, txbuf,
644 DIV_ROUND_UP(write_bytes, 4));
645
646 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
647 msecs_to_jiffies
648 (CQSPI_TIMEOUT_MS));
649 if (!ret) {
650 dev_err(nor->dev, "Indirect write timeout\n");
651 ret = -ETIMEDOUT;
652 goto failwr;
653 }
654
655 txbuf += write_bytes;
656 remaining -= write_bytes;
657
658 if (remaining > 0)
659 reinit_completion(&cqspi->transfer_complete);
660 }
661
662 /* Check indirect done status */
663 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
664 CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
665 if (ret) {
666 dev_err(nor->dev,
667 "Indirect write completion error (%i)\n", ret);
668 goto failwr;
669 }
670
671 /* Disable interrupt. */
672 writel(0, reg_base + CQSPI_REG_IRQMASK);
673
674 /* Clear indirect completion status */
675 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
676
677 cqspi_wait_idle(cqspi);
678
679 return 0;
680
681 failwr:
682 /* Disable interrupt. */
683 writel(0, reg_base + CQSPI_REG_IRQMASK);
684
685 /* Cancel the indirect write */
686 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
687 reg_base + CQSPI_REG_INDIRECTWR);
688 return ret;
689 }
690
691 static void cqspi_chipselect(struct spi_nor *nor)
692 {
693 struct cqspi_flash_pdata *f_pdata = nor->priv;
694 struct cqspi_st *cqspi = f_pdata->cqspi;
695 void __iomem *reg_base = cqspi->iobase;
696 unsigned int chip_select = f_pdata->cs;
697 unsigned int reg;
698
699 reg = readl(reg_base + CQSPI_REG_CONFIG);
700 if (cqspi->is_decoded_cs) {
701 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
702 } else {
703 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
704
705 /* Convert CS if without decoder.
706 * CS0 to 4b'1110
707 * CS1 to 4b'1101
708 * CS2 to 4b'1011
709 * CS3 to 4b'0111
710 */
711 chip_select = 0xF & ~(1 << chip_select);
712 }
713
714 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
715 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
716 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
717 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
718 writel(reg, reg_base + CQSPI_REG_CONFIG);
719 }
720
721 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
722 {
723 struct cqspi_flash_pdata *f_pdata = nor->priv;
724 struct cqspi_st *cqspi = f_pdata->cqspi;
725 void __iomem *iobase = cqspi->iobase;
726 unsigned int reg;
727
728 /* configure page size and block size. */
729 reg = readl(iobase + CQSPI_REG_SIZE);
730 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
731 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
732 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
733 reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
734 reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
735 reg |= (nor->addr_width - 1);
736 writel(reg, iobase + CQSPI_REG_SIZE);
737
738 /* configure the chip select */
739 cqspi_chipselect(nor);
740
741 /* Store the new configuration of the controller */
742 cqspi->current_page_size = nor->page_size;
743 cqspi->current_erase_size = nor->mtd.erasesize;
744 cqspi->current_addr_width = nor->addr_width;
745 }
746
747 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
748 const unsigned int ns_val)
749 {
750 unsigned int ticks;
751
752 ticks = ref_clk_hz / 1000; /* kHz */
753 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
754
755 return ticks;
756 }
757
758 static void cqspi_delay(struct spi_nor *nor)
759 {
760 struct cqspi_flash_pdata *f_pdata = nor->priv;
761 struct cqspi_st *cqspi = f_pdata->cqspi;
762 void __iomem *iobase = cqspi->iobase;
763 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
764 unsigned int tshsl, tchsh, tslch, tsd2d;
765 unsigned int reg;
766 unsigned int tsclk;
767
768 /* calculate the number of ref ticks for one sclk tick */
769 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
770
771 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
772 /* this particular value must be at least one sclk */
773 if (tshsl < tsclk)
774 tshsl = tsclk;
775
776 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
777 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
778 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
779
780 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
781 << CQSPI_REG_DELAY_TSHSL_LSB;
782 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
783 << CQSPI_REG_DELAY_TCHSH_LSB;
784 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
785 << CQSPI_REG_DELAY_TSLCH_LSB;
786 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
787 << CQSPI_REG_DELAY_TSD2D_LSB;
788 writel(reg, iobase + CQSPI_REG_DELAY);
789 }
790
791 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
792 {
793 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
794 void __iomem *reg_base = cqspi->iobase;
795 u32 reg, div;
796
797 /* Recalculate the baudrate divisor based on QSPI specification. */
798 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
799
800 reg = readl(reg_base + CQSPI_REG_CONFIG);
801 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
802 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
803 writel(reg, reg_base + CQSPI_REG_CONFIG);
804 }
805
806 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
807 const bool bypass,
808 const unsigned int delay)
809 {
810 void __iomem *reg_base = cqspi->iobase;
811 unsigned int reg;
812
813 reg = readl(reg_base + CQSPI_REG_READCAPTURE);
814
815 if (bypass)
816 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
817 else
818 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
819
820 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
821 << CQSPI_REG_READCAPTURE_DELAY_LSB);
822
823 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
824 << CQSPI_REG_READCAPTURE_DELAY_LSB;
825
826 writel(reg, reg_base + CQSPI_REG_READCAPTURE);
827 }
828
829 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
830 {
831 void __iomem *reg_base = cqspi->iobase;
832 unsigned int reg;
833
834 reg = readl(reg_base + CQSPI_REG_CONFIG);
835
836 if (enable)
837 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
838 else
839 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
840
841 writel(reg, reg_base + CQSPI_REG_CONFIG);
842 }
843
844 static void cqspi_configure(struct spi_nor *nor)
845 {
846 struct cqspi_flash_pdata *f_pdata = nor->priv;
847 struct cqspi_st *cqspi = f_pdata->cqspi;
848 const unsigned int sclk = f_pdata->clk_rate;
849 int switch_cs = (cqspi->current_cs != f_pdata->cs);
850 int switch_ck = (cqspi->sclk != sclk);
851
852 if ((cqspi->current_page_size != nor->page_size) ||
853 (cqspi->current_erase_size != nor->mtd.erasesize) ||
854 (cqspi->current_addr_width != nor->addr_width))
855 switch_cs = 1;
856
857 if (switch_cs || switch_ck)
858 cqspi_controller_enable(cqspi, 0);
859
860 /* Switch chip select. */
861 if (switch_cs) {
862 cqspi->current_cs = f_pdata->cs;
863 cqspi_configure_cs_and_sizes(nor);
864 }
865
866 /* Setup baudrate divisor and delays */
867 if (switch_ck) {
868 cqspi->sclk = sclk;
869 cqspi_config_baudrate_div(cqspi);
870 cqspi_delay(nor);
871 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
872 f_pdata->read_delay);
873 }
874
875 if (switch_cs || switch_ck)
876 cqspi_controller_enable(cqspi, 1);
877 }
878
879 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
880 {
881 struct cqspi_flash_pdata *f_pdata = nor->priv;
882
883 f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
884 f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
885 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
886
887 if (read) {
888 switch (nor->read_proto) {
889 case SNOR_PROTO_1_1_1:
890 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
891 break;
892 case SNOR_PROTO_1_1_2:
893 f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
894 break;
895 case SNOR_PROTO_1_1_4:
896 f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
897 break;
898 default:
899 return -EINVAL;
900 }
901 }
902
903 cqspi_configure(nor);
904
905 return 0;
906 }
907
908 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
909 size_t len, const u_char *buf)
910 {
911 struct cqspi_flash_pdata *f_pdata = nor->priv;
912 struct cqspi_st *cqspi = f_pdata->cqspi;
913 int ret;
914
915 ret = cqspi_set_protocol(nor, 0);
916 if (ret)
917 return ret;
918
919 ret = cqspi_write_setup(nor);
920 if (ret)
921 return ret;
922
923 if (f_pdata->use_direct_mode)
924 memcpy_toio(cqspi->ahb_base + to, buf, len);
925 else
926 ret = cqspi_indirect_write_execute(nor, to, buf, len);
927 if (ret)
928 return ret;
929
930 return len;
931 }
932
933 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
934 size_t len, u_char *buf)
935 {
936 struct cqspi_flash_pdata *f_pdata = nor->priv;
937 struct cqspi_st *cqspi = f_pdata->cqspi;
938 int ret;
939
940 ret = cqspi_set_protocol(nor, 1);
941 if (ret)
942 return ret;
943
944 ret = cqspi_read_setup(nor);
945 if (ret)
946 return ret;
947
948 if (f_pdata->use_direct_mode)
949 memcpy_fromio(buf, cqspi->ahb_base + from, len);
950 else
951 ret = cqspi_indirect_read_execute(nor, buf, from, len);
952 if (ret)
953 return ret;
954
955 return len;
956 }
957
958 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
959 {
960 int ret;
961
962 ret = cqspi_set_protocol(nor, 0);
963 if (ret)
964 return ret;
965
966 /* Send write enable, then erase commands. */
967 ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
968 if (ret)
969 return ret;
970
971 /* Set up command buffer. */
972 ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
973 if (ret)
974 return ret;
975
976 return 0;
977 }
978
979 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
980 {
981 struct cqspi_flash_pdata *f_pdata = nor->priv;
982 struct cqspi_st *cqspi = f_pdata->cqspi;
983
984 mutex_lock(&cqspi->bus_mutex);
985
986 return 0;
987 }
988
989 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
990 {
991 struct cqspi_flash_pdata *f_pdata = nor->priv;
992 struct cqspi_st *cqspi = f_pdata->cqspi;
993
994 mutex_unlock(&cqspi->bus_mutex);
995 }
996
997 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
998 {
999 int ret;
1000
1001 ret = cqspi_set_protocol(nor, 0);
1002 if (!ret)
1003 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
1004
1005 return ret;
1006 }
1007
1008 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1009 {
1010 int ret;
1011
1012 ret = cqspi_set_protocol(nor, 0);
1013 if (!ret)
1014 ret = cqspi_command_write(nor, opcode, buf, len);
1015
1016 return ret;
1017 }
1018
1019 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1020 struct cqspi_flash_pdata *f_pdata,
1021 struct device_node *np)
1022 {
1023 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1024 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1025 return -ENXIO;
1026 }
1027
1028 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1029 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1030 return -ENXIO;
1031 }
1032
1033 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1034 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1035 return -ENXIO;
1036 }
1037
1038 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1039 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1040 return -ENXIO;
1041 }
1042
1043 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1044 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1045 return -ENXIO;
1046 }
1047
1048 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1049 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1050 return -ENXIO;
1051 }
1052
1053 return 0;
1054 }
1055
1056 static int cqspi_of_get_pdata(struct platform_device *pdev)
1057 {
1058 struct device_node *np = pdev->dev.of_node;
1059 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1060
1061 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1062
1063 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1064 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1065 return -ENXIO;
1066 }
1067
1068 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1069 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1070 return -ENXIO;
1071 }
1072
1073 if (of_property_read_u32(np, "cdns,trigger-address",
1074 &cqspi->trigger_address)) {
1075 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1076 return -ENXIO;
1077 }
1078
1079 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1080
1081 return 0;
1082 }
1083
1084 static void cqspi_controller_init(struct cqspi_st *cqspi)
1085 {
1086 u32 reg;
1087
1088 cqspi_controller_enable(cqspi, 0);
1089
1090 /* Configure the remap address register, no remap */
1091 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1092
1093 /* Disable all interrupts. */
1094 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1095
1096 /* Configure the SRAM split to 1:1 . */
1097 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1098
1099 /* Load indirect trigger address. */
1100 writel(cqspi->trigger_address,
1101 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1102
1103 /* Program read watermark -- 1/2 of the FIFO. */
1104 writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1105 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1106 /* Program write watermark -- 1/8 of the FIFO. */
1107 writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1108 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1109
1110 /* Enable Direct Access Controller */
1111 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1112 reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1113 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1114
1115 cqspi_controller_enable(cqspi, 1);
1116 }
1117
1118 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1119 {
1120 const struct spi_nor_hwcaps hwcaps = {
1121 .mask = SNOR_HWCAPS_READ |
1122 SNOR_HWCAPS_READ_FAST |
1123 SNOR_HWCAPS_READ_1_1_2 |
1124 SNOR_HWCAPS_READ_1_1_4 |
1125 SNOR_HWCAPS_PP,
1126 };
1127 struct platform_device *pdev = cqspi->pdev;
1128 struct device *dev = &pdev->dev;
1129 struct cqspi_flash_pdata *f_pdata;
1130 struct spi_nor *nor;
1131 struct mtd_info *mtd;
1132 unsigned int cs;
1133 int i, ret;
1134
1135 /* Get flash device data */
1136 for_each_available_child_of_node(dev->of_node, np) {
1137 ret = of_property_read_u32(np, "reg", &cs);
1138 if (ret) {
1139 dev_err(dev, "Couldn't determine chip select.\n");
1140 goto err;
1141 }
1142
1143 if (cs >= CQSPI_MAX_CHIPSELECT) {
1144 ret = -EINVAL;
1145 dev_err(dev, "Chip select %d out of range.\n", cs);
1146 goto err;
1147 }
1148
1149 f_pdata = &cqspi->f_pdata[cs];
1150 f_pdata->cqspi = cqspi;
1151 f_pdata->cs = cs;
1152
1153 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1154 if (ret)
1155 goto err;
1156
1157 nor = &f_pdata->nor;
1158 mtd = &nor->mtd;
1159
1160 mtd->priv = nor;
1161
1162 nor->dev = dev;
1163 spi_nor_set_flash_node(nor, np);
1164 nor->priv = f_pdata;
1165
1166 nor->read_reg = cqspi_read_reg;
1167 nor->write_reg = cqspi_write_reg;
1168 nor->read = cqspi_read;
1169 nor->write = cqspi_write;
1170 nor->erase = cqspi_erase;
1171 nor->prepare = cqspi_prep;
1172 nor->unprepare = cqspi_unprep;
1173
1174 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1175 dev_name(dev), cs);
1176 if (!mtd->name) {
1177 ret = -ENOMEM;
1178 goto err;
1179 }
1180
1181 ret = spi_nor_scan(nor, NULL, &hwcaps);
1182 if (ret)
1183 goto err;
1184
1185 ret = mtd_device_register(mtd, NULL, 0);
1186 if (ret)
1187 goto err;
1188
1189 f_pdata->registered = true;
1190
1191 if (mtd->size <= cqspi->ahb_size) {
1192 f_pdata->use_direct_mode = true;
1193 dev_dbg(nor->dev, "using direct mode for %s\n",
1194 mtd->name);
1195 }
1196 }
1197
1198 return 0;
1199
1200 err:
1201 for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1202 if (cqspi->f_pdata[i].registered)
1203 mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1204 return ret;
1205 }
1206
1207 static int cqspi_probe(struct platform_device *pdev)
1208 {
1209 struct device_node *np = pdev->dev.of_node;
1210 struct device *dev = &pdev->dev;
1211 struct cqspi_st *cqspi;
1212 struct resource *res;
1213 struct resource *res_ahb;
1214 unsigned long data;
1215 int ret;
1216 int irq;
1217
1218 cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1219 if (!cqspi)
1220 return -ENOMEM;
1221
1222 mutex_init(&cqspi->bus_mutex);
1223 cqspi->pdev = pdev;
1224 platform_set_drvdata(pdev, cqspi);
1225
1226 /* Obtain configuration from OF. */
1227 ret = cqspi_of_get_pdata(pdev);
1228 if (ret) {
1229 dev_err(dev, "Cannot get mandatory OF data.\n");
1230 return -ENODEV;
1231 }
1232
1233 /* Obtain QSPI clock. */
1234 cqspi->clk = devm_clk_get(dev, NULL);
1235 if (IS_ERR(cqspi->clk)) {
1236 dev_err(dev, "Cannot claim QSPI clock.\n");
1237 return PTR_ERR(cqspi->clk);
1238 }
1239
1240 /* Obtain and remap controller address. */
1241 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1242 cqspi->iobase = devm_ioremap_resource(dev, res);
1243 if (IS_ERR(cqspi->iobase)) {
1244 dev_err(dev, "Cannot remap controller address.\n");
1245 return PTR_ERR(cqspi->iobase);
1246 }
1247
1248 /* Obtain and remap AHB address. */
1249 res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1250 cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1251 if (IS_ERR(cqspi->ahb_base)) {
1252 dev_err(dev, "Cannot remap AHB address.\n");
1253 return PTR_ERR(cqspi->ahb_base);
1254 }
1255 cqspi->ahb_size = resource_size(res_ahb);
1256
1257 init_completion(&cqspi->transfer_complete);
1258
1259 /* Obtain IRQ line. */
1260 irq = platform_get_irq(pdev, 0);
1261 if (irq < 0) {
1262 dev_err(dev, "Cannot obtain IRQ.\n");
1263 return -ENXIO;
1264 }
1265
1266 pm_runtime_enable(dev);
1267 ret = pm_runtime_get_sync(dev);
1268 if (ret < 0) {
1269 pm_runtime_put_noidle(dev);
1270 return ret;
1271 }
1272
1273 ret = clk_prepare_enable(cqspi->clk);
1274 if (ret) {
1275 dev_err(dev, "Cannot enable QSPI clock.\n");
1276 goto probe_clk_failed;
1277 }
1278
1279 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1280 data = (unsigned long)of_device_get_match_data(dev);
1281 if (data & CQSPI_NEEDS_WR_DELAY)
1282 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1283 cqspi->master_ref_clk_hz);
1284
1285 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1286 pdev->name, cqspi);
1287 if (ret) {
1288 dev_err(dev, "Cannot request IRQ.\n");
1289 goto probe_irq_failed;
1290 }
1291
1292 cqspi_wait_idle(cqspi);
1293 cqspi_controller_init(cqspi);
1294 cqspi->current_cs = -1;
1295 cqspi->sclk = 0;
1296
1297 ret = cqspi_setup_flash(cqspi, np);
1298 if (ret) {
1299 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1300 goto probe_setup_failed;
1301 }
1302
1303 return ret;
1304 probe_setup_failed:
1305 cqspi_controller_enable(cqspi, 0);
1306 probe_irq_failed:
1307 clk_disable_unprepare(cqspi->clk);
1308 probe_clk_failed:
1309 pm_runtime_put_sync(dev);
1310 pm_runtime_disable(dev);
1311 return ret;
1312 }
1313
1314 static int cqspi_remove(struct platform_device *pdev)
1315 {
1316 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1317 int i;
1318
1319 for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1320 if (cqspi->f_pdata[i].registered)
1321 mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1322
1323 cqspi_controller_enable(cqspi, 0);
1324
1325 clk_disable_unprepare(cqspi->clk);
1326
1327 pm_runtime_put_sync(&pdev->dev);
1328 pm_runtime_disable(&pdev->dev);
1329
1330 return 0;
1331 }
1332
1333 #ifdef CONFIG_PM_SLEEP
1334 static int cqspi_suspend(struct device *dev)
1335 {
1336 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1337
1338 cqspi_controller_enable(cqspi, 0);
1339 return 0;
1340 }
1341
1342 static int cqspi_resume(struct device *dev)
1343 {
1344 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1345
1346 cqspi_controller_enable(cqspi, 1);
1347 return 0;
1348 }
1349
1350 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1351 .suspend = cqspi_suspend,
1352 .resume = cqspi_resume,
1353 };
1354
1355 #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops)
1356 #else
1357 #define CQSPI_DEV_PM_OPS NULL
1358 #endif
1359
1360 static const struct of_device_id cqspi_dt_ids[] = {
1361 {
1362 .compatible = "cdns,qspi-nor",
1363 .data = (void *)0,
1364 },
1365 {
1366 .compatible = "ti,k2g-qspi",
1367 .data = (void *)CQSPI_NEEDS_WR_DELAY,
1368 },
1369 { /* end of table */ }
1370 };
1371
1372 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1373
1374 static struct platform_driver cqspi_platform_driver = {
1375 .probe = cqspi_probe,
1376 .remove = cqspi_remove,
1377 .driver = {
1378 .name = CQSPI_NAME,
1379 .pm = CQSPI_DEV_PM_OPS,
1380 .of_match_table = cqspi_dt_ids,
1381 },
1382 };
1383
1384 module_platform_driver(cqspi_platform_driver);
1385
1386 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1387 MODULE_LICENSE("GPL v2");
1388 MODULE_ALIAS("platform:" CQSPI_NAME);
1389 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1390 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
Linux with added FPC-III support