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Linux 4.16.11
[linux/fpc-iii.git] / drivers / mtd / spi-nor / spi-nor.c
blobd445a4d3b77077d838233c8a90a876d13650d72d
1 /*
2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
4 *
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
7 *
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
19 #include <linux/sizes.h>
20 #include <linux/slab.h>
21
22 #include <linux/mtd/mtd.h>
23 #include <linux/of_platform.h>
24 #include <linux/spi/flash.h>
25 #include <linux/mtd/spi-nor.h>
26
27 /* Define max times to check status register before we give up. */
28
29 /*
30 * For everything but full-chip erase; probably could be much smaller, but kept
31 * around for safety for now
32 */
33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
34
35 /*
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
37 * for larger flash
38 */
39 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
40
41 #define SPI_NOR_MAX_ID_LEN 6
42 #define SPI_NOR_MAX_ADDR_WIDTH 4
43
44 struct flash_info {
45 char *name;
46
47 /*
48 * This array stores the ID bytes.
49 * The first three bytes are the JEDIC ID.
50 * JEDEC ID zero means "no ID" (mostly older chips).
51 */
52 u8 id[SPI_NOR_MAX_ID_LEN];
53 u8 id_len;
54
55 /* The size listed here is what works with SPINOR_OP_SE, which isn't
56 * necessarily called a "sector" by the vendor.
57 */
58 unsigned sector_size;
59 u16 n_sectors;
60
61 u16 page_size;
62 u16 addr_width;
63
64 u16 flags;
65 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
66 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
67 #define SST_WRITE BIT(2) /* use SST byte programming */
68 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
69 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
70 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
71 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
72 #define USE_FSR BIT(7) /* use flag status register */
73 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
74 #define SPI_NOR_HAS_TB BIT(9) /*
75 * Flash SR has Top/Bottom (TB) protect
76 * bit. Must be used with
77 * SPI_NOR_HAS_LOCK.
78 */
79 #define SPI_S3AN BIT(10) /*
80 * Xilinx Spartan 3AN In-System Flash
81 * (MFR cannot be used for probing
82 * because it has the same value as
83 * ATMEL flashes)
84 */
85 #define SPI_NOR_4B_OPCODES BIT(11) /*
86 * Use dedicated 4byte address op codes
87 * to support memory size above 128Mib.
88 */
89 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
90 #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
91 #define USE_CLSR BIT(14) /* use CLSR command */
92
93 int (*quad_enable)(struct spi_nor *nor);
94 };
95
96 #define JEDEC_MFR(info) ((info)->id[0])
97
98 static const struct flash_info *spi_nor_match_id(const char *name);
99
100 /*
101 * Read the status register, returning its value in the location
102 * Return the status register value.
103 * Returns negative if error occurred.
104 */
105 static int read_sr(struct spi_nor *nor)
106 {
107 int ret;
108 u8 val;
109
110 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
111 if (ret < 0) {
112 pr_err("error %d reading SR\n", (int) ret);
113 return ret;
114 }
115
116 return val;
117 }
118
119 /*
120 * Read the flag status register, returning its value in the location
121 * Return the status register value.
122 * Returns negative if error occurred.
123 */
124 static int read_fsr(struct spi_nor *nor)
125 {
126 int ret;
127 u8 val;
128
129 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
130 if (ret < 0) {
131 pr_err("error %d reading FSR\n", ret);
132 return ret;
133 }
134
135 return val;
136 }
137
138 /*
139 * Read configuration register, returning its value in the
140 * location. Return the configuration register value.
141 * Returns negative if error occurred.
142 */
143 static int read_cr(struct spi_nor *nor)
144 {
145 int ret;
146 u8 val;
147
148 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
149 if (ret < 0) {
150 dev_err(nor->dev, "error %d reading CR\n", ret);
151 return ret;
152 }
153
154 return val;
155 }
156
157 /*
158 * Write status register 1 byte
159 * Returns negative if error occurred.
160 */
161 static inline int write_sr(struct spi_nor *nor, u8 val)
162 {
163 nor->cmd_buf[0] = val;
164 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
165 }
166
167 /*
168 * Set write enable latch with Write Enable command.
169 * Returns negative if error occurred.
170 */
171 static inline int write_enable(struct spi_nor *nor)
172 {
173 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
174 }
175
176 /*
177 * Send write disable instruction to the chip.
178 */
179 static inline int write_disable(struct spi_nor *nor)
180 {
181 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
182 }
183
184 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
185 {
186 return mtd->priv;
187 }
188
189
190 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
191 {
192 size_t i;
193
194 for (i = 0; i < size; i++)
195 if (table[i][0] == opcode)
196 return table[i][1];
197
198 /* No conversion found, keep input op code. */
199 return opcode;
200 }
201
202 static inline u8 spi_nor_convert_3to4_read(u8 opcode)
203 {
204 static const u8 spi_nor_3to4_read[][2] = {
205 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
206 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
207 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
208 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
209 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
210 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
211
212 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
213 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
214 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
215 };
216
217 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
218 ARRAY_SIZE(spi_nor_3to4_read));
219 }
220
221 static inline u8 spi_nor_convert_3to4_program(u8 opcode)
222 {
223 static const u8 spi_nor_3to4_program[][2] = {
224 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
225 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
226 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
227 };
228
229 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
230 ARRAY_SIZE(spi_nor_3to4_program));
231 }
232
233 static inline u8 spi_nor_convert_3to4_erase(u8 opcode)
234 {
235 static const u8 spi_nor_3to4_erase[][2] = {
236 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
237 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
238 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
239 };
240
241 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
242 ARRAY_SIZE(spi_nor_3to4_erase));
243 }
244
245 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
246 const struct flash_info *info)
247 {
248 /* Do some manufacturer fixups first */
249 switch (JEDEC_MFR(info)) {
250 case SNOR_MFR_SPANSION:
251 /* No small sector erase for 4-byte command set */
252 nor->erase_opcode = SPINOR_OP_SE;
253 nor->mtd.erasesize = info->sector_size;
254 break;
255
256 default:
257 break;
258 }
259
260 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
261 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
262 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
263 }
264
265 /* Enable/disable 4-byte addressing mode. */
266 static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
267 int enable)
268 {
269 int status;
270 bool need_wren = false;
271 u8 cmd;
272
273 switch (JEDEC_MFR(info)) {
274 case SNOR_MFR_MICRON:
275 /* Some Micron need WREN command; all will accept it */
276 need_wren = true;
277 case SNOR_MFR_MACRONIX:
278 case SNOR_MFR_WINBOND:
279 if (need_wren)
280 write_enable(nor);
281
282 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
283 status = nor->write_reg(nor, cmd, NULL, 0);
284 if (need_wren)
285 write_disable(nor);
286
287 return status;
288 default:
289 /* Spansion style */
290 nor->cmd_buf[0] = enable << 7;
291 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
292 }
293 }
294
295 static int s3an_sr_ready(struct spi_nor *nor)
296 {
297 int ret;
298 u8 val;
299
300 ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
301 if (ret < 0) {
302 dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
303 return ret;
304 }
305
306 return !!(val & XSR_RDY);
307 }
308
309 static inline int spi_nor_sr_ready(struct spi_nor *nor)
310 {
311 int sr = read_sr(nor);
312 if (sr < 0)
313 return sr;
314
315 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
316 if (sr & SR_E_ERR)
317 dev_err(nor->dev, "Erase Error occurred\n");
318 else
319 dev_err(nor->dev, "Programming Error occurred\n");
320
321 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
322 return -EIO;
323 }
324
325 return !(sr & SR_WIP);
326 }
327
328 static inline int spi_nor_fsr_ready(struct spi_nor *nor)
329 {
330 int fsr = read_fsr(nor);
331 if (fsr < 0)
332 return fsr;
333
334 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
335 if (fsr & FSR_E_ERR)
336 dev_err(nor->dev, "Erase operation failed.\n");
337 else
338 dev_err(nor->dev, "Program operation failed.\n");
339
340 if (fsr & FSR_PT_ERR)
341 dev_err(nor->dev,
342 "Attempted to modify a protected sector.\n");
343
344 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
345 return -EIO;
346 }
347
348 return fsr & FSR_READY;
349 }
350
351 static int spi_nor_ready(struct spi_nor *nor)
352 {
353 int sr, fsr;
354
355 if (nor->flags & SNOR_F_READY_XSR_RDY)
356 sr = s3an_sr_ready(nor);
357 else
358 sr = spi_nor_sr_ready(nor);
359 if (sr < 0)
360 return sr;
361 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
362 if (fsr < 0)
363 return fsr;
364 return sr && fsr;
365 }
366
367 /*
368 * Service routine to read status register until ready, or timeout occurs.
369 * Returns non-zero if error.
370 */
371 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
372 unsigned long timeout_jiffies)
373 {
374 unsigned long deadline;
375 int timeout = 0, ret;
376
377 deadline = jiffies + timeout_jiffies;
378
379 while (!timeout) {
380 if (time_after_eq(jiffies, deadline))
381 timeout = 1;
382
383 ret = spi_nor_ready(nor);
384 if (ret < 0)
385 return ret;
386 if (ret)
387 return 0;
388
389 cond_resched();
390 }
391
392 dev_err(nor->dev, "flash operation timed out\n");
393
394 return -ETIMEDOUT;
395 }
396
397 static int spi_nor_wait_till_ready(struct spi_nor *nor)
398 {
399 return spi_nor_wait_till_ready_with_timeout(nor,
400 DEFAULT_READY_WAIT_JIFFIES);
401 }
402
403 /*
404 * Erase the whole flash memory
405 *
406 * Returns 0 if successful, non-zero otherwise.
407 */
408 static int erase_chip(struct spi_nor *nor)
409 {
410 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
411
412 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
413 }
414
415 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
416 {
417 int ret = 0;
418
419 mutex_lock(&nor->lock);
420
421 if (nor->prepare) {
422 ret = nor->prepare(nor, ops);
423 if (ret) {
424 dev_err(nor->dev, "failed in the preparation.\n");
425 mutex_unlock(&nor->lock);
426 return ret;
427 }
428 }
429 return ret;
430 }
431
432 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
433 {
434 if (nor->unprepare)
435 nor->unprepare(nor, ops);
436 mutex_unlock(&nor->lock);
437 }
438
439 /*
440 * This code converts an address to the Default Address Mode, that has non
441 * power of two page sizes. We must support this mode because it is the default
442 * mode supported by Xilinx tools, it can access the whole flash area and
443 * changing over to the Power-of-two mode is irreversible and corrupts the
444 * original data.
445 * Addr can safely be unsigned int, the biggest S3AN device is smaller than
446 * 4 MiB.
447 */
448 static loff_t spi_nor_s3an_addr_convert(struct spi_nor *nor, unsigned int addr)
449 {
450 unsigned int offset;
451 unsigned int page;
452
453 offset = addr % nor->page_size;
454 page = addr / nor->page_size;
455 page <<= (nor->page_size > 512) ? 10 : 9;
456
457 return page | offset;
458 }
459
460 /*
461 * Initiate the erasure of a single sector
462 */
463 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
464 {
465 u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
466 int i;
467
468 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
469 addr = spi_nor_s3an_addr_convert(nor, addr);
470
471 if (nor->erase)
472 return nor->erase(nor, addr);
473
474 /*
475 * Default implementation, if driver doesn't have a specialized HW
476 * control
477 */
478 for (i = nor->addr_width - 1; i >= 0; i--) {
479 buf[i] = addr & 0xff;
480 addr >>= 8;
481 }
482
483 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
484 }
485
486 /*
487 * Erase an address range on the nor chip. The address range may extend
488 * one or more erase sectors. Return an error is there is a problem erasing.
489 */
490 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
491 {
492 struct spi_nor *nor = mtd_to_spi_nor(mtd);
493 u32 addr, len;
494 uint32_t rem;
495 int ret;
496
497 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
498 (long long)instr->len);
499
500 div_u64_rem(instr->len, mtd->erasesize, &rem);
501 if (rem)
502 return -EINVAL;
503
504 addr = instr->addr;
505 len = instr->len;
506
507 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
508 if (ret)
509 return ret;
510
511 /* whole-chip erase? */
512 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
513 unsigned long timeout;
514
515 write_enable(nor);
516
517 if (erase_chip(nor)) {
518 ret = -EIO;
519 goto erase_err;
520 }
521
522 /*
523 * Scale the timeout linearly with the size of the flash, with
524 * a minimum calibrated to an old 2MB flash. We could try to
525 * pull these from CFI/SFDP, but these values should be good
526 * enough for now.
527 */
528 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
529 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
530 (unsigned long)(mtd->size / SZ_2M));
531 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
532 if (ret)
533 goto erase_err;
534
535 /* REVISIT in some cases we could speed up erasing large regions
536 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
537 * to use "small sector erase", but that's not always optimal.
538 */
539
540 /* "sector"-at-a-time erase */
541 } else {
542 while (len) {
543 write_enable(nor);
544
545 ret = spi_nor_erase_sector(nor, addr);
546 if (ret)
547 goto erase_err;
548
549 addr += mtd->erasesize;
550 len -= mtd->erasesize;
551
552 ret = spi_nor_wait_till_ready(nor);
553 if (ret)
554 goto erase_err;
555 }
556 }
557
558 write_disable(nor);
559
560 erase_err:
561 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
562
563 instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE;
564 mtd_erase_callback(instr);
565
566 return ret;
567 }
568
569 /* Write status register and ensure bits in mask match written values */
570 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
571 {
572 int ret;
573
574 write_enable(nor);
575 ret = write_sr(nor, status_new);
576 if (ret)
577 return ret;
578
579 ret = spi_nor_wait_till_ready(nor);
580 if (ret)
581 return ret;
582
583 ret = read_sr(nor);
584 if (ret < 0)
585 return ret;
586
587 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
588 }
589
590 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
591 uint64_t *len)
592 {
593 struct mtd_info *mtd = &nor->mtd;
594 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
595 int shift = ffs(mask) - 1;
596 int pow;
597
598 if (!(sr & mask)) {
599 /* No protection */
600 *ofs = 0;
601 *len = 0;
602 } else {
603 pow = ((sr & mask) ^ mask) >> shift;
604 *len = mtd->size >> pow;
605 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
606 *ofs = 0;
607 else
608 *ofs = mtd->size - *len;
609 }
610 }
611
612 /*
613 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
614 * @locked is false); 0 otherwise
615 */
616 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
617 u8 sr, bool locked)
618 {
619 loff_t lock_offs;
620 uint64_t lock_len;
621
622 if (!len)
623 return 1;
624
625 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
626
627 if (locked)
628 /* Requested range is a sub-range of locked range */
629 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
630 else
631 /* Requested range does not overlap with locked range */
632 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
633 }
634
635 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
636 u8 sr)
637 {
638 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
639 }
640
641 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
642 u8 sr)
643 {
644 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
645 }
646
647 /*
648 * Lock a region of the flash. Compatible with ST Micro and similar flash.
649 * Supports the block protection bits BP{0,1,2} in the status register
650 * (SR). Does not support these features found in newer SR bitfields:
651 * - SEC: sector/block protect - only handle SEC=0 (block protect)
652 * - CMP: complement protect - only support CMP=0 (range is not complemented)
653 *
654 * Support for the following is provided conditionally for some flash:
655 * - TB: top/bottom protect
656 *
657 * Sample table portion for 8MB flash (Winbond w25q64fw):
658 *
659 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
660 * --------------------------------------------------------------------------
661 * X | X | 0 | 0 | 0 | NONE | NONE
662 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
663 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
664 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
665 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
666 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
667 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
668 * X | X | 1 | 1 | 1 | 8 MB | ALL
669 * ------|-------|-------|-------|-------|---------------|-------------------
670 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
671 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
672 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
673 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
674 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
675 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
676 *
677 * Returns negative on errors, 0 on success.
678 */
679 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
680 {
681 struct mtd_info *mtd = &nor->mtd;
682 int status_old, status_new;
683 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
684 u8 shift = ffs(mask) - 1, pow, val;
685 loff_t lock_len;
686 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
687 bool use_top;
688
689 status_old = read_sr(nor);
690 if (status_old < 0)
691 return status_old;
692
693 /* If nothing in our range is unlocked, we don't need to do anything */
694 if (stm_is_locked_sr(nor, ofs, len, status_old))
695 return 0;
696
697 /* If anything below us is unlocked, we can't use 'bottom' protection */
698 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
699 can_be_bottom = false;
700
701 /* If anything above us is unlocked, we can't use 'top' protection */
702 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
703 status_old))
704 can_be_top = false;
705
706 if (!can_be_bottom && !can_be_top)
707 return -EINVAL;
708
709 /* Prefer top, if both are valid */
710 use_top = can_be_top;
711
712 /* lock_len: length of region that should end up locked */
713 if (use_top)
714 lock_len = mtd->size - ofs;
715 else
716 lock_len = ofs + len;
717
718 /*
719 * Need smallest pow such that:
720 *
721 * 1 / (2^pow) <= (len / size)
722 *
723 * so (assuming power-of-2 size) we do:
724 *
725 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
726 */
727 pow = ilog2(mtd->size) - ilog2(lock_len);
728 val = mask - (pow << shift);
729 if (val & ~mask)
730 return -EINVAL;
731 /* Don't "lock" with no region! */
732 if (!(val & mask))
733 return -EINVAL;
734
735 status_new = (status_old & ~mask & ~SR_TB) | val;
736
737 /* Disallow further writes if WP pin is asserted */
738 status_new |= SR_SRWD;
739
740 if (!use_top)
741 status_new |= SR_TB;
742
743 /* Don't bother if they're the same */
744 if (status_new == status_old)
745 return 0;
746
747 /* Only modify protection if it will not unlock other areas */
748 if ((status_new & mask) < (status_old & mask))
749 return -EINVAL;
750
751 return write_sr_and_check(nor, status_new, mask);
752 }
753
754 /*
755 * Unlock a region of the flash. See stm_lock() for more info
756 *
757 * Returns negative on errors, 0 on success.
758 */
759 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
760 {
761 struct mtd_info *mtd = &nor->mtd;
762 int status_old, status_new;
763 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
764 u8 shift = ffs(mask) - 1, pow, val;
765 loff_t lock_len;
766 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
767 bool use_top;
768
769 status_old = read_sr(nor);
770 if (status_old < 0)
771 return status_old;
772
773 /* If nothing in our range is locked, we don't need to do anything */
774 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
775 return 0;
776
777 /* If anything below us is locked, we can't use 'top' protection */
778 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
779 can_be_top = false;
780
781 /* If anything above us is locked, we can't use 'bottom' protection */
782 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
783 status_old))
784 can_be_bottom = false;
785
786 if (!can_be_bottom && !can_be_top)
787 return -EINVAL;
788
789 /* Prefer top, if both are valid */
790 use_top = can_be_top;
791
792 /* lock_len: length of region that should remain locked */
793 if (use_top)
794 lock_len = mtd->size - (ofs + len);
795 else
796 lock_len = ofs;
797
798 /*
799 * Need largest pow such that:
800 *
801 * 1 / (2^pow) >= (len / size)
802 *
803 * so (assuming power-of-2 size) we do:
804 *
805 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
806 */
807 pow = ilog2(mtd->size) - order_base_2(lock_len);
808 if (lock_len == 0) {
809 val = 0; /* fully unlocked */
810 } else {
811 val = mask - (pow << shift);
812 /* Some power-of-two sizes are not supported */
813 if (val & ~mask)
814 return -EINVAL;
815 }
816
817 status_new = (status_old & ~mask & ~SR_TB) | val;
818
819 /* Don't protect status register if we're fully unlocked */
820 if (lock_len == 0)
821 status_new &= ~SR_SRWD;
822
823 if (!use_top)
824 status_new |= SR_TB;
825
826 /* Don't bother if they're the same */
827 if (status_new == status_old)
828 return 0;
829
830 /* Only modify protection if it will not lock other areas */
831 if ((status_new & mask) > (status_old & mask))
832 return -EINVAL;
833
834 return write_sr_and_check(nor, status_new, mask);
835 }
836
837 /*
838 * Check if a region of the flash is (completely) locked. See stm_lock() for
839 * more info.
840 *
841 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
842 * negative on errors.
843 */
844 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
845 {
846 int status;
847
848 status = read_sr(nor);
849 if (status < 0)
850 return status;
851
852 return stm_is_locked_sr(nor, ofs, len, status);
853 }
854
855 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
856 {
857 struct spi_nor *nor = mtd_to_spi_nor(mtd);
858 int ret;
859
860 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
861 if (ret)
862 return ret;
863
864 ret = nor->flash_lock(nor, ofs, len);
865
866 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
867 return ret;
868 }
869
870 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
871 {
872 struct spi_nor *nor = mtd_to_spi_nor(mtd);
873 int ret;
874
875 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
876 if (ret)
877 return ret;
878
879 ret = nor->flash_unlock(nor, ofs, len);
880
881 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
882 return ret;
883 }
884
885 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
886 {
887 struct spi_nor *nor = mtd_to_spi_nor(mtd);
888 int ret;
889
890 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
891 if (ret)
892 return ret;
893
894 ret = nor->flash_is_locked(nor, ofs, len);
895
896 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
897 return ret;
898 }
899
900 static int macronix_quad_enable(struct spi_nor *nor);
901
902 /* Used when the "_ext_id" is two bytes at most */
903 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
904 .id = { \
905 ((_jedec_id) >> 16) & 0xff, \
906 ((_jedec_id) >> 8) & 0xff, \
907 (_jedec_id) & 0xff, \
908 ((_ext_id) >> 8) & 0xff, \
909 (_ext_id) & 0xff, \
910 }, \
911 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
912 .sector_size = (_sector_size), \
913 .n_sectors = (_n_sectors), \
914 .page_size = 256, \
915 .flags = (_flags),
916
917 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
918 .id = { \
919 ((_jedec_id) >> 16) & 0xff, \
920 ((_jedec_id) >> 8) & 0xff, \
921 (_jedec_id) & 0xff, \
922 ((_ext_id) >> 16) & 0xff, \
923 ((_ext_id) >> 8) & 0xff, \
924 (_ext_id) & 0xff, \
925 }, \
926 .id_len = 6, \
927 .sector_size = (_sector_size), \
928 .n_sectors = (_n_sectors), \
929 .page_size = 256, \
930 .flags = (_flags),
931
932 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
933 .sector_size = (_sector_size), \
934 .n_sectors = (_n_sectors), \
935 .page_size = (_page_size), \
936 .addr_width = (_addr_width), \
937 .flags = (_flags),
938
939 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
940 .id = { \
941 ((_jedec_id) >> 16) & 0xff, \
942 ((_jedec_id) >> 8) & 0xff, \
943 (_jedec_id) & 0xff \
944 }, \
945 .id_len = 3, \
946 .sector_size = (8*_page_size), \
947 .n_sectors = (_n_sectors), \
948 .page_size = _page_size, \
949 .addr_width = 3, \
950 .flags = SPI_NOR_NO_FR | SPI_S3AN,
951
952 /* NOTE: double check command sets and memory organization when you add
953 * more nor chips. This current list focusses on newer chips, which
954 * have been converging on command sets which including JEDEC ID.
955 *
956 * All newly added entries should describe *hardware* and should use SECT_4K
957 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
958 * scenarios excluding small sectors there is config option that can be
959 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
960 * For historical (and compatibility) reasons (before we got above config) some
961 * old entries may be missing 4K flag.
962 */
963 static const struct flash_info spi_nor_ids[] = {
964 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
965 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
966 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
967
968 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
969 { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
970 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
971 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
972
973 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
974 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
975 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
976 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
977
978 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
979
980 /* EON -- en25xxx */
981 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
982 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
983 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
984 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
985 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
986 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
987 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
988 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
989
990 /* ESMT */
991 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
992 { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
993 { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
994
995 /* Everspin */
996 { "mr25h128", CAT25_INFO( 16 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
997 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
998 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
999 { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1000
1001 /* Fujitsu */
1002 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
1003
1004 /* GigaDevice */
1005 {
1006 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
1007 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1008 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1009 },
1010 {
1011 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
1012 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1013 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1014 },
1015 {
1016 "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
1017 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1018 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1019 },
1020 {
1021 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
1022 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1023 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1024 },
1025 {
1026 "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
1027 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1028 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1029 },
1030 {
1031 "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
1032 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1033 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1034 },
1035 {
1036 "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
1037 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1038 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1039 .quad_enable = macronix_quad_enable,
1040 },
1041
1042 /* Intel/Numonyx -- xxxs33b */
1043 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
1044 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
1045 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
1046
1047 /* ISSI */
1048 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
1049 { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
1050 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1051 { "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16,
1052 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1053 { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
1054 SECT_4K | SPI_NOR_DUAL_READ) },
1055
1056 /* Macronix */
1057 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
1058 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
1059 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
1060 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
1061 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
1062 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
1063 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
1064 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
1065 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
1066 { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
1067 { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
1068 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
1069 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
1070 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
1071 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1072 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
1073 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
1074 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1075 { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1076 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1077 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
1078
1079 /* Micron */
1080 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
1081 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1082 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1083 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
1084 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
1085 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
1086 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
1087 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1088 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
1089 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
1090 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
1091 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1092 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1093
1094 /* PMC */
1095 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
1096 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
1097 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
1098
1099 /* Spansion/Cypress -- single (large) sector size only, at least
1100 * for the chips listed here (without boot sectors).
1101 */
1102 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1103 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1104 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
1105 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1106 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1107 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
1108 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
1109 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
1110 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1111 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1112 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1113 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
1114 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
1115 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
1116 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
1117 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
1118 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1119 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1120 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1121 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1122 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1123 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
1124 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
1125 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
1126 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
1127 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1128 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1129 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1130
1131 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
1132 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1133 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1134 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
1135 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
1136 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
1137 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
1138 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
1139 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
1140 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
1141 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
1142 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1143 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1144 { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1145
1146 /* ST Microelectronics -- newer production may have feature updates */
1147 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
1148 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
1149 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
1150 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
1151 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
1152 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
1153 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
1154 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
1155 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
1156
1157 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
1158 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
1159 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
1160 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
1161 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
1162 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
1163 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
1164 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
1165 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
1166
1167 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
1168 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
1169 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
1170
1171 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
1172 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
1173 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
1174
1175 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
1176 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
1177 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
1178 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
1179 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
1180 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
1181
1182 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
1183 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
1184 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
1185 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
1186 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
1187 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
1188 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
1189 {
1190 "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
1191 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1192 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1193 },
1194 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
1195 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
1196 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
1197 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
1198 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
1199 {
1200 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
1201 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1202 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1203 },
1204 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
1205 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1206 {
1207 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
1208 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1209 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1210 },
1211 {
1212 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
1213 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1214 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1215 },
1216 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
1217 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
1218 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1219 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1220 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
1221 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
1222
1223 /* Catalyst / On Semiconductor -- non-JEDEC */
1224 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1225 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1226 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1227 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1228 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1229
1230 /* Xilinx S3AN Internal Flash */
1231 { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
1232 { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
1233 { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
1234 { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
1235 { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
1236 { },
1237 };
1238
1239 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
1240 {
1241 int tmp;
1242 u8 id[SPI_NOR_MAX_ID_LEN];
1243 const struct flash_info *info;
1244
1245 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
1246 if (tmp < 0) {
1247 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
1248 return ERR_PTR(tmp);
1249 }
1250
1251 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
1252 info = &spi_nor_ids[tmp];
1253 if (info->id_len) {
1254 if (!memcmp(info->id, id, info->id_len))
1255 return &spi_nor_ids[tmp];
1256 }
1257 }
1258 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1259 id[0], id[1], id[2]);
1260 return ERR_PTR(-ENODEV);
1261 }
1262
1263 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1264 size_t *retlen, u_char *buf)
1265 {
1266 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1267 int ret;
1268
1269 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1270
1271 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
1272 if (ret)
1273 return ret;
1274
1275 while (len) {
1276 loff_t addr = from;
1277
1278 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
1279 addr = spi_nor_s3an_addr_convert(nor, addr);
1280
1281 ret = nor->read(nor, addr, len, buf);
1282 if (ret == 0) {
1283 /* We shouldn't see 0-length reads */
1284 ret = -EIO;
1285 goto read_err;
1286 }
1287 if (ret < 0)
1288 goto read_err;
1289
1290 WARN_ON(ret > len);
1291 *retlen += ret;
1292 buf += ret;
1293 from += ret;
1294 len -= ret;
1295 }
1296 ret = 0;
1297
1298 read_err:
1299 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
1300 return ret;
1301 }
1302
1303 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1304 size_t *retlen, const u_char *buf)
1305 {
1306 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1307 size_t actual;
1308 int ret;
1309
1310 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1311
1312 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1313 if (ret)
1314 return ret;
1315
1316 write_enable(nor);
1317
1318 nor->sst_write_second = false;
1319
1320 actual = to % 2;
1321 /* Start write from odd address. */
1322 if (actual) {
1323 nor->program_opcode = SPINOR_OP_BP;
1324
1325 /* write one byte. */
1326 ret = nor->write(nor, to, 1, buf);
1327 if (ret < 0)
1328 goto sst_write_err;
1329 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1330 (int)ret);
1331 ret = spi_nor_wait_till_ready(nor);
1332 if (ret)
1333 goto sst_write_err;
1334 }
1335 to += actual;
1336
1337 /* Write out most of the data here. */
1338 for (; actual < len - 1; actual += 2) {
1339 nor->program_opcode = SPINOR_OP_AAI_WP;
1340
1341 /* write two bytes. */
1342 ret = nor->write(nor, to, 2, buf + actual);
1343 if (ret < 0)
1344 goto sst_write_err;
1345 WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
1346 (int)ret);
1347 ret = spi_nor_wait_till_ready(nor);
1348 if (ret)
1349 goto sst_write_err;
1350 to += 2;
1351 nor->sst_write_second = true;
1352 }
1353 nor->sst_write_second = false;
1354
1355 write_disable(nor);
1356 ret = spi_nor_wait_till_ready(nor);
1357 if (ret)
1358 goto sst_write_err;
1359
1360 /* Write out trailing byte if it exists. */
1361 if (actual != len) {
1362 write_enable(nor);
1363
1364 nor->program_opcode = SPINOR_OP_BP;
1365 ret = nor->write(nor, to, 1, buf + actual);
1366 if (ret < 0)
1367 goto sst_write_err;
1368 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1369 (int)ret);
1370 ret = spi_nor_wait_till_ready(nor);
1371 if (ret)
1372 goto sst_write_err;
1373 write_disable(nor);
1374 actual += 1;
1375 }
1376 sst_write_err:
1377 *retlen += actual;
1378 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1379 return ret;
1380 }
1381
1382 /*
1383 * Write an address range to the nor chip. Data must be written in
1384 * FLASH_PAGESIZE chunks. The address range may be any size provided
1385 * it is within the physical boundaries.
1386 */
1387 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1388 size_t *retlen, const u_char *buf)
1389 {
1390 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1391 size_t page_offset, page_remain, i;
1392 ssize_t ret;
1393
1394 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1395
1396 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1397 if (ret)
1398 return ret;
1399
1400 for (i = 0; i < len; ) {
1401 ssize_t written;
1402 loff_t addr = to + i;
1403
1404 /*
1405 * If page_size is a power of two, the offset can be quickly
1406 * calculated with an AND operation. On the other cases we
1407 * need to do a modulus operation (more expensive).
1408 * Power of two numbers have only one bit set and we can use
1409 * the instruction hweight32 to detect if we need to do a
1410 * modulus (do_div()) or not.
1411 */
1412 if (hweight32(nor->page_size) == 1) {
1413 page_offset = addr & (nor->page_size - 1);
1414 } else {
1415 uint64_t aux = addr;
1416
1417 page_offset = do_div(aux, nor->page_size);
1418 }
1419 /* the size of data remaining on the first page */
1420 page_remain = min_t(size_t,
1421 nor->page_size - page_offset, len - i);
1422
1423 if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
1424 addr = spi_nor_s3an_addr_convert(nor, addr);
1425
1426 write_enable(nor);
1427 ret = nor->write(nor, addr, page_remain, buf + i);
1428 if (ret < 0)
1429 goto write_err;
1430 written = ret;
1431
1432 ret = spi_nor_wait_till_ready(nor);
1433 if (ret)
1434 goto write_err;
1435 *retlen += written;
1436 i += written;
1437 if (written != page_remain) {
1438 dev_err(nor->dev,
1439 "While writing %zu bytes written %zd bytes\n",
1440 page_remain, written);
1441 ret = -EIO;
1442 goto write_err;
1443 }
1444 }
1445
1446 write_err:
1447 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1448 return ret;
1449 }
1450
1451 /**
1452 * macronix_quad_enable() - set QE bit in Status Register.
1453 * @nor: pointer to a 'struct spi_nor'
1454 *
1455 * Set the Quad Enable (QE) bit in the Status Register.
1456 *
1457 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1458 *
1459 * Return: 0 on success, -errno otherwise.
1460 */
1461 static int macronix_quad_enable(struct spi_nor *nor)
1462 {
1463 int ret, val;
1464
1465 val = read_sr(nor);
1466 if (val < 0)
1467 return val;
1468 if (val & SR_QUAD_EN_MX)
1469 return 0;
1470
1471 write_enable(nor);
1472
1473 write_sr(nor, val | SR_QUAD_EN_MX);
1474
1475 ret = spi_nor_wait_till_ready(nor);
1476 if (ret)
1477 return ret;
1478
1479 ret = read_sr(nor);
1480 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1481 dev_err(nor->dev, "Macronix Quad bit not set\n");
1482 return -EINVAL;
1483 }
1484
1485 return 0;
1486 }
1487
1488 /*
1489 * Write status Register and configuration register with 2 bytes
1490 * The first byte will be written to the status register, while the
1491 * second byte will be written to the configuration register.
1492 * Return negative if error occurred.
1493 */
1494 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1495 {
1496 int ret;
1497
1498 write_enable(nor);
1499
1500 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1501 if (ret < 0) {
1502 dev_err(nor->dev,
1503 "error while writing configuration register\n");
1504 return -EINVAL;
1505 }
1506
1507 ret = spi_nor_wait_till_ready(nor);
1508 if (ret) {
1509 dev_err(nor->dev,
1510 "timeout while writing configuration register\n");
1511 return ret;
1512 }
1513
1514 return 0;
1515 }
1516
1517 /**
1518 * spansion_quad_enable() - set QE bit in Configuraiton Register.
1519 * @nor: pointer to a 'struct spi_nor'
1520 *
1521 * Set the Quad Enable (QE) bit in the Configuration Register.
1522 * This function is kept for legacy purpose because it has been used for a
1523 * long time without anybody complaining but it should be considered as
1524 * deprecated and maybe buggy.
1525 * First, this function doesn't care about the previous values of the Status
1526 * and Configuration Registers when it sets the QE bit (bit 1) in the
1527 * Configuration Register: all other bits are cleared, which may have unwanted
1528 * side effects like removing some block protections.
1529 * Secondly, it uses the Read Configuration Register (35h) instruction though
1530 * some very old and few memories don't support this instruction. If a pull-up
1531 * resistor is present on the MISO/IO1 line, we might still be able to pass the
1532 * "read back" test because the QSPI memory doesn't recognize the command,
1533 * so leaves the MISO/IO1 line state unchanged, hence read_cr() returns 0xFF.
1534 *
1535 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1536 * memories.
1537 *
1538 * Return: 0 on success, -errno otherwise.
1539 */
1540 static int spansion_quad_enable(struct spi_nor *nor)
1541 {
1542 u8 sr_cr[2] = {0, CR_QUAD_EN_SPAN};
1543 int ret;
1544
1545 ret = write_sr_cr(nor, sr_cr);
1546 if (ret)
1547 return ret;
1548
1549 /* read back and check it */
1550 ret = read_cr(nor);
1551 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1552 dev_err(nor->dev, "Spansion Quad bit not set\n");
1553 return -EINVAL;
1554 }
1555
1556 return 0;
1557 }
1558
1559 /**
1560 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1561 * @nor: pointer to a 'struct spi_nor'
1562 *
1563 * Set the Quad Enable (QE) bit in the Configuration Register.
1564 * This function should be used with QSPI memories not supporting the Read
1565 * Configuration Register (35h) instruction.
1566 *
1567 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1568 * memories.
1569 *
1570 * Return: 0 on success, -errno otherwise.
1571 */
1572 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1573 {
1574 u8 sr_cr[2];
1575 int ret;
1576
1577 /* Keep the current value of the Status Register. */
1578 ret = read_sr(nor);
1579 if (ret < 0) {
1580 dev_err(nor->dev, "error while reading status register\n");
1581 return -EINVAL;
1582 }
1583 sr_cr[0] = ret;
1584 sr_cr[1] = CR_QUAD_EN_SPAN;
1585
1586 return write_sr_cr(nor, sr_cr);
1587 }
1588
1589 /**
1590 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1591 * @nor: pointer to a 'struct spi_nor'
1592 *
1593 * Set the Quad Enable (QE) bit in the Configuration Register.
1594 * This function should be used with QSPI memories supporting the Read
1595 * Configuration Register (35h) instruction.
1596 *
1597 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1598 * memories.
1599 *
1600 * Return: 0 on success, -errno otherwise.
1601 */
1602 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1603 {
1604 struct device *dev = nor->dev;
1605 u8 sr_cr[2];
1606 int ret;
1607
1608 /* Check current Quad Enable bit value. */
1609 ret = read_cr(nor);
1610 if (ret < 0) {
1611 dev_err(dev, "error while reading configuration register\n");
1612 return -EINVAL;
1613 }
1614
1615 if (ret & CR_QUAD_EN_SPAN)
1616 return 0;
1617
1618 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1619
1620 /* Keep the current value of the Status Register. */
1621 ret = read_sr(nor);
1622 if (ret < 0) {
1623 dev_err(dev, "error while reading status register\n");
1624 return -EINVAL;
1625 }
1626 sr_cr[0] = ret;
1627
1628 ret = write_sr_cr(nor, sr_cr);
1629 if (ret)
1630 return ret;
1631
1632 /* Read back and check it. */
1633 ret = read_cr(nor);
1634 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1635 dev_err(nor->dev, "Spansion Quad bit not set\n");
1636 return -EINVAL;
1637 }
1638
1639 return 0;
1640 }
1641
1642 /**
1643 * sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1644 * @nor: pointer to a 'struct spi_nor'
1645 *
1646 * Set the Quad Enable (QE) bit in the Status Register 2.
1647 *
1648 * This is one of the procedures to set the QE bit described in the SFDP
1649 * (JESD216 rev B) specification but no manufacturer using this procedure has
1650 * been identified yet, hence the name of the function.
1651 *
1652 * Return: 0 on success, -errno otherwise.
1653 */
1654 static int sr2_bit7_quad_enable(struct spi_nor *nor)
1655 {
1656 u8 sr2;
1657 int ret;
1658
1659 /* Check current Quad Enable bit value. */
1660 ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
1661 if (ret)
1662 return ret;
1663 if (sr2 & SR2_QUAD_EN_BIT7)
1664 return 0;
1665
1666 /* Update the Quad Enable bit. */
1667 sr2 |= SR2_QUAD_EN_BIT7;
1668
1669 write_enable(nor);
1670
1671 ret = nor->write_reg(nor, SPINOR_OP_WRSR2, &sr2, 1);
1672 if (ret < 0) {
1673 dev_err(nor->dev, "error while writing status register 2\n");
1674 return -EINVAL;
1675 }
1676
1677 ret = spi_nor_wait_till_ready(nor);
1678 if (ret < 0) {
1679 dev_err(nor->dev, "timeout while writing status register 2\n");
1680 return ret;
1681 }
1682
1683 /* Read back and check it. */
1684 ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
1685 if (!(ret > 0 && (sr2 & SR2_QUAD_EN_BIT7))) {
1686 dev_err(nor->dev, "SR2 Quad bit not set\n");
1687 return -EINVAL;
1688 }
1689
1690 return 0;
1691 }
1692
1693 static int spi_nor_check(struct spi_nor *nor)
1694 {
1695 if (!nor->dev || !nor->read || !nor->write ||
1696 !nor->read_reg || !nor->write_reg) {
1697 pr_err("spi-nor: please fill all the necessary fields!\n");
1698 return -EINVAL;
1699 }
1700
1701 return 0;
1702 }
1703
1704 static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor)
1705 {
1706 int ret;
1707 u8 val;
1708
1709 ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
1710 if (ret < 0) {
1711 dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
1712 return ret;
1713 }
1714
1715 nor->erase_opcode = SPINOR_OP_XSE;
1716 nor->program_opcode = SPINOR_OP_XPP;
1717 nor->read_opcode = SPINOR_OP_READ;
1718 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
1719
1720 /*
1721 * This flashes have a page size of 264 or 528 bytes (known as
1722 * Default addressing mode). It can be changed to a more standard
1723 * Power of two mode where the page size is 256/512. This comes
1724 * with a price: there is 3% less of space, the data is corrupted
1725 * and the page size cannot be changed back to default addressing
1726 * mode.
1727 *
1728 * The current addressing mode can be read from the XRDSR register
1729 * and should not be changed, because is a destructive operation.
1730 */
1731 if (val & XSR_PAGESIZE) {
1732 /* Flash in Power of 2 mode */
1733 nor->page_size = (nor->page_size == 264) ? 256 : 512;
1734 nor->mtd.writebufsize = nor->page_size;
1735 nor->mtd.size = 8 * nor->page_size * info->n_sectors;
1736 nor->mtd.erasesize = 8 * nor->page_size;
1737 } else {
1738 /* Flash in Default addressing mode */
1739 nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT;
1740 }
1741
1742 return 0;
1743 }
1744
1745 struct spi_nor_read_command {
1746 u8 num_mode_clocks;
1747 u8 num_wait_states;
1748 u8 opcode;
1749 enum spi_nor_protocol proto;
1750 };
1751
1752 struct spi_nor_pp_command {
1753 u8 opcode;
1754 enum spi_nor_protocol proto;
1755 };
1756
1757 enum spi_nor_read_command_index {
1758 SNOR_CMD_READ,
1759 SNOR_CMD_READ_FAST,
1760 SNOR_CMD_READ_1_1_1_DTR,
1761
1762 /* Dual SPI */
1763 SNOR_CMD_READ_1_1_2,
1764 SNOR_CMD_READ_1_2_2,
1765 SNOR_CMD_READ_2_2_2,
1766 SNOR_CMD_READ_1_2_2_DTR,
1767
1768 /* Quad SPI */
1769 SNOR_CMD_READ_1_1_4,
1770 SNOR_CMD_READ_1_4_4,
1771 SNOR_CMD_READ_4_4_4,
1772 SNOR_CMD_READ_1_4_4_DTR,
1773
1774 /* Octo SPI */
1775 SNOR_CMD_READ_1_1_8,
1776 SNOR_CMD_READ_1_8_8,
1777 SNOR_CMD_READ_8_8_8,
1778 SNOR_CMD_READ_1_8_8_DTR,
1779
1780 SNOR_CMD_READ_MAX
1781 };
1782
1783 enum spi_nor_pp_command_index {
1784 SNOR_CMD_PP,
1785
1786 /* Quad SPI */
1787 SNOR_CMD_PP_1_1_4,
1788 SNOR_CMD_PP_1_4_4,
1789 SNOR_CMD_PP_4_4_4,
1790
1791 /* Octo SPI */
1792 SNOR_CMD_PP_1_1_8,
1793 SNOR_CMD_PP_1_8_8,
1794 SNOR_CMD_PP_8_8_8,
1795
1796 SNOR_CMD_PP_MAX
1797 };
1798
1799 struct spi_nor_flash_parameter {
1800 u64 size;
1801 u32 page_size;
1802
1803 struct spi_nor_hwcaps hwcaps;
1804 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
1805 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
1806
1807 int (*quad_enable)(struct spi_nor *nor);
1808 };
1809
1810 static void
1811 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1812 u8 num_mode_clocks,
1813 u8 num_wait_states,
1814 u8 opcode,
1815 enum spi_nor_protocol proto)
1816 {
1817 read->num_mode_clocks = num_mode_clocks;
1818 read->num_wait_states = num_wait_states;
1819 read->opcode = opcode;
1820 read->proto = proto;
1821 }
1822
1823 static void
1824 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
1825 u8 opcode,
1826 enum spi_nor_protocol proto)
1827 {
1828 pp->opcode = opcode;
1829 pp->proto = proto;
1830 }
1831
1832 /*
1833 * Serial Flash Discoverable Parameters (SFDP) parsing.
1834 */
1835
1836 /**
1837 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
1838 * @nor: pointer to a 'struct spi_nor'
1839 * @addr: offset in the SFDP area to start reading data from
1840 * @len: number of bytes to read
1841 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
1842 *
1843 * Whatever the actual numbers of bytes for address and dummy cycles are
1844 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
1845 * followed by a 3-byte address and 8 dummy clock cycles.
1846 *
1847 * Return: 0 on success, -errno otherwise.
1848 */
1849 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
1850 size_t len, void *buf)
1851 {
1852 u8 addr_width, read_opcode, read_dummy;
1853 int ret;
1854
1855 read_opcode = nor->read_opcode;
1856 addr_width = nor->addr_width;
1857 read_dummy = nor->read_dummy;
1858
1859 nor->read_opcode = SPINOR_OP_RDSFDP;
1860 nor->addr_width = 3;
1861 nor->read_dummy = 8;
1862
1863 while (len) {
1864 ret = nor->read(nor, addr, len, (u8 *)buf);
1865 if (!ret || ret > len) {
1866 ret = -EIO;
1867 goto read_err;
1868 }
1869 if (ret < 0)
1870 goto read_err;
1871
1872 buf += ret;
1873 addr += ret;
1874 len -= ret;
1875 }
1876 ret = 0;
1877
1878 read_err:
1879 nor->read_opcode = read_opcode;
1880 nor->addr_width = addr_width;
1881 nor->read_dummy = read_dummy;
1882
1883 return ret;
1884 }
1885
1886 /**
1887 * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters.
1888 * @nor: pointer to a 'struct spi_nor'
1889 * @addr: offset in the SFDP area to start reading data from
1890 * @len: number of bytes to read
1891 * @buf: buffer where the SFDP data are copied into
1892 *
1893 * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not
1894 * guaranteed to be dma-safe.
1895 *
1896 * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp()
1897 * otherwise.
1898 */
1899 static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr,
1900 size_t len, void *buf)
1901 {
1902 void *dma_safe_buf;
1903 int ret;
1904
1905 dma_safe_buf = kmalloc(len, GFP_KERNEL);
1906 if (!dma_safe_buf)
1907 return -ENOMEM;
1908
1909 ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf);
1910 memcpy(buf, dma_safe_buf, len);
1911 kfree(dma_safe_buf);
1912
1913 return ret;
1914 }
1915
1916 struct sfdp_parameter_header {
1917 u8 id_lsb;
1918 u8 minor;
1919 u8 major;
1920 u8 length; /* in double words */
1921 u8 parameter_table_pointer[3]; /* byte address */
1922 u8 id_msb;
1923 };
1924
1925 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
1926 #define SFDP_PARAM_HEADER_PTP(p) \
1927 (((p)->parameter_table_pointer[2] << 16) | \
1928 ((p)->parameter_table_pointer[1] << 8) | \
1929 ((p)->parameter_table_pointer[0] << 0))
1930
1931 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
1932 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
1933
1934 #define SFDP_SIGNATURE 0x50444653U
1935 #define SFDP_JESD216_MAJOR 1
1936 #define SFDP_JESD216_MINOR 0
1937 #define SFDP_JESD216A_MINOR 5
1938 #define SFDP_JESD216B_MINOR 6
1939
1940 struct sfdp_header {
1941 u32 signature; /* Ox50444653U <=> "SFDP" */
1942 u8 minor;
1943 u8 major;
1944 u8 nph; /* 0-base number of parameter headers */
1945 u8 unused;
1946
1947 /* Basic Flash Parameter Table. */
1948 struct sfdp_parameter_header bfpt_header;
1949 };
1950
1951 /* Basic Flash Parameter Table */
1952
1953 /*
1954 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
1955 * They are indexed from 1 but C arrays are indexed from 0.
1956 */
1957 #define BFPT_DWORD(i) ((i) - 1)
1958 #define BFPT_DWORD_MAX 16
1959
1960 /* The first version of JESB216 defined only 9 DWORDs. */
1961 #define BFPT_DWORD_MAX_JESD216 9
1962
1963 /* 1st DWORD. */
1964 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
1965 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
1966 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
1967 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
1968 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
1969 #define BFPT_DWORD1_DTR BIT(19)
1970 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
1971 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
1972 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
1973
1974 /* 5th DWORD. */
1975 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
1976 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
1977
1978 /* 11th DWORD. */
1979 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
1980 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
1981
1982 /* 15th DWORD. */
1983
1984 /*
1985 * (from JESD216 rev B)
1986 * Quad Enable Requirements (QER):
1987 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
1988 * reads based on instruction. DQ3/HOLD# functions are hold during
1989 * instruction phase.
1990 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
1991 * two data bytes where bit 1 of the second byte is one.
1992 * [...]
1993 * Writing only one byte to the status register has the side-effect of
1994 * clearing status register 2, including the QE bit. The 100b code is
1995 * used if writing one byte to the status register does not modify
1996 * status register 2.
1997 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
1998 * one data byte where bit 6 is one.
1999 * [...]
2000 * - 011b: QE is bit 7 of status register 2. It is set via Write status
2001 * register 2 instruction 3Eh with one data byte where bit 7 is one.
2002 * [...]
2003 * The status register 2 is read using instruction 3Fh.
2004 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
2005 * two data bytes where bit 1 of the second byte is one.
2006 * [...]
2007 * In contrast to the 001b code, writing one byte to the status
2008 * register does not modify status register 2.
2009 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
2010 * Read Status instruction 05h. Status register2 is read using
2011 * instruction 35h. QE is set via Writ Status instruction 01h with
2012 * two data bytes where bit 1 of the second byte is one.
2013 * [...]
2014 */
2015 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
2016 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
2017 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
2018 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
2019 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
2020 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
2021 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
2022
2023 struct sfdp_bfpt {
2024 u32 dwords[BFPT_DWORD_MAX];
2025 };
2026
2027 /* Fast Read settings. */
2028
2029 static inline void
2030 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
2031 u16 half,
2032 enum spi_nor_protocol proto)
2033 {
2034 read->num_mode_clocks = (half >> 5) & 0x07;
2035 read->num_wait_states = (half >> 0) & 0x1f;
2036 read->opcode = (half >> 8) & 0xff;
2037 read->proto = proto;
2038 }
2039
2040 struct sfdp_bfpt_read {
2041 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
2042 u32 hwcaps;
2043
2044 /*
2045 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
2046 * whether the Fast Read x-y-z command is supported.
2047 */
2048 u32 supported_dword;
2049 u32 supported_bit;
2050
2051 /*
2052 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
2053 * encodes the op code, the number of mode clocks and the number of wait
2054 * states to be used by Fast Read x-y-z command.
2055 */
2056 u32 settings_dword;
2057 u32 settings_shift;
2058
2059 /* The SPI protocol for this Fast Read x-y-z command. */
2060 enum spi_nor_protocol proto;
2061 };
2062
2063 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
2064 /* Fast Read 1-1-2 */
2065 {
2066 SNOR_HWCAPS_READ_1_1_2,
2067 BFPT_DWORD(1), BIT(16), /* Supported bit */
2068 BFPT_DWORD(4), 0, /* Settings */
2069 SNOR_PROTO_1_1_2,
2070 },
2071
2072 /* Fast Read 1-2-2 */
2073 {
2074 SNOR_HWCAPS_READ_1_2_2,
2075 BFPT_DWORD(1), BIT(20), /* Supported bit */
2076 BFPT_DWORD(4), 16, /* Settings */
2077 SNOR_PROTO_1_2_2,
2078 },
2079
2080 /* Fast Read 2-2-2 */
2081 {
2082 SNOR_HWCAPS_READ_2_2_2,
2083 BFPT_DWORD(5), BIT(0), /* Supported bit */
2084 BFPT_DWORD(6), 16, /* Settings */
2085 SNOR_PROTO_2_2_2,
2086 },
2087
2088 /* Fast Read 1-1-4 */
2089 {
2090 SNOR_HWCAPS_READ_1_1_4,
2091 BFPT_DWORD(1), BIT(22), /* Supported bit */
2092 BFPT_DWORD(3), 16, /* Settings */
2093 SNOR_PROTO_1_1_4,
2094 },
2095
2096 /* Fast Read 1-4-4 */
2097 {
2098 SNOR_HWCAPS_READ_1_4_4,
2099 BFPT_DWORD(1), BIT(21), /* Supported bit */
2100 BFPT_DWORD(3), 0, /* Settings */
2101 SNOR_PROTO_1_4_4,
2102 },
2103
2104 /* Fast Read 4-4-4 */
2105 {
2106 SNOR_HWCAPS_READ_4_4_4,
2107 BFPT_DWORD(5), BIT(4), /* Supported bit */
2108 BFPT_DWORD(7), 16, /* Settings */
2109 SNOR_PROTO_4_4_4,
2110 },
2111 };
2112
2113 struct sfdp_bfpt_erase {
2114 /*
2115 * The half-word at offset <shift> in DWORD <dwoard> encodes the
2116 * op code and erase sector size to be used by Sector Erase commands.
2117 */
2118 u32 dword;
2119 u32 shift;
2120 };
2121
2122 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
2123 /* Erase Type 1 in DWORD8 bits[15:0] */
2124 {BFPT_DWORD(8), 0},
2125
2126 /* Erase Type 2 in DWORD8 bits[31:16] */
2127 {BFPT_DWORD(8), 16},
2128
2129 /* Erase Type 3 in DWORD9 bits[15:0] */
2130 {BFPT_DWORD(9), 0},
2131
2132 /* Erase Type 4 in DWORD9 bits[31:16] */
2133 {BFPT_DWORD(9), 16},
2134 };
2135
2136 static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
2137
2138 /**
2139 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
2140 * @nor: pointer to a 'struct spi_nor'
2141 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
2142 * the Basic Flash Parameter Table length and version
2143 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2144 * filled
2145 *
2146 * The Basic Flash Parameter Table is the main and only mandatory table as
2147 * defined by the SFDP (JESD216) specification.
2148 * It provides us with the total size (memory density) of the data array and
2149 * the number of address bytes for Fast Read, Page Program and Sector Erase
2150 * commands.
2151 * For Fast READ commands, it also gives the number of mode clock cycles and
2152 * wait states (regrouped in the number of dummy clock cycles) for each
2153 * supported instruction op code.
2154 * For Page Program, the page size is now available since JESD216 rev A, however
2155 * the supported instruction op codes are still not provided.
2156 * For Sector Erase commands, this table stores the supported instruction op
2157 * codes and the associated sector sizes.
2158 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
2159 * rev A. The QER bits encode the manufacturer dependent procedure to be
2160 * executed to set the Quad Enable (QE) bit in some internal register of the
2161 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
2162 * sending any Quad SPI command to the memory. Actually, setting the QE bit
2163 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
2164 * and IO3 hence enabling 4 (Quad) I/O lines.
2165 *
2166 * Return: 0 on success, -errno otherwise.
2167 */
2168 static int spi_nor_parse_bfpt(struct spi_nor *nor,
2169 const struct sfdp_parameter_header *bfpt_header,
2170 struct spi_nor_flash_parameter *params)
2171 {
2172 struct mtd_info *mtd = &nor->mtd;
2173 struct sfdp_bfpt bfpt;
2174 size_t len;
2175 int i, cmd, err;
2176 u32 addr;
2177 u16 half;
2178
2179 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
2180 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
2181 return -EINVAL;
2182
2183 /* Read the Basic Flash Parameter Table. */
2184 len = min_t(size_t, sizeof(bfpt),
2185 bfpt_header->length * sizeof(u32));
2186 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
2187 memset(&bfpt, 0, sizeof(bfpt));
2188 err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt);
2189 if (err < 0)
2190 return err;
2191
2192 /* Fix endianness of the BFPT DWORDs. */
2193 for (i = 0; i < BFPT_DWORD_MAX; i++)
2194 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
2195
2196 /* Number of address bytes. */
2197 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
2198 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
2199 nor->addr_width = 3;
2200 break;
2201
2202 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
2203 nor->addr_width = 4;
2204 break;
2205
2206 default:
2207 break;
2208 }
2209
2210 /* Flash Memory Density (in bits). */
2211 params->size = bfpt.dwords[BFPT_DWORD(2)];
2212 if (params->size & BIT(31)) {
2213 params->size &= ~BIT(31);
2214
2215 /*
2216 * Prevent overflows on params->size. Anyway, a NOR of 2^64
2217 * bits is unlikely to exist so this error probably means
2218 * the BFPT we are reading is corrupted/wrong.
2219 */
2220 if (params->size > 63)
2221 return -EINVAL;
2222
2223 params->size = 1ULL << params->size;
2224 } else {
2225 params->size++;
2226 }
2227 params->size >>= 3; /* Convert to bytes. */
2228
2229 /* Fast Read settings. */
2230 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
2231 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
2232 struct spi_nor_read_command *read;
2233
2234 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
2235 params->hwcaps.mask &= ~rd->hwcaps;
2236 continue;
2237 }
2238
2239 params->hwcaps.mask |= rd->hwcaps;
2240 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
2241 read = &params->reads[cmd];
2242 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
2243 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
2244 }
2245
2246 /* Sector Erase settings. */
2247 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
2248 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
2249 u32 erasesize;
2250 u8 opcode;
2251
2252 half = bfpt.dwords[er->dword] >> er->shift;
2253 erasesize = half & 0xff;
2254
2255 /* erasesize == 0 means this Erase Type is not supported. */
2256 if (!erasesize)
2257 continue;
2258
2259 erasesize = 1U << erasesize;
2260 opcode = (half >> 8) & 0xff;
2261 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
2262 if (erasesize == SZ_4K) {
2263 nor->erase_opcode = opcode;
2264 mtd->erasesize = erasesize;
2265 break;
2266 }
2267 #endif
2268 if (!mtd->erasesize || mtd->erasesize < erasesize) {
2269 nor->erase_opcode = opcode;
2270 mtd->erasesize = erasesize;
2271 }
2272 }
2273
2274 /* Stop here if not JESD216 rev A or later. */
2275 if (bfpt_header->length < BFPT_DWORD_MAX)
2276 return 0;
2277
2278 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
2279 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
2280 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
2281 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
2282 params->page_size = 1U << params->page_size;
2283
2284 /* Quad Enable Requirements. */
2285 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
2286 case BFPT_DWORD15_QER_NONE:
2287 params->quad_enable = NULL;
2288 break;
2289
2290 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
2291 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
2292 params->quad_enable = spansion_no_read_cr_quad_enable;
2293 break;
2294
2295 case BFPT_DWORD15_QER_SR1_BIT6:
2296 params->quad_enable = macronix_quad_enable;
2297 break;
2298
2299 case BFPT_DWORD15_QER_SR2_BIT7:
2300 params->quad_enable = sr2_bit7_quad_enable;
2301 break;
2302
2303 case BFPT_DWORD15_QER_SR2_BIT1:
2304 params->quad_enable = spansion_read_cr_quad_enable;
2305 break;
2306
2307 default:
2308 return -EINVAL;
2309 }
2310
2311 return 0;
2312 }
2313
2314 /**
2315 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
2316 * @nor: pointer to a 'struct spi_nor'
2317 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2318 * filled
2319 *
2320 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
2321 * specification. This is a standard which tends to supported by almost all
2322 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
2323 * runtime the main parameters needed to perform basic SPI flash operations such
2324 * as Fast Read, Page Program or Sector Erase commands.
2325 *
2326 * Return: 0 on success, -errno otherwise.
2327 */
2328 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2329 struct spi_nor_flash_parameter *params)
2330 {
2331 const struct sfdp_parameter_header *param_header, *bfpt_header;
2332 struct sfdp_parameter_header *param_headers = NULL;
2333 struct sfdp_header header;
2334 struct device *dev = nor->dev;
2335 size_t psize;
2336 int i, err;
2337
2338 /* Get the SFDP header. */
2339 err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header);
2340 if (err < 0)
2341 return err;
2342
2343 /* Check the SFDP header version. */
2344 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
2345 header.major != SFDP_JESD216_MAJOR)
2346 return -EINVAL;
2347
2348 /*
2349 * Verify that the first and only mandatory parameter header is a
2350 * Basic Flash Parameter Table header as specified in JESD216.
2351 */
2352 bfpt_header = &header.bfpt_header;
2353 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
2354 bfpt_header->major != SFDP_JESD216_MAJOR)
2355 return -EINVAL;
2356
2357 /*
2358 * Allocate memory then read all parameter headers with a single
2359 * Read SFDP command. These parameter headers will actually be parsed
2360 * twice: a first time to get the latest revision of the basic flash
2361 * parameter table, then a second time to handle the supported optional
2362 * tables.
2363 * Hence we read the parameter headers once for all to reduce the
2364 * processing time. Also we use kmalloc() instead of devm_kmalloc()
2365 * because we don't need to keep these parameter headers: the allocated
2366 * memory is always released with kfree() before exiting this function.
2367 */
2368 if (header.nph) {
2369 psize = header.nph * sizeof(*param_headers);
2370
2371 param_headers = kmalloc(psize, GFP_KERNEL);
2372 if (!param_headers)
2373 return -ENOMEM;
2374
2375 err = spi_nor_read_sfdp(nor, sizeof(header),
2376 psize, param_headers);
2377 if (err < 0) {
2378 dev_err(dev, "failed to read SFDP parameter headers\n");
2379 goto exit;
2380 }
2381 }
2382
2383 /*
2384 * Check other parameter headers to get the latest revision of
2385 * the basic flash parameter table.
2386 */
2387 for (i = 0; i < header.nph; i++) {
2388 param_header = &param_headers[i];
2389
2390 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
2391 param_header->major == SFDP_JESD216_MAJOR &&
2392 (param_header->minor > bfpt_header->minor ||
2393 (param_header->minor == bfpt_header->minor &&
2394 param_header->length > bfpt_header->length)))
2395 bfpt_header = param_header;
2396 }
2397
2398 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
2399 if (err)
2400 goto exit;
2401
2402 /* Parse other parameter headers. */
2403 for (i = 0; i < header.nph; i++) {
2404 param_header = &param_headers[i];
2405
2406 switch (SFDP_PARAM_HEADER_ID(param_header)) {
2407 case SFDP_SECTOR_MAP_ID:
2408 dev_info(dev, "non-uniform erase sector maps are not supported yet.\n");
2409 break;
2410
2411 default:
2412 break;
2413 }
2414
2415 if (err)
2416 goto exit;
2417 }
2418
2419 exit:
2420 kfree(param_headers);
2421 return err;
2422 }
2423
2424 static int spi_nor_init_params(struct spi_nor *nor,
2425 const struct flash_info *info,
2426 struct spi_nor_flash_parameter *params)
2427 {
2428 /* Set legacy flash parameters as default. */
2429 memset(params, 0, sizeof(*params));
2430
2431 /* Set SPI NOR sizes. */
2432 params->size = info->sector_size * info->n_sectors;
2433 params->page_size = info->page_size;
2434
2435 /* (Fast) Read settings. */
2436 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2437 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
2438 0, 0, SPINOR_OP_READ,
2439 SNOR_PROTO_1_1_1);
2440
2441 if (!(info->flags & SPI_NOR_NO_FR)) {
2442 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2443 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
2444 0, 8, SPINOR_OP_READ_FAST,
2445 SNOR_PROTO_1_1_1);
2446 }
2447
2448 if (info->flags & SPI_NOR_DUAL_READ) {
2449 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2450 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
2451 0, 8, SPINOR_OP_READ_1_1_2,
2452 SNOR_PROTO_1_1_2);
2453 }
2454
2455 if (info->flags & SPI_NOR_QUAD_READ) {
2456 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2457 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
2458 0, 8, SPINOR_OP_READ_1_1_4,
2459 SNOR_PROTO_1_1_4);
2460 }
2461
2462 /* Page Program settings. */
2463 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2464 spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
2465 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2466
2467 /* Select the procedure to set the Quad Enable bit. */
2468 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
2469 SNOR_HWCAPS_PP_QUAD)) {
2470 switch (JEDEC_MFR(info)) {
2471 case SNOR_MFR_MACRONIX:
2472 params->quad_enable = macronix_quad_enable;
2473 break;
2474
2475 case SNOR_MFR_MICRON:
2476 break;
2477
2478 default:
2479 /* Kept only for backward compatibility purpose. */
2480 params->quad_enable = spansion_quad_enable;
2481 break;
2482 }
2483
2484 /*
2485 * Some manufacturer like GigaDevice may use different
2486 * bit to set QE on different memories, so the MFR can't
2487 * indicate the quad_enable method for this case, we need
2488 * set it in flash info list.
2489 */
2490 if (info->quad_enable)
2491 params->quad_enable = info->quad_enable;
2492 }
2493
2494 /* Override the parameters with data read from SFDP tables. */
2495 nor->addr_width = 0;
2496 nor->mtd.erasesize = 0;
2497 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
2498 !(info->flags & SPI_NOR_SKIP_SFDP)) {
2499 struct spi_nor_flash_parameter sfdp_params;
2500
2501 memcpy(&sfdp_params, params, sizeof(sfdp_params));
2502 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
2503 nor->addr_width = 0;
2504 nor->mtd.erasesize = 0;
2505 } else {
2506 memcpy(params, &sfdp_params, sizeof(*params));
2507 }
2508 }
2509
2510 return 0;
2511 }
2512
2513 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2514 {
2515 size_t i;
2516
2517 for (i = 0; i < size; i++)
2518 if (table[i][0] == (int)hwcaps)
2519 return table[i][1];
2520
2521 return -EINVAL;
2522 }
2523
2524 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2525 {
2526 static const int hwcaps_read2cmd[][2] = {
2527 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2528 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2529 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2530 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2531 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2532 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2533 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2534 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2535 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2536 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2537 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2538 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2539 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2540 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2541 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2542 };
2543
2544 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2545 ARRAY_SIZE(hwcaps_read2cmd));
2546 }
2547
2548 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2549 {
2550 static const int hwcaps_pp2cmd[][2] = {
2551 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2552 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2553 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2554 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2555 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2556 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2557 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2558 };
2559
2560 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2561 ARRAY_SIZE(hwcaps_pp2cmd));
2562 }
2563
2564 static int spi_nor_select_read(struct spi_nor *nor,
2565 const struct spi_nor_flash_parameter *params,
2566 u32 shared_hwcaps)
2567 {
2568 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2569 const struct spi_nor_read_command *read;
2570
2571 if (best_match < 0)
2572 return -EINVAL;
2573
2574 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2575 if (cmd < 0)
2576 return -EINVAL;
2577
2578 read = &params->reads[cmd];
2579 nor->read_opcode = read->opcode;
2580 nor->read_proto = read->proto;
2581
2582 /*
2583 * In the spi-nor framework, we don't need to make the difference
2584 * between mode clock cycles and wait state clock cycles.
2585 * Indeed, the value of the mode clock cycles is used by a QSPI
2586 * flash memory to know whether it should enter or leave its 0-4-4
2587 * (Continuous Read / XIP) mode.
2588 * eXecution In Place is out of the scope of the mtd sub-system.
2589 * Hence we choose to merge both mode and wait state clock cycles
2590 * into the so called dummy clock cycles.
2591 */
2592 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2593 return 0;
2594 }
2595
2596 static int spi_nor_select_pp(struct spi_nor *nor,
2597 const struct spi_nor_flash_parameter *params,
2598 u32 shared_hwcaps)
2599 {
2600 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2601 const struct spi_nor_pp_command *pp;
2602
2603 if (best_match < 0)
2604 return -EINVAL;
2605
2606 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2607 if (cmd < 0)
2608 return -EINVAL;
2609
2610 pp = &params->page_programs[cmd];
2611 nor->program_opcode = pp->opcode;
2612 nor->write_proto = pp->proto;
2613 return 0;
2614 }
2615
2616 static int spi_nor_select_erase(struct spi_nor *nor,
2617 const struct flash_info *info)
2618 {
2619 struct mtd_info *mtd = &nor->mtd;
2620
2621 /* Do nothing if already configured from SFDP. */
2622 if (mtd->erasesize)
2623 return 0;
2624
2625 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
2626 /* prefer "small sector" erase if possible */
2627 if (info->flags & SECT_4K) {
2628 nor->erase_opcode = SPINOR_OP_BE_4K;
2629 mtd->erasesize = 4096;
2630 } else if (info->flags & SECT_4K_PMC) {
2631 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
2632 mtd->erasesize = 4096;
2633 } else
2634 #endif
2635 {
2636 nor->erase_opcode = SPINOR_OP_SE;
2637 mtd->erasesize = info->sector_size;
2638 }
2639 return 0;
2640 }
2641
2642 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
2643 const struct spi_nor_flash_parameter *params,
2644 const struct spi_nor_hwcaps *hwcaps)
2645 {
2646 u32 ignored_mask, shared_mask;
2647 bool enable_quad_io;
2648 int err;
2649
2650 /*
2651 * Keep only the hardware capabilities supported by both the SPI
2652 * controller and the SPI flash memory.
2653 */
2654 shared_mask = hwcaps->mask & params->hwcaps.mask;
2655
2656 /* SPI n-n-n protocols are not supported yet. */
2657 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
2658 SNOR_HWCAPS_READ_4_4_4 |
2659 SNOR_HWCAPS_READ_8_8_8 |
2660 SNOR_HWCAPS_PP_4_4_4 |
2661 SNOR_HWCAPS_PP_8_8_8);
2662 if (shared_mask & ignored_mask) {
2663 dev_dbg(nor->dev,
2664 "SPI n-n-n protocols are not supported yet.\n");
2665 shared_mask &= ~ignored_mask;
2666 }
2667
2668 /* Select the (Fast) Read command. */
2669 err = spi_nor_select_read(nor, params, shared_mask);
2670 if (err) {
2671 dev_err(nor->dev,
2672 "can't select read settings supported by both the SPI controller and memory.\n");
2673 return err;
2674 }
2675
2676 /* Select the Page Program command. */
2677 err = spi_nor_select_pp(nor, params, shared_mask);
2678 if (err) {
2679 dev_err(nor->dev,
2680 "can't select write settings supported by both the SPI controller and memory.\n");
2681 return err;
2682 }
2683
2684 /* Select the Sector Erase command. */
2685 err = spi_nor_select_erase(nor, info);
2686 if (err) {
2687 dev_err(nor->dev,
2688 "can't select erase settings supported by both the SPI controller and memory.\n");
2689 return err;
2690 }
2691
2692 /* Enable Quad I/O if needed. */
2693 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2694 spi_nor_get_protocol_width(nor->write_proto) == 4);
2695 if (enable_quad_io && params->quad_enable)
2696 nor->quad_enable = params->quad_enable;
2697 else
2698 nor->quad_enable = NULL;
2699
2700 return 0;
2701 }
2702
2703 static int spi_nor_init(struct spi_nor *nor)
2704 {
2705 int err;
2706
2707 /*
2708 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
2709 * with the software protection bits set
2710 */
2711 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
2712 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
2713 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
2714 nor->info->flags & SPI_NOR_HAS_LOCK) {
2715 write_enable(nor);
2716 write_sr(nor, 0);
2717 spi_nor_wait_till_ready(nor);
2718 }
2719
2720 if (nor->quad_enable) {
2721 err = nor->quad_enable(nor);
2722 if (err) {
2723 dev_err(nor->dev, "quad mode not supported\n");
2724 return err;
2725 }
2726 }
2727
2728 if ((nor->addr_width == 4) &&
2729 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
2730 !(nor->info->flags & SPI_NOR_4B_OPCODES))
2731 set_4byte(nor, nor->info, 1);
2732
2733 return 0;
2734 }
2735
2736 /* mtd resume handler */
2737 static void spi_nor_resume(struct mtd_info *mtd)
2738 {
2739 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2740 struct device *dev = nor->dev;
2741 int ret;
2742
2743 /* re-initialize the nor chip */
2744 ret = spi_nor_init(nor);
2745 if (ret)
2746 dev_err(dev, "resume() failed\n");
2747 }
2748
2749 void spi_nor_restore(struct spi_nor *nor)
2750 {
2751 /* restore the addressing mode */
2752 if ((nor->addr_width == 4) &&
2753 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
2754 !(nor->info->flags & SPI_NOR_4B_OPCODES))
2755 set_4byte(nor, nor->info, 0);
2756 }
2757 EXPORT_SYMBOL_GPL(spi_nor_restore);
2758
2759 int spi_nor_scan(struct spi_nor *nor, const char *name,
2760 const struct spi_nor_hwcaps *hwcaps)
2761 {
2762 struct spi_nor_flash_parameter params;
2763 const struct flash_info *info = NULL;
2764 struct device *dev = nor->dev;
2765 struct mtd_info *mtd = &nor->mtd;
2766 struct device_node *np = spi_nor_get_flash_node(nor);
2767 int ret;
2768 int i;
2769
2770 ret = spi_nor_check(nor);
2771 if (ret)
2772 return ret;
2773
2774 /* Reset SPI protocol for all commands. */
2775 nor->reg_proto = SNOR_PROTO_1_1_1;
2776 nor->read_proto = SNOR_PROTO_1_1_1;
2777 nor->write_proto = SNOR_PROTO_1_1_1;
2778
2779 if (name)
2780 info = spi_nor_match_id(name);
2781 /* Try to auto-detect if chip name wasn't specified or not found */
2782 if (!info)
2783 info = spi_nor_read_id(nor);
2784 if (IS_ERR_OR_NULL(info))
2785 return -ENOENT;
2786
2787 /*
2788 * If caller has specified name of flash model that can normally be
2789 * detected using JEDEC, let's verify it.
2790 */
2791 if (name && info->id_len) {
2792 const struct flash_info *jinfo;
2793
2794 jinfo = spi_nor_read_id(nor);
2795 if (IS_ERR(jinfo)) {
2796 return PTR_ERR(jinfo);
2797 } else if (jinfo != info) {
2798 /*
2799 * JEDEC knows better, so overwrite platform ID. We
2800 * can't trust partitions any longer, but we'll let
2801 * mtd apply them anyway, since some partitions may be
2802 * marked read-only, and we don't want to lose that
2803 * information, even if it's not 100% accurate.
2804 */
2805 dev_warn(dev, "found %s, expected %s\n",
2806 jinfo->name, info->name);
2807 info = jinfo;
2808 }
2809 }
2810
2811 mutex_init(&nor->lock);
2812
2813 /*
2814 * Make sure the XSR_RDY flag is set before calling
2815 * spi_nor_wait_till_ready(). Xilinx S3AN share MFR
2816 * with Atmel spi-nor
2817 */
2818 if (info->flags & SPI_S3AN)
2819 nor->flags |= SNOR_F_READY_XSR_RDY;
2820
2821 /* Parse the Serial Flash Discoverable Parameters table. */
2822 ret = spi_nor_init_params(nor, info, &params);
2823 if (ret)
2824 return ret;
2825
2826 if (!mtd->name)
2827 mtd->name = dev_name(dev);
2828 mtd->priv = nor;
2829 mtd->type = MTD_NORFLASH;
2830 mtd->writesize = 1;
2831 mtd->flags = MTD_CAP_NORFLASH;
2832 mtd->size = params.size;
2833 mtd->_erase = spi_nor_erase;
2834 mtd->_read = spi_nor_read;
2835 mtd->_resume = spi_nor_resume;
2836
2837 /* NOR protection support for STmicro/Micron chips and similar */
2838 if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
2839 info->flags & SPI_NOR_HAS_LOCK) {
2840 nor->flash_lock = stm_lock;
2841 nor->flash_unlock = stm_unlock;
2842 nor->flash_is_locked = stm_is_locked;
2843 }
2844
2845 if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
2846 mtd->_lock = spi_nor_lock;
2847 mtd->_unlock = spi_nor_unlock;
2848 mtd->_is_locked = spi_nor_is_locked;
2849 }
2850
2851 /* sst nor chips use AAI word program */
2852 if (info->flags & SST_WRITE)
2853 mtd->_write = sst_write;
2854 else
2855 mtd->_write = spi_nor_write;
2856
2857 if (info->flags & USE_FSR)
2858 nor->flags |= SNOR_F_USE_FSR;
2859 if (info->flags & SPI_NOR_HAS_TB)
2860 nor->flags |= SNOR_F_HAS_SR_TB;
2861 if (info->flags & NO_CHIP_ERASE)
2862 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2863 if (info->flags & USE_CLSR)
2864 nor->flags |= SNOR_F_USE_CLSR;
2865
2866 if (info->flags & SPI_NOR_NO_ERASE)
2867 mtd->flags |= MTD_NO_ERASE;
2868
2869 mtd->dev.parent = dev;
2870 nor->page_size = params.page_size;
2871 mtd->writebufsize = nor->page_size;
2872
2873 if (np) {
2874 /* If we were instantiated by DT, use it */
2875 if (of_property_read_bool(np, "m25p,fast-read"))
2876 params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2877 else
2878 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2879 } else {
2880 /* If we weren't instantiated by DT, default to fast-read */
2881 params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2882 }
2883
2884 /* Some devices cannot do fast-read, no matter what DT tells us */
2885 if (info->flags & SPI_NOR_NO_FR)
2886 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2887
2888 /*
2889 * Configure the SPI memory:
2890 * - select op codes for (Fast) Read, Page Program and Sector Erase.
2891 * - set the number of dummy cycles (mode cycles + wait states).
2892 * - set the SPI protocols for register and memory accesses.
2893 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
2894 */
2895 ret = spi_nor_setup(nor, info, &params, hwcaps);
2896 if (ret)
2897 return ret;
2898
2899 if (nor->addr_width) {
2900 /* already configured from SFDP */
2901 } else if (info->addr_width) {
2902 nor->addr_width = info->addr_width;
2903 } else if (mtd->size > 0x1000000) {
2904 /* enable 4-byte addressing if the device exceeds 16MiB */
2905 nor->addr_width = 4;
2906 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
2907 info->flags & SPI_NOR_4B_OPCODES)
2908 spi_nor_set_4byte_opcodes(nor, info);
2909 } else {
2910 nor->addr_width = 3;
2911 }
2912
2913 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
2914 dev_err(dev, "address width is too large: %u\n",
2915 nor->addr_width);
2916 return -EINVAL;
2917 }
2918
2919 if (info->flags & SPI_S3AN) {
2920 ret = s3an_nor_scan(info, nor);
2921 if (ret)
2922 return ret;
2923 }
2924
2925 /* Send all the required SPI flash commands to initialize device */
2926 nor->info = info;
2927 ret = spi_nor_init(nor);
2928 if (ret)
2929 return ret;
2930
2931 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
2932 (long long)mtd->size >> 10);
2933
2934 dev_dbg(dev,
2935 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
2936 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
2937 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
2938 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
2939
2940 if (mtd->numeraseregions)
2941 for (i = 0; i < mtd->numeraseregions; i++)
2942 dev_dbg(dev,
2943 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
2944 ".erasesize = 0x%.8x (%uKiB), "
2945 ".numblocks = %d }\n",
2946 i, (long long)mtd->eraseregions[i].offset,
2947 mtd->eraseregions[i].erasesize,
2948 mtd->eraseregions[i].erasesize / 1024,
2949 mtd->eraseregions[i].numblocks);
2950 return 0;
2951 }
2952 EXPORT_SYMBOL_GPL(spi_nor_scan);
2953
2954 static const struct flash_info *spi_nor_match_id(const char *name)
2955 {
2956 const struct flash_info *id = spi_nor_ids;
2957
2958 while (id->name) {
2959 if (!strcmp(name, id->name))
2960 return id;
2961 id++;
2962 }
2963 return NULL;
2964 }
2965
2966 MODULE_LICENSE("GPL");
2967 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
2968 MODULE_AUTHOR("Mike Lavender");
2969 MODULE_DESCRIPTION("framework for SPI NOR");
Linux with added FPC-III support