drivers/mtd/spi-nor/stm32-quadspi.c

   1 /*
   2  * Driver for stm32 quadspi controller
   3  *
   4  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   5  * Author(s): Ludovic Barre author <ludovic.barre@st.com>.
   6  *
   7  * License terms: GPL V2.0.
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
  16  * details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * This program. If not, see <http://www.gnu.org/licenses/>.
  20  */
  21 #include <linux/clk.h>
  22 #include <linux/errno.h>
  23 #include <linux/io.h>
  24 #include <linux/iopoll.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/module.h>
  27 #include <linux/mtd/mtd.h>
  28 #include <linux/mtd/partitions.h>
  29 #include <linux/mtd/spi-nor.h>
  30 #include <linux/mutex.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/reset.h>
  35 #include <linux/sizes.h>
  36
  37 #define QUADSPI_CR              0x00
  38 #define CR_EN                   BIT(0)
  39 #define CR_ABORT                BIT(1)
  40 #define CR_DMAEN                BIT(2)
  41 #define CR_TCEN                 BIT(3)
  42 #define CR_SSHIFT               BIT(4)
  43 #define CR_DFM                  BIT(6)
  44 #define CR_FSEL                 BIT(7)
  45 #define CR_FTHRES_SHIFT         8
  46 #define CR_FTHRES_MASK          GENMASK(12, 8)
  47 #define CR_FTHRES(n)            (((n) << CR_FTHRES_SHIFT) & CR_FTHRES_MASK)
  48 #define CR_TEIE                 BIT(16)
  49 #define CR_TCIE                 BIT(17)
  50 #define CR_FTIE                 BIT(18)
  51 #define CR_SMIE                 BIT(19)
  52 #define CR_TOIE                 BIT(20)
  53 #define CR_PRESC_SHIFT          24
  54 #define CR_PRESC_MASK           GENMASK(31, 24)
  55 #define CR_PRESC(n)             (((n) << CR_PRESC_SHIFT) & CR_PRESC_MASK)
  56
  57 #define QUADSPI_DCR             0x04
  58 #define DCR_CSHT_SHIFT          8
  59 #define DCR_CSHT_MASK           GENMASK(10, 8)
  60 #define DCR_CSHT(n)             (((n) << DCR_CSHT_SHIFT) & DCR_CSHT_MASK)
  61 #define DCR_FSIZE_SHIFT         16
  62 #define DCR_FSIZE_MASK          GENMASK(20, 16)
  63 #define DCR_FSIZE(n)            (((n) << DCR_FSIZE_SHIFT) & DCR_FSIZE_MASK)
  64
  65 #define QUADSPI_SR              0x08
  66 #define SR_TEF                  BIT(0)
  67 #define SR_TCF                  BIT(1)
  68 #define SR_FTF                  BIT(2)
  69 #define SR_SMF                  BIT(3)
  70 #define SR_TOF                  BIT(4)
  71 #define SR_BUSY                 BIT(5)
  72 #define SR_FLEVEL_SHIFT         8
  73 #define SR_FLEVEL_MASK          GENMASK(13, 8)
  74
  75 #define QUADSPI_FCR             0x0c
  76 #define FCR_CTCF                BIT(1)
  77
  78 #define QUADSPI_DLR             0x10
  79
  80 #define QUADSPI_CCR             0x14
  81 #define CCR_INST_SHIFT          0
  82 #define CCR_INST_MASK           GENMASK(7, 0)
  83 #define CCR_INST(n)             (((n) << CCR_INST_SHIFT) & CCR_INST_MASK)
  84 #define CCR_IMODE_NONE          (0U << 8)
  85 #define CCR_IMODE_1             (1U << 8)
  86 #define CCR_IMODE_2             (2U << 8)
  87 #define CCR_IMODE_4             (3U << 8)
  88 #define CCR_ADMODE_NONE         (0U << 10)
  89 #define CCR_ADMODE_1            (1U << 10)
  90 #define CCR_ADMODE_2            (2U << 10)
  91 #define CCR_ADMODE_4            (3U << 10)
  92 #define CCR_ADSIZE_SHIFT        12
  93 #define CCR_ADSIZE_MASK         GENMASK(13, 12)
  94 #define CCR_ADSIZE(n)           (((n) << CCR_ADSIZE_SHIFT) & CCR_ADSIZE_MASK)
  95 #define CCR_ABMODE_NONE         (0U << 14)
  96 #define CCR_ABMODE_1            (1U << 14)
  97 #define CCR_ABMODE_2            (2U << 14)
  98 #define CCR_ABMODE_4            (3U << 14)
  99 #define CCR_ABSIZE_8            (0U << 16)
 100 #define CCR_ABSIZE_16           (1U << 16)
 101 #define CCR_ABSIZE_24           (2U << 16)
 102 #define CCR_ABSIZE_32           (3U << 16)
 103 #define CCR_DCYC_SHIFT          18
 104 #define CCR_DCYC_MASK           GENMASK(22, 18)
 105 #define CCR_DCYC(n)             (((n) << CCR_DCYC_SHIFT) & CCR_DCYC_MASK)
 106 #define CCR_DMODE_NONE          (0U << 24)
 107 #define CCR_DMODE_1             (1U << 24)
 108 #define CCR_DMODE_2             (2U << 24)
 109 #define CCR_DMODE_4             (3U << 24)
 110 #define CCR_FMODE_INDW          (0U << 26)
 111 #define CCR_FMODE_INDR          (1U << 26)
 112 #define CCR_FMODE_APM           (2U << 26)
 113 #define CCR_FMODE_MM            (3U << 26)
 114
 115 #define QUADSPI_AR              0x18
 116 #define QUADSPI_ABR             0x1c
 117 #define QUADSPI_DR              0x20
 118 #define QUADSPI_PSMKR           0x24
 119 #define QUADSPI_PSMAR           0x28
 120 #define QUADSPI_PIR             0x2c
 121 #define QUADSPI_LPTR            0x30
 122 #define LPTR_DFT_TIMEOUT        0x10
 123
 124 #define FSIZE_VAL(size)         (__fls(size) - 1)
 125
 126 #define STM32_MAX_MMAP_SZ       SZ_256M
 127 #define STM32_MAX_NORCHIP       2
 128
 129 #define STM32_QSPI_FIFO_SZ      32
 130 #define STM32_QSPI_FIFO_TIMEOUT_US 30000
 131 #define STM32_QSPI_BUSY_TIMEOUT_US 100000
 132
 133 struct stm32_qspi_flash {
 134         struct spi_nor nor;
 135         struct stm32_qspi *qspi;
 136         u32 cs;
 137         u32 fsize;
 138         u32 presc;
 139         u32 read_mode;
 140         bool registered;
 141         u32 prefetch_limit;
 142 };
 143
 144 struct stm32_qspi {
 145         struct device *dev;
 146         void __iomem *io_base;
 147         void __iomem *mm_base;
 148         resource_size_t mm_size;
 149         u32 nor_num;
 150         struct clk *clk;
 151         u32 clk_rate;
 152         struct stm32_qspi_flash flash[STM32_MAX_NORCHIP];
 153         struct completion cmd_completion;
 154
 155         /*
 156          * to protect device configuration, could be different between
 157          * 2 flash access (bk1, bk2)
 158          */
 159         struct mutex lock;
 160 };
 161
 162 struct stm32_qspi_cmd {
 163         u8 addr_width;
 164         u8 dummy;
 165         bool tx_data;
 166         u8 opcode;
 167         u32 framemode;
 168         u32 qspimode;
 169         u32 addr;
 170         size_t len;
 171         void *buf;
 172 };
 173
 174 static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi)
 175 {
 176         u32 cr;
 177         int err = 0;
 178
 179         if (readl_relaxed(qspi->io_base + QUADSPI_SR) & SR_TCF)
 180                 return 0;
 181
 182         reinit_completion(&qspi->cmd_completion);
 183         cr = readl_relaxed(qspi->io_base + QUADSPI_CR);
 184         writel_relaxed(cr | CR_TCIE, qspi->io_base + QUADSPI_CR);
 185
 186         if (!wait_for_completion_interruptible_timeout(&qspi->cmd_completion,
 187                                                        msecs_to_jiffies(1000)))
 188                 err = -ETIMEDOUT;
 189
 190         writel_relaxed(cr, qspi->io_base + QUADSPI_CR);
 191         return err;
 192 }
 193
 194 static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
 195 {
 196         u32 sr;
 197
 198         return readl_relaxed_poll_timeout(qspi->io_base + QUADSPI_SR, sr,
 199                                           !(sr & SR_BUSY), 10,
 200                                           STM32_QSPI_BUSY_TIMEOUT_US);
 201 }
 202
 203 static void stm32_qspi_set_framemode(struct spi_nor *nor,
 204                                      struct stm32_qspi_cmd *cmd, bool read)
 205 {
 206         u32 dmode = CCR_DMODE_1;
 207
 208         cmd->framemode = CCR_IMODE_1;
 209
 210         if (read) {
 211                 switch (nor->read_proto) {
 212                 default:
 213                 case SNOR_PROTO_1_1_1:
 214                         dmode = CCR_DMODE_1;
 215                         break;
 216                 case SNOR_PROTO_1_1_2:
 217                         dmode = CCR_DMODE_2;
 218                         break;
 219                 case SNOR_PROTO_1_1_4:
 220                         dmode = CCR_DMODE_4;
 221                         break;
 222                 }
 223         }
 224
 225         cmd->framemode |= cmd->tx_data ? dmode : 0;
 226         cmd->framemode |= cmd->addr_width ? CCR_ADMODE_1 : 0;
 227 }
 228
 229 static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
 230 {
 231         *val = readb_relaxed(addr);
 232 }
 233
 234 static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
 235 {
 236         writeb_relaxed(*val, addr);
 237 }
 238
 239 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
 240                               const struct stm32_qspi_cmd *cmd)
 241 {
 242         void (*tx_fifo)(u8 *, void __iomem *);
 243         u32 len = cmd->len, sr;
 244         u8 *buf = cmd->buf;
 245         int ret;
 246
 247         if (cmd->qspimode == CCR_FMODE_INDW)
 248                 tx_fifo = stm32_qspi_write_fifo;
 249         else
 250                 tx_fifo = stm32_qspi_read_fifo;
 251
 252         while (len--) {
 253                 ret = readl_relaxed_poll_timeout(qspi->io_base + QUADSPI_SR,
 254                                                  sr, (sr & SR_FTF), 10,
 255                                                  STM32_QSPI_FIFO_TIMEOUT_US);
 256                 if (ret) {
 257                         dev_err(qspi->dev, "fifo timeout (stat:%#x)\n", sr);
 258                         return ret;
 259                 }
 260                 tx_fifo(buf++, qspi->io_base + QUADSPI_DR);
 261         }
 262
 263         return 0;
 264 }
 265
 266 static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
 267                             const struct stm32_qspi_cmd *cmd)
 268 {
 269         memcpy_fromio(cmd->buf, qspi->mm_base + cmd->addr, cmd->len);
 270         return 0;
 271 }
 272
 273 static int stm32_qspi_tx(struct stm32_qspi *qspi,
 274                          const struct stm32_qspi_cmd *cmd)
 275 {
 276         if (!cmd->tx_data)
 277                 return 0;
 278
 279         if (cmd->qspimode == CCR_FMODE_MM)
 280                 return stm32_qspi_tx_mm(qspi, cmd);
 281
 282         return stm32_qspi_tx_poll(qspi, cmd);
 283 }
 284
 285 static int stm32_qspi_send(struct stm32_qspi_flash *flash,
 286                            const struct stm32_qspi_cmd *cmd)
 287 {
 288         struct stm32_qspi *qspi = flash->qspi;
 289         u32 ccr, dcr, cr;
 290         u32 last_byte;
 291         int err;
 292
 293         err = stm32_qspi_wait_nobusy(qspi);
 294         if (err)
 295                 goto abort;
 296
 297         dcr = readl_relaxed(qspi->io_base + QUADSPI_DCR) & ~DCR_FSIZE_MASK;
 298         dcr |= DCR_FSIZE(flash->fsize);
 299         writel_relaxed(dcr, qspi->io_base + QUADSPI_DCR);
 300
 301         cr = readl_relaxed(qspi->io_base + QUADSPI_CR);
 302         cr &= ~CR_PRESC_MASK & ~CR_FSEL;
 303         cr |= CR_PRESC(flash->presc);
 304         cr |= flash->cs ? CR_FSEL : 0;
 305         writel_relaxed(cr, qspi->io_base + QUADSPI_CR);
 306
 307         if (cmd->tx_data)
 308                 writel_relaxed(cmd->len - 1, qspi->io_base + QUADSPI_DLR);
 309
 310         ccr = cmd->framemode | cmd->qspimode;
 311
 312         if (cmd->dummy)
 313                 ccr |= CCR_DCYC(cmd->dummy);
 314
 315         if (cmd->addr_width)
 316                 ccr |= CCR_ADSIZE(cmd->addr_width - 1);
 317
 318         ccr |= CCR_INST(cmd->opcode);
 319         writel_relaxed(ccr, qspi->io_base + QUADSPI_CCR);
 320
 321         if (cmd->addr_width && cmd->qspimode != CCR_FMODE_MM)
 322                 writel_relaxed(cmd->addr, qspi->io_base + QUADSPI_AR);
 323
 324         err = stm32_qspi_tx(qspi, cmd);
 325         if (err)
 326                 goto abort;
 327
 328         if (cmd->qspimode != CCR_FMODE_MM) {
 329                 err = stm32_qspi_wait_cmd(qspi);
 330                 if (err)
 331                         goto abort;
 332                 writel_relaxed(FCR_CTCF, qspi->io_base + QUADSPI_FCR);
 333         } else {
 334                 last_byte = cmd->addr + cmd->len;
 335                 if (last_byte > flash->prefetch_limit)
 336                         goto abort;
 337         }
 338
 339         return err;
 340
 341 abort:
 342         cr = readl_relaxed(qspi->io_base + QUADSPI_CR) | CR_ABORT;
 343         writel_relaxed(cr, qspi->io_base + QUADSPI_CR);
 344
 345         if (err)
 346                 dev_err(qspi->dev, "%s abort err:%d\n", __func__, err);
 347
 348         return err;
 349 }
 350
 351 static int stm32_qspi_read_reg(struct spi_nor *nor,
 352                                u8 opcode, u8 *buf, int len)
 353 {
 354         struct stm32_qspi_flash *flash = nor->priv;
 355         struct device *dev = flash->qspi->dev;
 356         struct stm32_qspi_cmd cmd;
 357
 358         dev_dbg(dev, "read_reg: cmd:%#.2x buf:%p len:%#x\n", opcode, buf, len);
 359
 360         memset(&cmd, 0, sizeof(cmd));
 361         cmd.opcode = opcode;
 362         cmd.tx_data = true;
 363         cmd.len = len;
 364         cmd.buf = buf;
 365         cmd.qspimode = CCR_FMODE_INDR;
 366
 367         stm32_qspi_set_framemode(nor, &cmd, false);
 368
 369         return stm32_qspi_send(flash, &cmd);
 370 }
 371
 372 static int stm32_qspi_write_reg(struct spi_nor *nor, u8 opcode,
 373                                 u8 *buf, int len)
 374 {
 375         struct stm32_qspi_flash *flash = nor->priv;
 376         struct device *dev = flash->qspi->dev;
 377         struct stm32_qspi_cmd cmd;
 378
 379         dev_dbg(dev, "write_reg: cmd:%#.2x buf:%p len:%#x\n", opcode, buf, len);
 380
 381         memset(&cmd, 0, sizeof(cmd));
 382         cmd.opcode = opcode;
 383         cmd.tx_data = !!(buf && len > 0);
 384         cmd.len = len;
 385         cmd.buf = buf;
 386         cmd.qspimode = CCR_FMODE_INDW;
 387
 388         stm32_qspi_set_framemode(nor, &cmd, false);
 389
 390         return stm32_qspi_send(flash, &cmd);
 391 }
 392
 393 static ssize_t stm32_qspi_read(struct spi_nor *nor, loff_t from, size_t len,
 394                                u_char *buf)
 395 {
 396         struct stm32_qspi_flash *flash = nor->priv;
 397         struct stm32_qspi *qspi = flash->qspi;
 398         struct stm32_qspi_cmd cmd;
 399         int err;
 400
 401         dev_dbg(qspi->dev, "read(%#.2x): buf:%p from:%#.8x len:%#zx\n",
 402                 nor->read_opcode, buf, (u32)from, len);
 403
 404         memset(&cmd, 0, sizeof(cmd));
 405         cmd.opcode = nor->read_opcode;
 406         cmd.addr_width = nor->addr_width;
 407         cmd.addr = (u32)from;
 408         cmd.tx_data = true;
 409         cmd.dummy = nor->read_dummy;
 410         cmd.len = len;
 411         cmd.buf = buf;
 412         cmd.qspimode = flash->read_mode;
 413
 414         stm32_qspi_set_framemode(nor, &cmd, true);
 415         err = stm32_qspi_send(flash, &cmd);
 416
 417         return err ? err : len;
 418 }
 419
 420 static ssize_t stm32_qspi_write(struct spi_nor *nor, loff_t to, size_t len,
 421                                 const u_char *buf)
 422 {
 423         struct stm32_qspi_flash *flash = nor->priv;
 424         struct device *dev = flash->qspi->dev;
 425         struct stm32_qspi_cmd cmd;
 426         int err;
 427
 428         dev_dbg(dev, "write(%#.2x): buf:%p to:%#.8x len:%#zx\n",
 429                 nor->program_opcode, buf, (u32)to, len);
 430
 431         memset(&cmd, 0, sizeof(cmd));
 432         cmd.opcode = nor->program_opcode;
 433         cmd.addr_width = nor->addr_width;
 434         cmd.addr = (u32)to;
 435         cmd.tx_data = true;
 436         cmd.len = len;
 437         cmd.buf = (void *)buf;
 438         cmd.qspimode = CCR_FMODE_INDW;
 439
 440         stm32_qspi_set_framemode(nor, &cmd, false);
 441         err = stm32_qspi_send(flash, &cmd);
 442
 443         return err ? err : len;
 444 }
 445
 446 static int stm32_qspi_erase(struct spi_nor *nor, loff_t offs)
 447 {
 448         struct stm32_qspi_flash *flash = nor->priv;
 449         struct device *dev = flash->qspi->dev;
 450         struct stm32_qspi_cmd cmd;
 451
 452         dev_dbg(dev, "erase(%#.2x):offs:%#x\n", nor->erase_opcode, (u32)offs);
 453
 454         memset(&cmd, 0, sizeof(cmd));
 455         cmd.opcode = nor->erase_opcode;
 456         cmd.addr_width = nor->addr_width;
 457         cmd.addr = (u32)offs;
 458         cmd.qspimode = CCR_FMODE_INDW;
 459
 460         stm32_qspi_set_framemode(nor, &cmd, false);
 461
 462         return stm32_qspi_send(flash, &cmd);
 463 }
 464
 465 static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
 466 {
 467         struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
 468         u32 cr, sr, fcr = 0;
 469
 470         cr = readl_relaxed(qspi->io_base + QUADSPI_CR);
 471         sr = readl_relaxed(qspi->io_base + QUADSPI_SR);
 472
 473         if ((cr & CR_TCIE) && (sr & SR_TCF)) {
 474                 /* tx complete */
 475                 fcr |= FCR_CTCF;
 476                 complete(&qspi->cmd_completion);
 477         } else {
 478                 dev_info_ratelimited(qspi->dev, "spurious interrupt\n");
 479         }
 480
 481         writel_relaxed(fcr, qspi->io_base + QUADSPI_FCR);
 482
 483         return IRQ_HANDLED;
 484 }
 485
 486 static int stm32_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
 487 {
 488         struct stm32_qspi_flash *flash = nor->priv;
 489         struct stm32_qspi *qspi = flash->qspi;
 490
 491         mutex_lock(&qspi->lock);
 492         return 0;
 493 }
 494
 495 static void stm32_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
 496 {
 497         struct stm32_qspi_flash *flash = nor->priv;
 498         struct stm32_qspi *qspi = flash->qspi;
 499
 500         mutex_unlock(&qspi->lock);
 501 }
 502
 503 static int stm32_qspi_flash_setup(struct stm32_qspi *qspi,
 504                                   struct device_node *np)
 505 {
 506         struct spi_nor_hwcaps hwcaps = {
 507                 .mask = SNOR_HWCAPS_READ |
 508                         SNOR_HWCAPS_READ_FAST |
 509                         SNOR_HWCAPS_PP,
 510         };
 511         u32 width, presc, cs_num, max_rate = 0;
 512         struct stm32_qspi_flash *flash;
 513         struct mtd_info *mtd;
 514         int ret;
 515
 516         of_property_read_u32(np, "reg", &cs_num);
 517         if (cs_num >= STM32_MAX_NORCHIP)
 518                 return -EINVAL;
 519
 520         of_property_read_u32(np, "spi-max-frequency", &max_rate);
 521         if (!max_rate)
 522                 return -EINVAL;
 523
 524         presc = DIV_ROUND_UP(qspi->clk_rate, max_rate) - 1;
 525
 526         if (of_property_read_u32(np, "spi-rx-bus-width", &width))
 527                 width = 1;
 528
 529         if (width == 4)
 530                 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
 531         else if (width == 2)
 532                 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
 533         else if (width != 1)
 534                 return -EINVAL;
 535
 536         flash = &qspi->flash[cs_num];
 537         flash->qspi = qspi;
 538         flash->cs = cs_num;
 539         flash->presc = presc;
 540
 541         flash->nor.dev = qspi->dev;
 542         spi_nor_set_flash_node(&flash->nor, np);
 543         flash->nor.priv = flash;
 544         mtd = &flash->nor.mtd;
 545
 546         flash->nor.read = stm32_qspi_read;
 547         flash->nor.write = stm32_qspi_write;
 548         flash->nor.erase = stm32_qspi_erase;
 549         flash->nor.read_reg = stm32_qspi_read_reg;
 550         flash->nor.write_reg = stm32_qspi_write_reg;
 551         flash->nor.prepare = stm32_qspi_prep;
 552         flash->nor.unprepare = stm32_qspi_unprep;
 553
 554         writel_relaxed(LPTR_DFT_TIMEOUT, qspi->io_base + QUADSPI_LPTR);
 555
 556         writel_relaxed(CR_PRESC(presc) | CR_FTHRES(3) | CR_TCEN | CR_SSHIFT
 557                        | CR_EN, qspi->io_base + QUADSPI_CR);
 558
 559         /*
 560          * in stm32 qspi controller, QUADSPI_DCR register has a fsize field
 561          * which define the size of nor flash.
 562          * if fsize is NULL, the controller can't sent spi-nor command.
 563          * set a temporary value just to discover the nor flash with
 564          * "spi_nor_scan". After, the right value (mtd->size) can be set.
 565          */
 566         flash->fsize = FSIZE_VAL(SZ_1K);
 567
 568         ret = spi_nor_scan(&flash->nor, NULL, &hwcaps);
 569         if (ret) {
 570                 dev_err(qspi->dev, "device scan failed\n");
 571                 return ret;
 572         }
 573
 574         flash->fsize = FSIZE_VAL(mtd->size);
 575         flash->prefetch_limit = mtd->size - STM32_QSPI_FIFO_SZ;
 576
 577         flash->read_mode = CCR_FMODE_MM;
 578         if (mtd->size > qspi->mm_size)
 579                 flash->read_mode = CCR_FMODE_INDR;
 580
 581         writel_relaxed(DCR_CSHT(1), qspi->io_base + QUADSPI_DCR);
 582
 583         ret = mtd_device_register(mtd, NULL, 0);
 584         if (ret) {
 585                 dev_err(qspi->dev, "mtd device parse failed\n");
 586                 return ret;
 587         }
 588
 589         flash->registered = true;
 590
 591         dev_dbg(qspi->dev, "read mm:%s cs:%d bus:%d\n",
 592                 flash->read_mode == CCR_FMODE_MM ? "yes" : "no", cs_num, width);
 593
 594         return 0;
 595 }
 596
 597 static void stm32_qspi_mtd_free(struct stm32_qspi *qspi)
 598 {
 599         int i;
 600
 601         for (i = 0; i < STM32_MAX_NORCHIP; i++)
 602                 if (qspi->flash[i].registered)
 603                         mtd_device_unregister(&qspi->flash[i].nor.mtd);
 604 }
 605
 606 static int stm32_qspi_probe(struct platform_device *pdev)
 607 {
 608         struct device *dev = &pdev->dev;
 609         struct device_node *flash_np;
 610         struct reset_control *rstc;
 611         struct stm32_qspi *qspi;
 612         struct resource *res;
 613         int ret, irq;
 614
 615         qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
 616         if (!qspi)
 617                 return -ENOMEM;
 618
 619         qspi->nor_num = of_get_child_count(dev->of_node);
 620         if (!qspi->nor_num || qspi->nor_num > STM32_MAX_NORCHIP)
 621                 return -ENODEV;
 622
 623         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
 624         qspi->io_base = devm_ioremap_resource(dev, res);
 625         if (IS_ERR(qspi->io_base))
 626                 return PTR_ERR(qspi->io_base);
 627
 628         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
 629         qspi->mm_base = devm_ioremap_resource(dev, res);
 630         if (IS_ERR(qspi->mm_base))
 631                 return PTR_ERR(qspi->mm_base);
 632
 633         qspi->mm_size = resource_size(res);
 634
 635         irq = platform_get_irq(pdev, 0);
 636         ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
 637                                dev_name(dev), qspi);
 638         if (ret) {
 639                 dev_err(dev, "failed to request irq\n");
 640                 return ret;
 641         }
 642
 643         init_completion(&qspi->cmd_completion);
 644
 645         qspi->clk = devm_clk_get(dev, NULL);
 646         if (IS_ERR(qspi->clk))
 647                 return PTR_ERR(qspi->clk);
 648
 649         qspi->clk_rate = clk_get_rate(qspi->clk);
 650         if (!qspi->clk_rate)
 651                 return -EINVAL;
 652
 653         ret = clk_prepare_enable(qspi->clk);
 654         if (ret) {
 655                 dev_err(dev, "can not enable the clock\n");
 656                 return ret;
 657         }
 658
 659         rstc = devm_reset_control_get(dev, NULL);
 660         if (!IS_ERR(rstc)) {
 661                 reset_control_assert(rstc);
 662                 udelay(2);
 663                 reset_control_deassert(rstc);
 664         }
 665
 666         qspi->dev = dev;
 667         platform_set_drvdata(pdev, qspi);
 668         mutex_init(&qspi->lock);
 669
 670         for_each_available_child_of_node(dev->of_node, flash_np) {
 671                 ret = stm32_qspi_flash_setup(qspi, flash_np);
 672                 if (ret) {
 673                         dev_err(dev, "unable to setup flash chip\n");
 674                         goto err_flash;
 675                 }
 676         }
 677
 678         return 0;
 679
 680 err_flash:
 681         mutex_destroy(&qspi->lock);
 682         stm32_qspi_mtd_free(qspi);
 683
 684         clk_disable_unprepare(qspi->clk);
 685         return ret;
 686 }
 687
 688 static int stm32_qspi_remove(struct platform_device *pdev)
 689 {
 690         struct stm32_qspi *qspi = platform_get_drvdata(pdev);
 691
 692         /* disable qspi */
 693         writel_relaxed(0, qspi->io_base + QUADSPI_CR);
 694
 695         stm32_qspi_mtd_free(qspi);
 696         mutex_destroy(&qspi->lock);
 697
 698         clk_disable_unprepare(qspi->clk);
 699         return 0;
 700 }
 701
 702 static const struct of_device_id stm32_qspi_match[] = {
 703         {.compatible = "st,stm32f469-qspi"},
 704         {}
 705 };
 706 MODULE_DEVICE_TABLE(of, stm32_qspi_match);
 707
 708 static struct platform_driver stm32_qspi_driver = {
 709         .probe  = stm32_qspi_probe,
 710         .remove = stm32_qspi_remove,
 711         .driver = {
 712                 .name = "stm32-quadspi",
 713                 .of_match_table = stm32_qspi_match,
 714         },
 715 };
 716 module_platform_driver(stm32_qspi_driver);
 717
 718 MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
 719 MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
 720 MODULE_LICENSE("GPL v2");