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Linux 4.16.11
[linux/fpc-iii.git] / drivers / net / dsa / lan9303-core.c
blob6171c0853ff112984a21f940891e253eb57ceb3b
1 /*
2 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/regmap.h>
18 #include <linux/mutex.h>
19 #include <linux/mii.h>
20 #include <linux/phy.h>
21 #include <linux/if_bridge.h>
22 #include <linux/etherdevice.h>
23
24 #include "lan9303.h"
25
26 #define LAN9303_NUM_PORTS 3
27
28 /* 13.2 System Control and Status Registers
29 * Multiply register number by 4 to get address offset.
30 */
31 #define LAN9303_CHIP_REV 0x14
32 # define LAN9303_CHIP_ID 0x9303
33 #define LAN9303_IRQ_CFG 0x15
34 # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8)
35 # define LAN9303_IRQ_CFG_IRQ_POL BIT(4)
36 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0)
37 #define LAN9303_INT_STS 0x16
38 # define LAN9303_INT_STS_PHY_INT2 BIT(27)
39 # define LAN9303_INT_STS_PHY_INT1 BIT(26)
40 #define LAN9303_INT_EN 0x17
41 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27)
42 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26)
43 #define LAN9303_HW_CFG 0x1D
44 # define LAN9303_HW_CFG_READY BIT(27)
45 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26)
46 # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25)
47 #define LAN9303_PMI_DATA 0x29
48 #define LAN9303_PMI_ACCESS 0x2A
49 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11)
50 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6)
51 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0)
52 # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1)
53 #define LAN9303_MANUAL_FC_1 0x68
54 #define LAN9303_MANUAL_FC_2 0x69
55 #define LAN9303_MANUAL_FC_0 0x6a
56 #define LAN9303_SWITCH_CSR_DATA 0x6b
57 #define LAN9303_SWITCH_CSR_CMD 0x6c
58 #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31)
59 #define LAN9303_SWITCH_CSR_CMD_RW BIT(30)
60 #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16))
61 #define LAN9303_VIRT_PHY_BASE 0x70
62 #define LAN9303_VIRT_SPECIAL_CTRL 0x77
63 #define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/
64
65 /*13.4 Switch Fabric Control and Status Registers
66 * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA.
67 */
68 #define LAN9303_SW_DEV_ID 0x0000
69 #define LAN9303_SW_RESET 0x0001
70 #define LAN9303_SW_RESET_RESET BIT(0)
71 #define LAN9303_SW_IMR 0x0004
72 #define LAN9303_SW_IPR 0x0005
73 #define LAN9303_MAC_VER_ID_0 0x0400
74 #define LAN9303_MAC_RX_CFG_0 0x0401
75 # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1)
76 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0)
77 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410
78 #define LAN9303_MAC_RX_64_CNT_0 0x0411
79 #define LAN9303_MAC_RX_127_CNT_0 0x0412
80 #define LAN9303_MAC_RX_255_CNT_0 0x413
81 #define LAN9303_MAC_RX_511_CNT_0 0x0414
82 #define LAN9303_MAC_RX_1023_CNT_0 0x0415
83 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416
84 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417
85 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418
86 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419
87 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a
88 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b
89 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c
90 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d
91 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e
92 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f
93 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420
94 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421
95 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422
96 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423
97
98 #define LAN9303_MAC_TX_CFG_0 0x0440
99 # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2)
100 # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1)
101 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0)
102 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451
103 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452
104 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453
105 #define LAN9303_MAC_TX_64_CNT_0 0x0454
106 #define LAN9303_MAC_TX_127_CNT_0 0x0455
107 #define LAN9303_MAC_TX_255_CNT_0 0x0456
108 #define LAN9303_MAC_TX_511_CNT_0 0x0457
109 #define LAN9303_MAC_TX_1023_CNT_0 0x0458
110 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459
111 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a
112 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c
113 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d
114 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e
115 #define LAN9303_MAC_TX_LATECOL_0 0x045f
116 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460
117 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461
118 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462
119 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463
120
121 #define LAN9303_MAC_VER_ID_1 0x0800
122 #define LAN9303_MAC_RX_CFG_1 0x0801
123 #define LAN9303_MAC_TX_CFG_1 0x0840
124 #define LAN9303_MAC_VER_ID_2 0x0c00
125 #define LAN9303_MAC_RX_CFG_2 0x0c01
126 #define LAN9303_MAC_TX_CFG_2 0x0c40
127 #define LAN9303_SWE_ALR_CMD 0x1800
128 # define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2)
129 # define LAN9303_ALR_CMD_GET_FIRST BIT(1)
130 # define LAN9303_ALR_CMD_GET_NEXT BIT(0)
131 #define LAN9303_SWE_ALR_WR_DAT_0 0x1801
132 #define LAN9303_SWE_ALR_WR_DAT_1 0x1802
133 # define LAN9303_ALR_DAT1_VALID BIT(26)
134 # define LAN9303_ALR_DAT1_END_OF_TABL BIT(25)
135 # define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25)
136 # define LAN9303_ALR_DAT1_STATIC BIT(24)
137 # define LAN9303_ALR_DAT1_PORT_BITOFFS 16
138 # define LAN9303_ALR_DAT1_PORT_MASK (7 << LAN9303_ALR_DAT1_PORT_BITOFFS)
139 #define LAN9303_SWE_ALR_RD_DAT_0 0x1805
140 #define LAN9303_SWE_ALR_RD_DAT_1 0x1806
141 #define LAN9303_SWE_ALR_CMD_STS 0x1808
142 # define ALR_STS_MAKE_PEND BIT(0)
143 #define LAN9303_SWE_VLAN_CMD 0x180b
144 # define LAN9303_SWE_VLAN_CMD_RNW BIT(5)
145 # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4)
146 #define LAN9303_SWE_VLAN_WR_DATA 0x180c
147 #define LAN9303_SWE_VLAN_RD_DATA 0x180e
148 # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17)
149 # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16)
150 # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15)
151 # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14)
152 # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13)
153 # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12)
154 #define LAN9303_SWE_VLAN_CMD_STS 0x1810
155 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840
156 # define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7)
157 # define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p)
158 #define LAN9303_SWE_PORT_STATE 0x1843
159 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0)
160 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5)
161 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4)
162 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0)
163 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3)
164 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2)
165 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0)
166 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1)
167 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0)
168 # define LAN9303_SWE_PORT_STATE_DISABLED_PORT0 (3)
169 #define LAN9303_SWE_PORT_MIRROR 0x1846
170 # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8)
171 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7)
172 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6)
173 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5)
174 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4)
175 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3)
176 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2)
177 # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1)
178 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0)
179 # define LAN9303_SWE_PORT_MIRROR_DISABLED 0
180 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847
181 #define LAN9303_SWE_INGRESS_PORT_TYPE_VLAN 3
182 #define LAN9303_BM_CFG 0x1c00
183 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c
184 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16))
185 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8))
186 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0))
187
188 #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0))
189
190 /* the built-in PHYs are of type LAN911X */
191 #define MII_LAN911X_SPECIAL_MODES 0x12
192 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f
193
194 static const struct regmap_range lan9303_valid_regs[] = {
195 regmap_reg_range(0x14, 0x17), /* misc, interrupt */
196 regmap_reg_range(0x19, 0x19), /* endian test */
197 regmap_reg_range(0x1d, 0x1d), /* hardware config */
198 regmap_reg_range(0x23, 0x24), /* general purpose timer */
199 regmap_reg_range(0x27, 0x27), /* counter */
200 regmap_reg_range(0x29, 0x2a), /* PMI index regs */
201 regmap_reg_range(0x68, 0x6a), /* flow control */
202 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */
203 regmap_reg_range(0x6d, 0x6f), /* misc */
204 regmap_reg_range(0x70, 0x77), /* virtual phy */
205 regmap_reg_range(0x78, 0x7a), /* GPIO */
206 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */
207 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */
208 };
209
210 static const struct regmap_range lan9303_reserved_ranges[] = {
211 regmap_reg_range(0x00, 0x13),
212 regmap_reg_range(0x18, 0x18),
213 regmap_reg_range(0x1a, 0x1c),
214 regmap_reg_range(0x1e, 0x22),
215 regmap_reg_range(0x25, 0x26),
216 regmap_reg_range(0x28, 0x28),
217 regmap_reg_range(0x2b, 0x67),
218 regmap_reg_range(0x7b, 0x7b),
219 regmap_reg_range(0x7f, 0x7f),
220 regmap_reg_range(0xb8, 0xff),
221 };
222
223 const struct regmap_access_table lan9303_register_set = {
224 .yes_ranges = lan9303_valid_regs,
225 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs),
226 .no_ranges = lan9303_reserved_ranges,
227 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges),
228 };
229 EXPORT_SYMBOL(lan9303_register_set);
230
231 static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg)
232 {
233 int ret, i;
234
235 /* we can lose arbitration for the I2C case, because the device
236 * tries to detect and read an external EEPROM after reset and acts as
237 * a master on the shared I2C bus itself. This conflicts with our
238 * attempts to access the device as a slave at the same moment.
239 */
240 for (i = 0; i < 5; i++) {
241 ret = regmap_read(regmap, offset, reg);
242 if (!ret)
243 return 0;
244 if (ret != -EAGAIN)
245 break;
246 msleep(500);
247 }
248
249 return -EIO;
250 }
251
252 static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask)
253 {
254 int i;
255
256 for (i = 0; i < 25; i++) {
257 u32 reg;
258 int ret;
259
260 ret = lan9303_read(chip->regmap, offset, &reg);
261 if (ret) {
262 dev_err(chip->dev, "%s failed to read offset %d: %d\n",
263 __func__, offset, ret);
264 return ret;
265 }
266 if (!(reg & mask))
267 return 0;
268 usleep_range(1000, 2000);
269 }
270
271 return -ETIMEDOUT;
272 }
273
274 static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum)
275 {
276 int ret;
277 u32 val;
278
279 if (regnum > MII_EXPANSION)
280 return -EINVAL;
281
282 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val);
283 if (ret)
284 return ret;
285
286 return val & 0xffff;
287 }
288
289 static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val)
290 {
291 if (regnum > MII_EXPANSION)
292 return -EINVAL;
293
294 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val);
295 }
296
297 static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip)
298 {
299 return lan9303_read_wait(chip, LAN9303_PMI_ACCESS,
300 LAN9303_PMI_ACCESS_MII_BUSY);
301 }
302
303 static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum)
304 {
305 int ret;
306 u32 val;
307
308 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
309 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
310
311 mutex_lock(&chip->indirect_mutex);
312
313 ret = lan9303_indirect_phy_wait_for_completion(chip);
314 if (ret)
315 goto on_error;
316
317 /* start the MII read cycle */
318 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val);
319 if (ret)
320 goto on_error;
321
322 ret = lan9303_indirect_phy_wait_for_completion(chip);
323 if (ret)
324 goto on_error;
325
326 /* read the result of this operation */
327 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val);
328 if (ret)
329 goto on_error;
330
331 mutex_unlock(&chip->indirect_mutex);
332
333 return val & 0xffff;
334
335 on_error:
336 mutex_unlock(&chip->indirect_mutex);
337 return ret;
338 }
339
340 static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr,
341 int regnum, u16 val)
342 {
343 int ret;
344 u32 reg;
345
346 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
347 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
348 reg |= LAN9303_PMI_ACCESS_MII_WRITE;
349
350 mutex_lock(&chip->indirect_mutex);
351
352 ret = lan9303_indirect_phy_wait_for_completion(chip);
353 if (ret)
354 goto on_error;
355
356 /* write the data first... */
357 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val);
358 if (ret)
359 goto on_error;
360
361 /* ...then start the MII write cycle */
362 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg);
363
364 on_error:
365 mutex_unlock(&chip->indirect_mutex);
366 return ret;
367 }
368
369 const struct lan9303_phy_ops lan9303_indirect_phy_ops = {
370 .phy_read = lan9303_indirect_phy_read,
371 .phy_write = lan9303_indirect_phy_write,
372 };
373 EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops);
374
375 static int lan9303_switch_wait_for_completion(struct lan9303 *chip)
376 {
377 return lan9303_read_wait(chip, LAN9303_SWITCH_CSR_CMD,
378 LAN9303_SWITCH_CSR_CMD_BUSY);
379 }
380
381 static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val)
382 {
383 u32 reg;
384 int ret;
385
386 reg = regnum;
387 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
388 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
389
390 mutex_lock(&chip->indirect_mutex);
391
392 ret = lan9303_switch_wait_for_completion(chip);
393 if (ret)
394 goto on_error;
395
396 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
397 if (ret) {
398 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret);
399 goto on_error;
400 }
401
402 /* trigger write */
403 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
404 if (ret)
405 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
406 ret);
407
408 on_error:
409 mutex_unlock(&chip->indirect_mutex);
410 return ret;
411 }
412
413 static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val)
414 {
415 u32 reg;
416 int ret;
417
418 reg = regnum;
419 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
420 reg |= LAN9303_SWITCH_CSR_CMD_RW;
421 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
422
423 mutex_lock(&chip->indirect_mutex);
424
425 ret = lan9303_switch_wait_for_completion(chip);
426 if (ret)
427 goto on_error;
428
429 /* trigger read */
430 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
431 if (ret) {
432 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
433 ret);
434 goto on_error;
435 }
436
437 ret = lan9303_switch_wait_for_completion(chip);
438 if (ret)
439 goto on_error;
440
441 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
442 if (ret)
443 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret);
444 on_error:
445 mutex_unlock(&chip->indirect_mutex);
446 return ret;
447 }
448
449 static int lan9303_write_switch_reg_mask(struct lan9303 *chip, u16 regnum,
450 u32 val, u32 mask)
451 {
452 int ret;
453 u32 reg;
454
455 ret = lan9303_read_switch_reg(chip, regnum, &reg);
456 if (ret)
457 return ret;
458
459 reg = (reg & ~mask) | val;
460
461 return lan9303_write_switch_reg(chip, regnum, reg);
462 }
463
464 static int lan9303_write_switch_port(struct lan9303 *chip, int port,
465 u16 regnum, u32 val)
466 {
467 return lan9303_write_switch_reg(
468 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
469 }
470
471 static int lan9303_read_switch_port(struct lan9303 *chip, int port,
472 u16 regnum, u32 *val)
473 {
474 return lan9303_read_switch_reg(
475 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
476 }
477
478 static int lan9303_detect_phy_setup(struct lan9303 *chip)
479 {
480 int reg;
481
482 /* Calculate chip->phy_addr_base:
483 * Depending on the 'phy_addr_sel_strap' setting, the three phys are
484 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the
485 * 'phy_addr_sel_strap' setting directly, so we need a test, which
486 * configuration is active:
487 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0
488 * and the IDs are 0-1-2, else it contains something different from
489 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3.
490 * 0xffff is returned on MDIO read with no response.
491 */
492 reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES);
493 if (reg < 0) {
494 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg);
495 return reg;
496 }
497
498 chip->phy_addr_base = reg != 0 && reg != 0xffff;
499
500 dev_dbg(chip->dev, "Phy setup '%s' detected\n",
501 chip->phy_addr_base ? "1-2-3" : "0-1-2");
502
503 return 0;
504 }
505
506 /* Map ALR-port bits to port bitmap, and back */
507 static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 };
508 static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 };
509
510 /* Return pointer to first free ALR cache entry, return NULL if none */
511 static struct lan9303_alr_cache_entry *
512 lan9303_alr_cache_find_free(struct lan9303 *chip)
513 {
514 int i;
515 struct lan9303_alr_cache_entry *entr = chip->alr_cache;
516
517 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
518 if (entr->port_map == 0)
519 return entr;
520
521 return NULL;
522 }
523
524 /* Return pointer to ALR cache entry matching MAC address */
525 static struct lan9303_alr_cache_entry *
526 lan9303_alr_cache_find_mac(struct lan9303 *chip, const u8 *mac_addr)
527 {
528 int i;
529 struct lan9303_alr_cache_entry *entr = chip->alr_cache;
530
531 BUILD_BUG_ON_MSG(sizeof(struct lan9303_alr_cache_entry) & 1,
532 "ether_addr_equal require u16 alignment");
533
534 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
535 if (ether_addr_equal(entr->mac_addr, mac_addr))
536 return entr;
537
538 return NULL;
539 }
540
541 static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, u32 mask)
542 {
543 int i;
544
545 for (i = 0; i < 25; i++) {
546 u32 reg;
547
548 lan9303_read_switch_reg(chip, regno, &reg);
549 if (!(reg & mask))
550 return 0;
551 usleep_range(1000, 2000);
552 }
553
554 return -ETIMEDOUT;
555 }
556
557 static int lan9303_alr_make_entry_raw(struct lan9303 *chip, u32 dat0, u32 dat1)
558 {
559 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_0, dat0);
560 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_1, dat1);
561 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
562 LAN9303_ALR_CMD_MAKE_ENTRY);
563 lan9303_csr_reg_wait(chip, LAN9303_SWE_ALR_CMD_STS, ALR_STS_MAKE_PEND);
564 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
565
566 return 0;
567 }
568
569 typedef void alr_loop_cb_t(struct lan9303 *chip, u32 dat0, u32 dat1,
570 int portmap, void *ctx);
571
572 static void lan9303_alr_loop(struct lan9303 *chip, alr_loop_cb_t *cb, void *ctx)
573 {
574 int i;
575
576 mutex_lock(&chip->alr_mutex);
577 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
578 LAN9303_ALR_CMD_GET_FIRST);
579 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
580
581 for (i = 1; i < LAN9303_NUM_ALR_RECORDS; i++) {
582 u32 dat0, dat1;
583 int alrport, portmap;
584
585 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_0, &dat0);
586 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_1, &dat1);
587 if (dat1 & LAN9303_ALR_DAT1_END_OF_TABL)
588 break;
589
590 alrport = (dat1 & LAN9303_ALR_DAT1_PORT_MASK) >>
591 LAN9303_ALR_DAT1_PORT_BITOFFS;
592 portmap = alrport_2_portmap[alrport];
593
594 cb(chip, dat0, dat1, portmap, ctx);
595
596 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
597 LAN9303_ALR_CMD_GET_NEXT);
598 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
599 }
600 mutex_unlock(&chip->alr_mutex);
601 }
602
603 static void alr_reg_to_mac(u32 dat0, u32 dat1, u8 mac[6])
604 {
605 mac[0] = (dat0 >> 0) & 0xff;
606 mac[1] = (dat0 >> 8) & 0xff;
607 mac[2] = (dat0 >> 16) & 0xff;
608 mac[3] = (dat0 >> 24) & 0xff;
609 mac[4] = (dat1 >> 0) & 0xff;
610 mac[5] = (dat1 >> 8) & 0xff;
611 }
612
613 struct del_port_learned_ctx {
614 int port;
615 };
616
617 /* Clear learned (non-static) entry on given port */
618 static void alr_loop_cb_del_port_learned(struct lan9303 *chip, u32 dat0,
619 u32 dat1, int portmap, void *ctx)
620 {
621 struct del_port_learned_ctx *del_ctx = ctx;
622 int port = del_ctx->port;
623
624 if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC))
625 return;
626
627 /* learned entries has only one port, we can just delete */
628 dat1 &= ~LAN9303_ALR_DAT1_VALID; /* delete entry */
629 lan9303_alr_make_entry_raw(chip, dat0, dat1);
630 }
631
632 struct port_fdb_dump_ctx {
633 int port;
634 void *data;
635 dsa_fdb_dump_cb_t *cb;
636 };
637
638 static void alr_loop_cb_fdb_port_dump(struct lan9303 *chip, u32 dat0,
639 u32 dat1, int portmap, void *ctx)
640 {
641 struct port_fdb_dump_ctx *dump_ctx = ctx;
642 u8 mac[ETH_ALEN];
643 bool is_static;
644
645 if ((BIT(dump_ctx->port) & portmap) == 0)
646 return;
647
648 alr_reg_to_mac(dat0, dat1, mac);
649 is_static = !!(dat1 & LAN9303_ALR_DAT1_STATIC);
650 dump_ctx->cb(mac, 0, is_static, dump_ctx->data);
651 }
652
653 /* Set a static ALR entry. Delete entry if port_map is zero */
654 static void lan9303_alr_set_entry(struct lan9303 *chip, const u8 *mac,
655 u8 port_map, bool stp_override)
656 {
657 u32 dat0, dat1, alr_port;
658
659 dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map);
660 dat1 = LAN9303_ALR_DAT1_STATIC;
661 if (port_map)
662 dat1 |= LAN9303_ALR_DAT1_VALID;
663 /* otherwise no ports: delete entry */
664 if (stp_override)
665 dat1 |= LAN9303_ALR_DAT1_AGE_OVERRID;
666
667 alr_port = portmap_2_alrport[port_map & 7];
668 dat1 &= ~LAN9303_ALR_DAT1_PORT_MASK;
669 dat1 |= alr_port << LAN9303_ALR_DAT1_PORT_BITOFFS;
670
671 dat0 = 0;
672 dat0 |= (mac[0] << 0);
673 dat0 |= (mac[1] << 8);
674 dat0 |= (mac[2] << 16);
675 dat0 |= (mac[3] << 24);
676
677 dat1 |= (mac[4] << 0);
678 dat1 |= (mac[5] << 8);
679
680 lan9303_alr_make_entry_raw(chip, dat0, dat1);
681 }
682
683 /* Add port to static ALR entry, create new static entry if needed */
684 static int lan9303_alr_add_port(struct lan9303 *chip, const u8 *mac, int port,
685 bool stp_override)
686 {
687 struct lan9303_alr_cache_entry *entr;
688
689 mutex_lock(&chip->alr_mutex);
690 entr = lan9303_alr_cache_find_mac(chip, mac);
691 if (!entr) { /*New entry */
692 entr = lan9303_alr_cache_find_free(chip);
693 if (!entr) {
694 mutex_unlock(&chip->alr_mutex);
695 return -ENOSPC;
696 }
697 ether_addr_copy(entr->mac_addr, mac);
698 }
699 entr->port_map |= BIT(port);
700 entr->stp_override = stp_override;
701 lan9303_alr_set_entry(chip, mac, entr->port_map, stp_override);
702 mutex_unlock(&chip->alr_mutex);
703
704 return 0;
705 }
706
707 /* Delete static port from ALR entry, delete entry if last port */
708 static int lan9303_alr_del_port(struct lan9303 *chip, const u8 *mac, int port)
709 {
710 struct lan9303_alr_cache_entry *entr;
711
712 mutex_lock(&chip->alr_mutex);
713 entr = lan9303_alr_cache_find_mac(chip, mac);
714 if (!entr)
715 goto out; /* no static entry found */
716
717 entr->port_map &= ~BIT(port);
718 if (entr->port_map == 0) /* zero means its free again */
719 eth_zero_addr(entr->mac_addr);
720 lan9303_alr_set_entry(chip, mac, entr->port_map, entr->stp_override);
721
722 out:
723 mutex_unlock(&chip->alr_mutex);
724 return 0;
725 }
726
727 static int lan9303_disable_processing_port(struct lan9303 *chip,
728 unsigned int port)
729 {
730 int ret;
731
732 /* disable RX, but keep register reset default values else */
733 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
734 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES);
735 if (ret)
736 return ret;
737
738 /* disable TX, but keep register reset default values else */
739 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
740 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
741 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE);
742 }
743
744 static int lan9303_enable_processing_port(struct lan9303 *chip,
745 unsigned int port)
746 {
747 int ret;
748
749 /* enable RX and keep register reset default values else */
750 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
751 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES |
752 LAN9303_MAC_RX_CFG_X_RX_ENABLE);
753 if (ret)
754 return ret;
755
756 /* enable TX and keep register reset default values else */
757 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
758 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
759 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE |
760 LAN9303_MAC_TX_CFG_X_TX_ENABLE);
761 }
762
763 /* forward special tagged packets from port 0 to port 1 *or* port 2 */
764 static int lan9303_setup_tagging(struct lan9303 *chip)
765 {
766 int ret;
767 u32 val;
768 /* enable defining the destination port via special VLAN tagging
769 * for port 0
770 */
771 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE,
772 LAN9303_SWE_INGRESS_PORT_TYPE_VLAN);
773 if (ret)
774 return ret;
775
776 /* tag incoming packets at port 1 and 2 on their way to port 0 to be
777 * able to discover their source port
778 */
779 val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0;
780 return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val);
781 }
782
783 /* We want a special working switch:
784 * - do not forward packets between port 1 and 2
785 * - forward everything from port 1 to port 0
786 * - forward everything from port 2 to port 0
787 */
788 static int lan9303_separate_ports(struct lan9303 *chip)
789 {
790 int ret;
791
792 lan9303_alr_del_port(chip, eth_stp_addr, 0);
793 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
794 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 |
795 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 |
796 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 |
797 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING |
798 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL);
799 if (ret)
800 return ret;
801
802 /* prevent port 1 and 2 from forwarding packets by their own */
803 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
804 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 |
805 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 |
806 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2);
807 }
808
809 static void lan9303_bridge_ports(struct lan9303 *chip)
810 {
811 /* ports bridged: remove mirroring */
812 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
813 LAN9303_SWE_PORT_MIRROR_DISABLED);
814
815 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
816 chip->swe_port_state);
817 lan9303_alr_add_port(chip, eth_stp_addr, 0, true);
818 }
819
820 static void lan9303_handle_reset(struct lan9303 *chip)
821 {
822 if (!chip->reset_gpio)
823 return;
824
825 if (chip->reset_duration != 0)
826 msleep(chip->reset_duration);
827
828 /* release (deassert) reset and activate the device */
829 gpiod_set_value_cansleep(chip->reset_gpio, 0);
830 }
831
832 /* stop processing packets for all ports */
833 static int lan9303_disable_processing(struct lan9303 *chip)
834 {
835 int p;
836
837 for (p = 1; p < LAN9303_NUM_PORTS; p++) {
838 int ret = lan9303_disable_processing_port(chip, p);
839
840 if (ret)
841 return ret;
842 }
843
844 return 0;
845 }
846
847 static int lan9303_check_device(struct lan9303 *chip)
848 {
849 int ret;
850 u32 reg;
851
852 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, &reg);
853 if (ret) {
854 dev_err(chip->dev, "failed to read chip revision register: %d\n",
855 ret);
856 if (!chip->reset_gpio) {
857 dev_dbg(chip->dev,
858 "hint: maybe failed due to missing reset GPIO\n");
859 }
860 return ret;
861 }
862
863 if ((reg >> 16) != LAN9303_CHIP_ID) {
864 dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n",
865 reg >> 16);
866 return -ENODEV;
867 }
868
869 /* The default state of the LAN9303 device is to forward packets between
870 * all ports (if not configured differently by an external EEPROM).
871 * The initial state of a DSA device must be forwarding packets only
872 * between the external and the internal ports and no forwarding
873 * between the external ports. In preparation we stop packet handling
874 * at all for now until the LAN9303 device is re-programmed accordingly.
875 */
876 ret = lan9303_disable_processing(chip);
877 if (ret)
878 dev_warn(chip->dev, "failed to disable switching %d\n", ret);
879
880 dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff);
881
882 ret = lan9303_detect_phy_setup(chip);
883 if (ret) {
884 dev_err(chip->dev,
885 "failed to discover phy bootstrap setup: %d\n", ret);
886 return ret;
887 }
888
889 return 0;
890 }
891
892 /* ---------------------------- DSA -----------------------------------*/
893
894 static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds,
895 int port)
896 {
897 return DSA_TAG_PROTO_LAN9303;
898 }
899
900 static int lan9303_setup(struct dsa_switch *ds)
901 {
902 struct lan9303 *chip = ds->priv;
903 int ret;
904
905 /* Make sure that port 0 is the cpu port */
906 if (!dsa_is_cpu_port(ds, 0)) {
907 dev_err(chip->dev, "port 0 is not the CPU port\n");
908 return -EINVAL;
909 }
910
911 ret = lan9303_setup_tagging(chip);
912 if (ret)
913 dev_err(chip->dev, "failed to setup port tagging %d\n", ret);
914
915 ret = lan9303_separate_ports(chip);
916 if (ret)
917 dev_err(chip->dev, "failed to separate ports %d\n", ret);
918
919 ret = lan9303_enable_processing_port(chip, 0);
920 if (ret)
921 dev_err(chip->dev, "failed to re-enable switching %d\n", ret);
922
923 /* Trap IGMP to port 0 */
924 ret = lan9303_write_switch_reg_mask(chip, LAN9303_SWE_GLB_INGRESS_CFG,
925 LAN9303_SWE_GLB_INGR_IGMP_TRAP |
926 LAN9303_SWE_GLB_INGR_IGMP_PORT(0),
927 LAN9303_SWE_GLB_INGR_IGMP_PORT(1) |
928 LAN9303_SWE_GLB_INGR_IGMP_PORT(2));
929 if (ret)
930 dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret);
931
932 return 0;
933 }
934
935 struct lan9303_mib_desc {
936 unsigned int offset; /* offset of first MAC */
937 const char *name;
938 };
939
940 static const struct lan9303_mib_desc lan9303_mib[] = {
941 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", },
942 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", },
943 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", },
944 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", },
945 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", },
946 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", },
947 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", },
948 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", },
949 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", },
950 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", },
951 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", },
952 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", },
953 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", },
954 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", },
955 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", },
956 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", },
957 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", },
958 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", },
959 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", },
960 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", },
961 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", },
962 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", },
963 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "TxUnderRun", },
964 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", },
965 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", },
966 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", },
967 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", },
968 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", },
969 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", },
970 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", },
971 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", },
972 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", },
973 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", },
974 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", },
975 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", },
976 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", },
977 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", },
978 };
979
980 static void lan9303_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
981 {
982 unsigned int u;
983
984 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
985 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name,
986 ETH_GSTRING_LEN);
987 }
988 }
989
990 static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port,
991 uint64_t *data)
992 {
993 struct lan9303 *chip = ds->priv;
994 unsigned int u;
995
996 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
997 u32 reg;
998 int ret;
999
1000 ret = lan9303_read_switch_port(
1001 chip, port, lan9303_mib[u].offset, &reg);
1002
1003 if (ret)
1004 dev_warn(chip->dev, "Reading status port %d reg %u failed\n",
1005 port, lan9303_mib[u].offset);
1006 data[u] = reg;
1007 }
1008 }
1009
1010 static int lan9303_get_sset_count(struct dsa_switch *ds)
1011 {
1012 return ARRAY_SIZE(lan9303_mib);
1013 }
1014
1015 static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum)
1016 {
1017 struct lan9303 *chip = ds->priv;
1018 int phy_base = chip->phy_addr_base;
1019
1020 if (phy == phy_base)
1021 return lan9303_virt_phy_reg_read(chip, regnum);
1022 if (phy > phy_base + 2)
1023 return -ENODEV;
1024
1025 return chip->ops->phy_read(chip, phy, regnum);
1026 }
1027
1028 static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum,
1029 u16 val)
1030 {
1031 struct lan9303 *chip = ds->priv;
1032 int phy_base = chip->phy_addr_base;
1033
1034 if (phy == phy_base)
1035 return lan9303_virt_phy_reg_write(chip, regnum, val);
1036 if (phy > phy_base + 2)
1037 return -ENODEV;
1038
1039 return chip->ops->phy_write(chip, phy, regnum, val);
1040 }
1041
1042 static void lan9303_adjust_link(struct dsa_switch *ds, int port,
1043 struct phy_device *phydev)
1044 {
1045 struct lan9303 *chip = ds->priv;
1046 int ctl, res;
1047
1048 if (!phy_is_pseudo_fixed_link(phydev))
1049 return;
1050
1051 ctl = lan9303_phy_read(ds, port, MII_BMCR);
1052
1053 ctl &= ~BMCR_ANENABLE;
1054
1055 if (phydev->speed == SPEED_100)
1056 ctl |= BMCR_SPEED100;
1057 else if (phydev->speed == SPEED_10)
1058 ctl &= ~BMCR_SPEED100;
1059 else
1060 dev_err(ds->dev, "unsupported speed: %d\n", phydev->speed);
1061
1062 if (phydev->duplex == DUPLEX_FULL)
1063 ctl |= BMCR_FULLDPLX;
1064 else
1065 ctl &= ~BMCR_FULLDPLX;
1066
1067 res = lan9303_phy_write(ds, port, MII_BMCR, ctl);
1068
1069 if (port == chip->phy_addr_base) {
1070 /* Virtual Phy: Remove Turbo 200Mbit mode */
1071 lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, &ctl);
1072
1073 ctl &= ~LAN9303_VIRT_SPECIAL_TURBO;
1074 res = regmap_write(chip->regmap,
1075 LAN9303_VIRT_SPECIAL_CTRL, ctl);
1076 }
1077 }
1078
1079 static int lan9303_port_enable(struct dsa_switch *ds, int port,
1080 struct phy_device *phy)
1081 {
1082 struct lan9303 *chip = ds->priv;
1083
1084 return lan9303_enable_processing_port(chip, port);
1085 }
1086
1087 static void lan9303_port_disable(struct dsa_switch *ds, int port,
1088 struct phy_device *phy)
1089 {
1090 struct lan9303 *chip = ds->priv;
1091
1092 lan9303_disable_processing_port(chip, port);
1093 lan9303_phy_write(ds, chip->phy_addr_base + port, MII_BMCR, BMCR_PDOWN);
1094 }
1095
1096 static int lan9303_port_bridge_join(struct dsa_switch *ds, int port,
1097 struct net_device *br)
1098 {
1099 struct lan9303 *chip = ds->priv;
1100
1101 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
1102 if (dsa_to_port(ds, 1)->bridge_dev == dsa_to_port(ds, 2)->bridge_dev) {
1103 lan9303_bridge_ports(chip);
1104 chip->is_bridged = true; /* unleash stp_state_set() */
1105 }
1106
1107 return 0;
1108 }
1109
1110 static void lan9303_port_bridge_leave(struct dsa_switch *ds, int port,
1111 struct net_device *br)
1112 {
1113 struct lan9303 *chip = ds->priv;
1114
1115 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
1116 if (chip->is_bridged) {
1117 lan9303_separate_ports(chip);
1118 chip->is_bridged = false;
1119 }
1120 }
1121
1122 static void lan9303_port_stp_state_set(struct dsa_switch *ds, int port,
1123 u8 state)
1124 {
1125 int portmask, portstate;
1126 struct lan9303 *chip = ds->priv;
1127
1128 dev_dbg(chip->dev, "%s(port %d, state %d)\n",
1129 __func__, port, state);
1130
1131 switch (state) {
1132 case BR_STATE_DISABLED:
1133 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
1134 break;
1135 case BR_STATE_BLOCKING:
1136 case BR_STATE_LISTENING:
1137 portstate = LAN9303_SWE_PORT_STATE_BLOCKING_PORT0;
1138 break;
1139 case BR_STATE_LEARNING:
1140 portstate = LAN9303_SWE_PORT_STATE_LEARNING_PORT0;
1141 break;
1142 case BR_STATE_FORWARDING:
1143 portstate = LAN9303_SWE_PORT_STATE_FORWARDING_PORT0;
1144 break;
1145 default:
1146 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
1147 dev_err(chip->dev, "unknown stp state: port %d, state %d\n",
1148 port, state);
1149 }
1150
1151 portmask = 0x3 << (port * 2);
1152 portstate <<= (port * 2);
1153
1154 chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate;
1155
1156 if (chip->is_bridged)
1157 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
1158 chip->swe_port_state);
1159 /* else: touching SWE_PORT_STATE would break port separation */
1160 }
1161
1162 static void lan9303_port_fast_age(struct dsa_switch *ds, int port)
1163 {
1164 struct lan9303 *chip = ds->priv;
1165 struct del_port_learned_ctx del_ctx = {
1166 .port = port,
1167 };
1168
1169 dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
1170 lan9303_alr_loop(chip, alr_loop_cb_del_port_learned, &del_ctx);
1171 }
1172
1173 static int lan9303_port_fdb_add(struct dsa_switch *ds, int port,
1174 const unsigned char *addr, u16 vid)
1175 {
1176 struct lan9303 *chip = ds->priv;
1177
1178 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
1179 if (vid)
1180 return -EOPNOTSUPP;
1181
1182 return lan9303_alr_add_port(chip, addr, port, false);
1183 }
1184
1185 static int lan9303_port_fdb_del(struct dsa_switch *ds, int port,
1186 const unsigned char *addr, u16 vid)
1187
1188 {
1189 struct lan9303 *chip = ds->priv;
1190
1191 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
1192 if (vid)
1193 return -EOPNOTSUPP;
1194 lan9303_alr_del_port(chip, addr, port);
1195
1196 return 0;
1197 }
1198
1199 static int lan9303_port_fdb_dump(struct dsa_switch *ds, int port,
1200 dsa_fdb_dump_cb_t *cb, void *data)
1201 {
1202 struct lan9303 *chip = ds->priv;
1203 struct port_fdb_dump_ctx dump_ctx = {
1204 .port = port,
1205 .data = data,
1206 .cb = cb,
1207 };
1208
1209 dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
1210 lan9303_alr_loop(chip, alr_loop_cb_fdb_port_dump, &dump_ctx);
1211
1212 return 0;
1213 }
1214
1215 static int lan9303_port_mdb_prepare(struct dsa_switch *ds, int port,
1216 const struct switchdev_obj_port_mdb *mdb)
1217 {
1218 struct lan9303 *chip = ds->priv;
1219
1220 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1221 mdb->vid);
1222 if (mdb->vid)
1223 return -EOPNOTSUPP;
1224 if (lan9303_alr_cache_find_mac(chip, mdb->addr))
1225 return 0;
1226 if (!lan9303_alr_cache_find_free(chip))
1227 return -ENOSPC;
1228
1229 return 0;
1230 }
1231
1232 static void lan9303_port_mdb_add(struct dsa_switch *ds, int port,
1233 const struct switchdev_obj_port_mdb *mdb)
1234 {
1235 struct lan9303 *chip = ds->priv;
1236
1237 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1238 mdb->vid);
1239 lan9303_alr_add_port(chip, mdb->addr, port, false);
1240 }
1241
1242 static int lan9303_port_mdb_del(struct dsa_switch *ds, int port,
1243 const struct switchdev_obj_port_mdb *mdb)
1244 {
1245 struct lan9303 *chip = ds->priv;
1246
1247 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1248 mdb->vid);
1249 if (mdb->vid)
1250 return -EOPNOTSUPP;
1251 lan9303_alr_del_port(chip, mdb->addr, port);
1252
1253 return 0;
1254 }
1255
1256 static const struct dsa_switch_ops lan9303_switch_ops = {
1257 .get_tag_protocol = lan9303_get_tag_protocol,
1258 .setup = lan9303_setup,
1259 .get_strings = lan9303_get_strings,
1260 .phy_read = lan9303_phy_read,
1261 .phy_write = lan9303_phy_write,
1262 .adjust_link = lan9303_adjust_link,
1263 .get_ethtool_stats = lan9303_get_ethtool_stats,
1264 .get_sset_count = lan9303_get_sset_count,
1265 .port_enable = lan9303_port_enable,
1266 .port_disable = lan9303_port_disable,
1267 .port_bridge_join = lan9303_port_bridge_join,
1268 .port_bridge_leave = lan9303_port_bridge_leave,
1269 .port_stp_state_set = lan9303_port_stp_state_set,
1270 .port_fast_age = lan9303_port_fast_age,
1271 .port_fdb_add = lan9303_port_fdb_add,
1272 .port_fdb_del = lan9303_port_fdb_del,
1273 .port_fdb_dump = lan9303_port_fdb_dump,
1274 .port_mdb_prepare = lan9303_port_mdb_prepare,
1275 .port_mdb_add = lan9303_port_mdb_add,
1276 .port_mdb_del = lan9303_port_mdb_del,
1277 };
1278
1279 static int lan9303_register_switch(struct lan9303 *chip)
1280 {
1281 int base;
1282
1283 chip->ds = dsa_switch_alloc(chip->dev, LAN9303_NUM_PORTS);
1284 if (!chip->ds)
1285 return -ENOMEM;
1286
1287 chip->ds->priv = chip;
1288 chip->ds->ops = &lan9303_switch_ops;
1289 base = chip->phy_addr_base;
1290 chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1 + base, base);
1291
1292 return dsa_register_switch(chip->ds);
1293 }
1294
1295 static int lan9303_probe_reset_gpio(struct lan9303 *chip,
1296 struct device_node *np)
1297 {
1298 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset",
1299 GPIOD_OUT_LOW);
1300 if (IS_ERR(chip->reset_gpio))
1301 return PTR_ERR(chip->reset_gpio);
1302
1303 if (!chip->reset_gpio) {
1304 dev_dbg(chip->dev, "No reset GPIO defined\n");
1305 return 0;
1306 }
1307
1308 chip->reset_duration = 200;
1309
1310 if (np) {
1311 of_property_read_u32(np, "reset-duration",
1312 &chip->reset_duration);
1313 } else {
1314 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n");
1315 }
1316
1317 /* A sane reset duration should not be longer than 1s */
1318 if (chip->reset_duration > 1000)
1319 chip->reset_duration = 1000;
1320
1321 return 0;
1322 }
1323
1324 int lan9303_probe(struct lan9303 *chip, struct device_node *np)
1325 {
1326 int ret;
1327
1328 mutex_init(&chip->indirect_mutex);
1329 mutex_init(&chip->alr_mutex);
1330
1331 ret = lan9303_probe_reset_gpio(chip, np);
1332 if (ret)
1333 return ret;
1334
1335 lan9303_handle_reset(chip);
1336
1337 ret = lan9303_check_device(chip);
1338 if (ret)
1339 return ret;
1340
1341 ret = lan9303_register_switch(chip);
1342 if (ret) {
1343 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret);
1344 return ret;
1345 }
1346
1347 return 0;
1348 }
1349 EXPORT_SYMBOL(lan9303_probe);
1350
1351 int lan9303_remove(struct lan9303 *chip)
1352 {
1353 int rc;
1354
1355 rc = lan9303_disable_processing(chip);
1356 if (rc != 0)
1357 dev_warn(chip->dev, "shutting down failed\n");
1358
1359 dsa_unregister_switch(chip->ds);
1360
1361 /* assert reset to the whole device to prevent it from doing anything */
1362 gpiod_set_value_cansleep(chip->reset_gpio, 1);
1363 gpiod_unexport(chip->reset_gpio);
1364
1365 return 0;
1366 }
1367 EXPORT_SYMBOL(lan9303_remove);
1368
1369 MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>");
1370 MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch");
1371 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support