drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h

   1 /* Applied Micro X-Gene SoC Ethernet Driver
   2  *
   3  * Copyright (c) 2014, Applied Micro Circuits Corporation
   4  * Authors: Iyappan Subramanian <isubramanian@apm.com>
   5  *          Keyur Chudgar <kchudgar@apm.com>
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef __XGENE_ENET_XGMAC_H__
  22 #define __XGENE_ENET_XGMAC_H__
  23
  24 #define X2_BLOCK_ETH_MAC_CSR_OFFSET     0x3000
  25 #define BLOCK_AXG_MAC_OFFSET            0x0800
  26 #define BLOCK_AXG_STATS_OFFSET          0x0800
  27 #define BLOCK_AXG_MAC_CSR_OFFSET        0x2000
  28 #define BLOCK_PCS_OFFSET                0x3800
  29
  30 #define XGENET_CONFIG_REG_ADDR          0x20
  31 #define XGENET_SRST_ADDR                0x00
  32 #define XGENET_CLKEN_ADDR               0x08
  33
  34 #define CSR_CLK         BIT(0)
  35 #define XGENET_CLK      BIT(1)
  36 #define PCS_CLK         BIT(3)
  37 #define AN_REF_CLK      BIT(4)
  38 #define AN_CLK          BIT(5)
  39 #define AD_CLK          BIT(6)
  40
  41 #define CSR_RST         BIT(0)
  42 #define XGENET_RST      BIT(1)
  43 #define PCS_RST         BIT(3)
  44 #define AN_REF_RST      BIT(4)
  45 #define AN_RST          BIT(5)
  46 #define AD_RST          BIT(6)
  47
  48 #define AXGMAC_CONFIG_0                 0x0000
  49 #define AXGMAC_CONFIG_1                 0x0004
  50 #define HSTMACRST                       BIT(31)
  51 #define HSTTCTLEN                       BIT(31)
  52 #define HSTTFEN                         BIT(30)
  53 #define HSTRCTLEN                       BIT(29)
  54 #define HSTRFEN                         BIT(28)
  55 #define HSTPPEN                         BIT(7)
  56 #define HSTDRPLT64                      BIT(5)
  57 #define HSTLENCHK                       BIT(3)
  58 #define HSTMACADR_LSW_ADDR              0x0010
  59 #define HSTMACADR_MSW_ADDR              0x0014
  60 #define HSTMAXFRAME_LENGTH_ADDR         0x0020
  61
  62 #define XG_MCX_RX_DV_GATE_REG_0_ADDR    0x0004
  63 #define XG_MCX_ECM_CFG_0_ADDR           0x0074
  64 #define XG_MCX_MULTI_DPF0_ADDR          0x007c
  65 #define XG_MCX_MULTI_DPF1_ADDR          0x0080
  66 #define XG_DEF_PAUSE_THRES              0x390
  67 #define XG_DEF_PAUSE_OFF_THRES          0x2c0
  68 #define XG_RSIF_CONFIG_REG_ADDR         0x00a0
  69 #define XG_RSIF_CLE_BUFF_THRESH                0x3
  70 #define RSIF_CLE_BUFF_THRESH_SET(dst, val)     xgene_set_bits(dst, val, 0, 3)
  71 #define XG_RSIF_CONFIG1_REG_ADDR       0x00b8
  72 #define XG_RSIF_PLC_CLE_BUFF_THRESH    0x1
  73 #define RSIF_PLC_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 2)
  74 #define XG_MCX_ECM_CONFIG0_REG_0_ADDR          0x0070
  75 #define XG_MCX_ICM_ECM_DROP_COUNT_REG0_ADDR    0x0124
  76 #define XCLE_BYPASS_REG0_ADDR           0x0160
  77 #define XCLE_BYPASS_REG1_ADDR           0x0164
  78 #define XG_CFG_BYPASS_ADDR              0x0204
  79 #define XG_CFG_LINK_AGGR_RESUME_0_ADDR  0x0214
  80 #define XG_LINK_STATUS_ADDR             0x0228
  81 #define XG_TSIF_MSS_REG0_ADDR           0x02a4
  82 #define XG_DEBUG_REG_ADDR               0x0400
  83 #define XG_ENET_SPARE_CFG_REG_ADDR      0x040c
  84 #define XG_ENET_SPARE_CFG_REG_1_ADDR    0x0410
  85 #define XGENET_RX_DV_GATE_REG_0_ADDR    0x0804
  86 #define XGENET_ECM_CONFIG0_REG_0        0x0870
  87 #define XGENET_ICM_ECM_DROP_COUNT_REG0  0x0924
  88 #define XGENET_CSR_ECM_CFG_0_ADDR       0x0880
  89 #define XGENET_CSR_MULTI_DPF0_ADDR      0x0888
  90 #define XGENET_CSR_MULTI_DPF1_ADDR      0x088c
  91 #define XG_RXBUF_PAUSE_THRESH           0x0020
  92 #define XG_MCX_ICM_CONFIG0_REG_0_ADDR   0x00e0
  93 #define XG_MCX_ICM_CONFIG2_REG_0_ADDR   0x00e8
  94
  95 #define PCS_CONTROL_1                   0x0000
  96 #define PCS_CTRL_PCS_RST                BIT(15)
  97
  98 extern const struct xgene_mac_ops xgene_xgmac_ops;
  99 extern const struct xgene_port_ops xgene_xgport_ops;
 100
 101 #endif /* __XGENE_ENET_XGMAC_H__ */