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Linux 4.16.11
[linux/fpc-iii.git] / drivers / net / ethernet / hisilicon / hns / hns_dsaf_main.c
blobe0bc79ea3d88091c5723403c724a5d4460f93e99
1 /*
2 * Copyright (c) 2014-2015 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/vmalloc.h>
24
25 #include "hns_dsaf_mac.h"
26 #include "hns_dsaf_main.h"
27 #include "hns_dsaf_ppe.h"
28 #include "hns_dsaf_rcb.h"
29 #include "hns_dsaf_misc.h"
30
31 const char *g_dsaf_mode_match[DSAF_MODE_MAX] = {
32 [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf",
33 [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss",
34 [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf",
35 [DSAF_MODE_DISABLE_SP] = "single-port",
36 };
37
38 static const struct acpi_device_id hns_dsaf_acpi_match[] = {
39 { "HISI00B1", 0 },
40 { "HISI00B2", 0 },
41 { },
42 };
43 MODULE_DEVICE_TABLE(acpi, hns_dsaf_acpi_match);
44
45 int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev)
46 {
47 int ret, i;
48 u32 desc_num;
49 u32 buf_size;
50 u32 reset_offset = 0;
51 u32 res_idx = 0;
52 const char *mode_str;
53 struct regmap *syscon;
54 struct resource *res;
55 struct device_node *np = dsaf_dev->dev->of_node, *np_temp;
56 struct platform_device *pdev = to_platform_device(dsaf_dev->dev);
57
58 if (dev_of_node(dsaf_dev->dev)) {
59 if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1"))
60 dsaf_dev->dsaf_ver = AE_VERSION_1;
61 else
62 dsaf_dev->dsaf_ver = AE_VERSION_2;
63 } else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
64 if (acpi_dev_found(hns_dsaf_acpi_match[0].id))
65 dsaf_dev->dsaf_ver = AE_VERSION_1;
66 else if (acpi_dev_found(hns_dsaf_acpi_match[1].id))
67 dsaf_dev->dsaf_ver = AE_VERSION_2;
68 else
69 return -ENXIO;
70 } else {
71 dev_err(dsaf_dev->dev, "cannot get cfg data from of or acpi\n");
72 return -ENXIO;
73 }
74
75 ret = device_property_read_string(dsaf_dev->dev, "mode", &mode_str);
76 if (ret) {
77 dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret);
78 return ret;
79 }
80 for (i = 0; i < DSAF_MODE_MAX; i++) {
81 if (g_dsaf_mode_match[i] &&
82 !strcmp(mode_str, g_dsaf_mode_match[i]))
83 break;
84 }
85 if (i >= DSAF_MODE_MAX ||
86 i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) {
87 dev_err(dsaf_dev->dev,
88 "%s prs mode str fail!\n", dsaf_dev->ae_dev.name);
89 return -EINVAL;
90 }
91 dsaf_dev->dsaf_mode = (enum dsaf_mode)i;
92
93 if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE)
94 dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE;
95 else
96 dsaf_dev->dsaf_en = HRD_DSAF_MODE;
97
98 if ((i == DSAF_MODE_ENABLE_16VM) ||
99 (i == DSAF_MODE_DISABLE_2PORT_8VM) ||
100 (i == DSAF_MODE_DISABLE_6PORT_2VM))
101 dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE;
102 else
103 dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE;
104
105 if (dev_of_node(dsaf_dev->dev)) {
106 np_temp = of_parse_phandle(np, "subctrl-syscon", 0);
107 syscon = syscon_node_to_regmap(np_temp);
108 of_node_put(np_temp);
109 if (IS_ERR_OR_NULL(syscon)) {
110 res = platform_get_resource(pdev, IORESOURCE_MEM,
111 res_idx++);
112 if (!res) {
113 dev_err(dsaf_dev->dev, "subctrl info is needed!\n");
114 return -ENOMEM;
115 }
116
117 dsaf_dev->sc_base = devm_ioremap_resource(&pdev->dev,
118 res);
119 if (IS_ERR(dsaf_dev->sc_base))
120 return PTR_ERR(dsaf_dev->sc_base);
121
122 res = platform_get_resource(pdev, IORESOURCE_MEM,
123 res_idx++);
124 if (!res) {
125 dev_err(dsaf_dev->dev, "serdes-ctrl info is needed!\n");
126 return -ENOMEM;
127 }
128
129 dsaf_dev->sds_base = devm_ioremap_resource(&pdev->dev,
130 res);
131 if (IS_ERR(dsaf_dev->sds_base))
132 return PTR_ERR(dsaf_dev->sds_base);
133 } else {
134 dsaf_dev->sub_ctrl = syscon;
135 }
136 }
137
138 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe-base");
139 if (!res) {
140 res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx++);
141 if (!res) {
142 dev_err(dsaf_dev->dev, "ppe-base info is needed!\n");
143 return -ENOMEM;
144 }
145 }
146 dsaf_dev->ppe_base = devm_ioremap_resource(&pdev->dev, res);
147 if (IS_ERR(dsaf_dev->ppe_base))
148 return PTR_ERR(dsaf_dev->ppe_base);
149 dsaf_dev->ppe_paddr = res->start;
150
151 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
152 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
153 "dsaf-base");
154 if (!res) {
155 res = platform_get_resource(pdev, IORESOURCE_MEM,
156 res_idx);
157 if (!res) {
158 dev_err(dsaf_dev->dev,
159 "dsaf-base info is needed!\n");
160 return -ENOMEM;
161 }
162 }
163 dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res);
164 if (IS_ERR(dsaf_dev->io_base))
165 return PTR_ERR(dsaf_dev->io_base);
166 }
167
168 ret = device_property_read_u32(dsaf_dev->dev, "desc-num", &desc_num);
169 if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT ||
170 desc_num > HNS_DSAF_MAX_DESC_CNT) {
171 dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n",
172 desc_num, ret);
173 return -EINVAL;
174 }
175 dsaf_dev->desc_num = desc_num;
176
177 ret = device_property_read_u32(dsaf_dev->dev, "reset-field-offset",
178 &reset_offset);
179 if (ret < 0) {
180 dev_dbg(dsaf_dev->dev,
181 "get reset-field-offset fail, ret=%d!\r\n", ret);
182 }
183 dsaf_dev->reset_offset = reset_offset;
184
185 ret = device_property_read_u32(dsaf_dev->dev, "buf-size", &buf_size);
186 if (ret < 0) {
187 dev_err(dsaf_dev->dev,
188 "get buf-size fail, ret=%d!\r\n", ret);
189 return ret;
190 }
191 dsaf_dev->buf_size = buf_size;
192
193 dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size);
194 if (dsaf_dev->buf_size_type < 0) {
195 dev_err(dsaf_dev->dev,
196 "buf_size(%d) is wrong!\n", buf_size);
197 return -EINVAL;
198 }
199
200 dsaf_dev->misc_op = hns_misc_op_get(dsaf_dev);
201 if (!dsaf_dev->misc_op)
202 return -ENOMEM;
203
204 if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL)))
205 dev_dbg(dsaf_dev->dev, "set mask to 64bit\n");
206 else
207 dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n");
208
209 return 0;
210 }
211
212 /**
213 * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en
214 * @dsaf_id: dsa fabric id
215 */
216 static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev)
217 {
218 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1);
219 }
220
221 /**
222 * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce
223 * @dsaf_id: dsa fabric id
224 * @hns_dsaf_reg_cnt_clr_ce: config value
225 */
226 static void
227 hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce)
228 {
229 dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG,
230 DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce);
231 }
232
233 /**
234 * hns_ppe_qid_cfg - config ppe qid
235 * @dsaf_id: dsa fabric id
236 * @pppe_qid_cfg: value array
237 */
238 static void
239 hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg)
240 {
241 u32 i;
242
243 for (i = 0; i < DSAF_COMM_CHN; i++) {
244 dsaf_set_dev_field(dsaf_dev,
245 DSAF_PPE_QID_CFG_0_REG + 0x0004 * i,
246 DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S,
247 qid_cfg);
248 }
249 }
250
251 static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev)
252 {
253 u16 max_q_per_vf, max_vfn;
254 u32 q_id, q_num_per_port;
255 u32 i;
256
257 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
258 q_num_per_port = max_vfn * max_q_per_vf;
259
260 for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) {
261 dsaf_set_dev_field(dsaf_dev,
262 DSAF_MIX_DEF_QID_0_REG + 0x0004 * i,
263 0xff, 0, q_id);
264 q_id += q_num_per_port;
265 }
266 }
267
268 static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev)
269 {
270 u16 max_q_per_vf, max_vfn;
271 u32 q_id, q_num_per_port;
272 u32 mac_id;
273
274 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
275 return;
276
277 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
278 q_num_per_port = max_vfn * max_q_per_vf;
279
280 for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) {
281 dsaf_set_dev_field(dsaf_dev,
282 DSAFV2_SERDES_LBK_0_REG + 4 * mac_id,
283 DSAFV2_SERDES_LBK_QID_M,
284 DSAFV2_SERDES_LBK_QID_S,
285 q_id);
286 q_id += q_num_per_port;
287 }
288 }
289
290 /**
291 * hns_dsaf_sw_port_type_cfg - cfg sw type
292 * @dsaf_id: dsa fabric id
293 * @psw_port_type: array
294 */
295 static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev,
296 enum dsaf_sw_port_type port_type)
297 {
298 u32 i;
299
300 for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
301 dsaf_set_dev_field(dsaf_dev,
302 DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i,
303 DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S,
304 port_type);
305 }
306 }
307
308 /**
309 * hns_dsaf_stp_port_type_cfg - cfg stp type
310 * @dsaf_id: dsa fabric id
311 * @pstp_port_type: array
312 */
313 static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev,
314 enum dsaf_stp_port_type port_type)
315 {
316 u32 i;
317
318 for (i = 0; i < DSAF_COMM_CHN; i++) {
319 dsaf_set_dev_field(dsaf_dev,
320 DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i,
321 DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S,
322 port_type);
323 }
324 }
325
326 #define HNS_DSAF_SBM_NUM(dev) \
327 (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM)
328 /**
329 * hns_dsaf_sbm_cfg - config sbm
330 * @dsaf_id: dsa fabric id
331 */
332 static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev)
333 {
334 u32 o_sbm_cfg;
335 u32 i;
336
337 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
338 o_sbm_cfg = dsaf_read_dev(dsaf_dev,
339 DSAF_SBM_CFG_REG_0_REG + 0x80 * i);
340 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1);
341 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0);
342 dsaf_write_dev(dsaf_dev,
343 DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg);
344 }
345 }
346
347 /**
348 * hns_dsaf_sbm_cfg_mib_en - config sbm
349 * @dsaf_id: dsa fabric id
350 */
351 static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev)
352 {
353 u32 sbm_cfg_mib_en;
354 u32 i;
355 u32 reg;
356 u32 read_cnt;
357
358 /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */
359 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
360 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
361 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0);
362 }
363
364 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
365 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
366 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1);
367 }
368
369 /* waitint for all sbm enable finished */
370 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
371 read_cnt = 0;
372 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
373 do {
374 udelay(1);
375 sbm_cfg_mib_en = dsaf_get_dev_bit(
376 dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S);
377 read_cnt++;
378 } while (sbm_cfg_mib_en == 0 &&
379 read_cnt < DSAF_CFG_READ_CNT);
380
381 if (sbm_cfg_mib_en == 0) {
382 dev_err(dsaf_dev->dev,
383 "sbm_cfg_mib_en fail,%s,sbm_num=%d\n",
384 dsaf_dev->ae_dev.name, i);
385 return -ENODEV;
386 }
387 }
388
389 return 0;
390 }
391
392 /**
393 * hns_dsaf_sbm_bp_wl_cfg - config sbm
394 * @dsaf_id: dsa fabric id
395 */
396 static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
397 {
398 u32 o_sbm_bp_cfg;
399 u32 reg;
400 u32 i;
401
402 /* XGE */
403 for (i = 0; i < DSAF_XGE_NUM; i++) {
404 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
405 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
406 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M,
407 DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512);
408 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M,
409 DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
410 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M,
411 DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
412 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
413
414 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
415 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
416 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M,
417 DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
418 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M,
419 DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
420 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
421
422 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
423 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
424 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
425 DSAF_SBM_CFG2_SET_BUF_NUM_S, 104);
426 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
427 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128);
428 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
429
430 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
431 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
432 dsaf_set_field(o_sbm_bp_cfg,
433 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
434 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110);
435 dsaf_set_field(o_sbm_bp_cfg,
436 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
437 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160);
438 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
439
440 /* for no enable pfc mode */
441 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
442 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
443 dsaf_set_field(o_sbm_bp_cfg,
444 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
445 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128);
446 dsaf_set_field(o_sbm_bp_cfg,
447 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
448 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192);
449 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
450 }
451
452 /* PPE */
453 for (i = 0; i < DSAF_COMM_CHN; i++) {
454 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
455 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
456 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
457 DSAF_SBM_CFG2_SET_BUF_NUM_S, 10);
458 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
459 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12);
460 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
461 }
462
463 /* RoCEE */
464 for (i = 0; i < DSAF_COMM_CHN; i++) {
465 reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
466 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
467 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
468 DSAF_SBM_CFG2_SET_BUF_NUM_S, 2);
469 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
470 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4);
471 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
472 }
473 }
474
475 static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
476 {
477 u32 o_sbm_bp_cfg;
478 u32 reg;
479 u32 i;
480
481 /* XGE */
482 for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) {
483 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
484 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
485 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M,
486 DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256);
487 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M,
488 DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
489 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M,
490 DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
491 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
492
493 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
494 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
495 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M,
496 DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
497 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M,
498 DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
499 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
500
501 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
502 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
503 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M,
504 DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104);
505 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M,
506 DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128);
507 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
508
509 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
510 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
511 dsaf_set_field(o_sbm_bp_cfg,
512 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
513 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 55);
514 dsaf_set_field(o_sbm_bp_cfg,
515 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
516 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 110);
517 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
518
519 /* for no enable pfc mode */
520 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
521 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
522 dsaf_set_field(o_sbm_bp_cfg,
523 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M,
524 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 128);
525 dsaf_set_field(o_sbm_bp_cfg,
526 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M,
527 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 192);
528 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
529 }
530
531 /* PPE */
532 for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) {
533 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
534 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
535 dsaf_set_field(o_sbm_bp_cfg,
536 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M,
537 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S, 2);
538 dsaf_set_field(o_sbm_bp_cfg,
539 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M,
540 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S, 3);
541 dsaf_set_field(o_sbm_bp_cfg,
542 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M,
543 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S, 52);
544 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
545 }
546
547 /* RoCEE */
548 for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) {
549 reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
550 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
551 dsaf_set_field(o_sbm_bp_cfg,
552 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M,
553 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S, 2);
554 dsaf_set_field(o_sbm_bp_cfg,
555 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M,
556 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S, 4);
557 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
558 }
559 }
560
561 /**
562 * hns_dsaf_voq_bp_all_thrd_cfg - voq
563 * @dsaf_id: dsa fabric id
564 */
565 static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev)
566 {
567 u32 voq_bp_all_thrd;
568 u32 i;
569
570 for (i = 0; i < DSAF_VOQ_NUM; i++) {
571 voq_bp_all_thrd = dsaf_read_dev(
572 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i);
573 if (i < DSAF_XGE_NUM) {
574 dsaf_set_field(voq_bp_all_thrd,
575 DSAF_VOQ_BP_ALL_DOWNTHRD_M,
576 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930);
577 dsaf_set_field(voq_bp_all_thrd,
578 DSAF_VOQ_BP_ALL_UPTHRD_M,
579 DSAF_VOQ_BP_ALL_UPTHRD_S, 950);
580 } else {
581 dsaf_set_field(voq_bp_all_thrd,
582 DSAF_VOQ_BP_ALL_DOWNTHRD_M,
583 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220);
584 dsaf_set_field(voq_bp_all_thrd,
585 DSAF_VOQ_BP_ALL_UPTHRD_M,
586 DSAF_VOQ_BP_ALL_UPTHRD_S, 230);
587 }
588 dsaf_write_dev(
589 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i,
590 voq_bp_all_thrd);
591 }
592 }
593
594 static void hns_dsaf_tbl_tcam_match_cfg(
595 struct dsaf_device *dsaf_dev,
596 struct dsaf_tbl_tcam_data *ptbl_tcam_data)
597 {
598 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_L_REG,
599 ptbl_tcam_data->tbl_tcam_data_low);
600 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_H_REG,
601 ptbl_tcam_data->tbl_tcam_data_high);
602 }
603
604 /**
605 * hns_dsaf_tbl_tcam_data_cfg - tbl
606 * @dsaf_id: dsa fabric id
607 * @ptbl_tcam_data: addr
608 */
609 static void hns_dsaf_tbl_tcam_data_cfg(
610 struct dsaf_device *dsaf_dev,
611 struct dsaf_tbl_tcam_data *ptbl_tcam_data)
612 {
613 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG,
614 ptbl_tcam_data->tbl_tcam_data_low);
615 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG,
616 ptbl_tcam_data->tbl_tcam_data_high);
617 }
618
619 /**
620 * dsaf_tbl_tcam_mcast_cfg - tbl
621 * @dsaf_id: dsa fabric id
622 * @ptbl_tcam_mcast: addr
623 */
624 static void hns_dsaf_tbl_tcam_mcast_cfg(
625 struct dsaf_device *dsaf_dev,
626 struct dsaf_tbl_tcam_mcast_cfg *mcast)
627 {
628 u32 mcast_cfg4;
629
630 mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
631 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S,
632 mcast->tbl_mcast_item_vld);
633 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S,
634 mcast->tbl_mcast_old_en);
635 dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M,
636 DSAF_TBL_MCAST_CFG4_VM128_112_S,
637 mcast->tbl_mcast_port_msk[4]);
638 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4);
639
640 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG,
641 mcast->tbl_mcast_port_msk[3]);
642
643 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG,
644 mcast->tbl_mcast_port_msk[2]);
645
646 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG,
647 mcast->tbl_mcast_port_msk[1]);
648
649 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG,
650 mcast->tbl_mcast_port_msk[0]);
651 }
652
653 /**
654 * hns_dsaf_tbl_tcam_ucast_cfg - tbl
655 * @dsaf_id: dsa fabric id
656 * @ptbl_tcam_ucast: addr
657 */
658 static void hns_dsaf_tbl_tcam_ucast_cfg(
659 struct dsaf_device *dsaf_dev,
660 struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast)
661 {
662 u32 ucast_cfg1;
663
664 ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
665 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S,
666 tbl_tcam_ucast->tbl_ucast_mac_discard);
667 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S,
668 tbl_tcam_ucast->tbl_ucast_item_vld);
669 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S,
670 tbl_tcam_ucast->tbl_ucast_old_en);
671 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S,
672 tbl_tcam_ucast->tbl_ucast_dvc);
673 dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
674 DSAF_TBL_UCAST_CFG1_OUT_PORT_S,
675 tbl_tcam_ucast->tbl_ucast_out_port);
676 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1);
677 }
678
679 /**
680 * hns_dsaf_tbl_line_cfg - tbl
681 * @dsaf_id: dsa fabric id
682 * @ptbl_lin: addr
683 */
684 static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev,
685 struct dsaf_tbl_line_cfg *tbl_lin)
686 {
687 u32 tbl_line;
688
689 tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG);
690 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S,
691 tbl_lin->tbl_line_mac_discard);
692 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S,
693 tbl_lin->tbl_line_dvc);
694 dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M,
695 DSAF_TBL_LINE_CFG_OUT_PORT_S,
696 tbl_lin->tbl_line_out_port);
697 dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line);
698 }
699
700 /**
701 * hns_dsaf_tbl_tcam_mcast_pul - tbl
702 * @dsaf_id: dsa fabric id
703 */
704 static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev)
705 {
706 u32 o_tbl_pul;
707
708 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
709 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
710 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
711 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
712 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
713 }
714
715 /**
716 * hns_dsaf_tbl_line_pul - tbl
717 * @dsaf_id: dsa fabric id
718 */
719 static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev)
720 {
721 u32 tbl_pul;
722
723 tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
724 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1);
725 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
726 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0);
727 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
728 }
729
730 /**
731 * hns_dsaf_tbl_tcam_data_mcast_pul - tbl
732 * @dsaf_id: dsa fabric id
733 */
734 static void hns_dsaf_tbl_tcam_data_mcast_pul(
735 struct dsaf_device *dsaf_dev)
736 {
737 u32 o_tbl_pul;
738
739 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
740 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
741 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
742 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
743 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
744 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
745 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
746 }
747
748 /**
749 * hns_dsaf_tbl_tcam_data_ucast_pul - tbl
750 * @dsaf_id: dsa fabric id
751 */
752 static void hns_dsaf_tbl_tcam_data_ucast_pul(
753 struct dsaf_device *dsaf_dev)
754 {
755 u32 o_tbl_pul;
756
757 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
758 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
759 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1);
760 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
761 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
762 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0);
763 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
764 }
765
766 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en)
767 {
768 if (AE_IS_VER1(dsaf_dev->dsaf_ver) && !HNS_DSAF_IS_DEBUG(dsaf_dev))
769 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG,
770 DSAF_CFG_MIX_MODE_S, !!en);
771 }
772
773 /**
774 * hns_dsaf_tbl_stat_en - tbl
775 * @dsaf_id: dsa fabric id
776 * @ptbl_stat_en: addr
777 */
778 static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev)
779 {
780 u32 o_tbl_ctrl;
781
782 o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG);
783 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1);
784 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1);
785 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1);
786 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1);
787 dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl);
788 }
789
790 /**
791 * hns_dsaf_rocee_bp_en - rocee back press enable
792 * @dsaf_id: dsa fabric id
793 */
794 static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev)
795 {
796 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
797 dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG,
798 DSAF_FC_XGE_TX_PAUSE_S, 1);
799 }
800
801 /* set msk for dsaf exception irq*/
802 static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev,
803 u32 chnn_num, u32 mask_set)
804 {
805 dsaf_write_dev(dsaf_dev,
806 DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set);
807 }
808
809 static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev,
810 u32 chnn_num, u32 msk_set)
811 {
812 dsaf_write_dev(dsaf_dev,
813 DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set);
814 }
815
816 static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev,
817 u32 chnn, u32 msk_set)
818 {
819 dsaf_write_dev(dsaf_dev,
820 DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set);
821 }
822
823 static void
824 hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set)
825 {
826 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set);
827 }
828
829 /* clr dsaf exception irq*/
830 static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev,
831 u32 chnn_num, u32 int_src)
832 {
833 dsaf_write_dev(dsaf_dev,
834 DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src);
835 }
836
837 static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev,
838 u32 chnn, u32 int_src)
839 {
840 dsaf_write_dev(dsaf_dev,
841 DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src);
842 }
843
844 static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev,
845 u32 chnn, u32 int_src)
846 {
847 dsaf_write_dev(dsaf_dev,
848 DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src);
849 }
850
851 static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev,
852 u32 int_src)
853 {
854 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src);
855 }
856
857 /**
858 * hns_dsaf_single_line_tbl_cfg - INT
859 * @dsaf_id: dsa fabric id
860 * @address:
861 * @ptbl_line:
862 */
863 static void hns_dsaf_single_line_tbl_cfg(
864 struct dsaf_device *dsaf_dev,
865 u32 address, struct dsaf_tbl_line_cfg *ptbl_line)
866 {
867 spin_lock_bh(&dsaf_dev->tcam_lock);
868
869 /*Write Addr*/
870 hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address);
871
872 /*Write Line*/
873 hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line);
874
875 /*Write Plus*/
876 hns_dsaf_tbl_line_pul(dsaf_dev);
877
878 spin_unlock_bh(&dsaf_dev->tcam_lock);
879 }
880
881 /**
882 * hns_dsaf_tcam_uc_cfg - INT
883 * @dsaf_id: dsa fabric id
884 * @address,
885 * @ptbl_tcam_data,
886 */
887 static void hns_dsaf_tcam_uc_cfg(
888 struct dsaf_device *dsaf_dev, u32 address,
889 struct dsaf_tbl_tcam_data *ptbl_tcam_data,
890 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
891 {
892 spin_lock_bh(&dsaf_dev->tcam_lock);
893
894 /*Write Addr*/
895 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
896 /*Write Tcam Data*/
897 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
898 /*Write Tcam Ucast*/
899 hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast);
900 /*Write Plus*/
901 hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
902
903 spin_unlock_bh(&dsaf_dev->tcam_lock);
904 }
905
906 /**
907 * hns_dsaf_tcam_mc_cfg - cfg the tcam for mc
908 * @dsaf_dev: dsa fabric device struct pointer
909 * @address: tcam index
910 * @ptbl_tcam_data: tcam data struct pointer
911 * @ptbl_tcam_mcast: tcam mask struct pointer, it must be null for HNSv1
912 */
913 static void hns_dsaf_tcam_mc_cfg(
914 struct dsaf_device *dsaf_dev, u32 address,
915 struct dsaf_tbl_tcam_data *ptbl_tcam_data,
916 struct dsaf_tbl_tcam_data *ptbl_tcam_mask,
917 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
918 {
919 spin_lock_bh(&dsaf_dev->tcam_lock);
920
921 /*Write Addr*/
922 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
923 /*Write Tcam Data*/
924 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
925 /*Write Tcam Mcast*/
926 hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast);
927 /* Write Match Data */
928 if (ptbl_tcam_mask)
929 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, ptbl_tcam_mask);
930
931 /* Write Puls */
932 hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
933
934 spin_unlock_bh(&dsaf_dev->tcam_lock);
935 }
936
937 /**
938 * hns_dsaf_tcam_mc_invld - INT
939 * @dsaf_id: dsa fabric id
940 * @address
941 */
942 static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address)
943 {
944 spin_lock_bh(&dsaf_dev->tcam_lock);
945
946 /*Write Addr*/
947 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
948
949 /*write tcam mcast*/
950 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0);
951 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0);
952 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0);
953 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0);
954 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0);
955
956 /*Write Plus*/
957 hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev);
958
959 spin_unlock_bh(&dsaf_dev->tcam_lock);
960 }
961
962 void hns_dsaf_tcam_addr_get(struct dsaf_drv_tbl_tcam_key *mac_key, u8 *addr)
963 {
964 addr[0] = mac_key->high.bits.mac_0;
965 addr[1] = mac_key->high.bits.mac_1;
966 addr[2] = mac_key->high.bits.mac_2;
967 addr[3] = mac_key->high.bits.mac_3;
968 addr[4] = mac_key->low.bits.mac_4;
969 addr[5] = mac_key->low.bits.mac_5;
970 }
971
972 /**
973 * hns_dsaf_tcam_uc_get - INT
974 * @dsaf_id: dsa fabric id
975 * @address
976 * @ptbl_tcam_data
977 * @ptbl_tcam_ucast
978 */
979 static void hns_dsaf_tcam_uc_get(
980 struct dsaf_device *dsaf_dev, u32 address,
981 struct dsaf_tbl_tcam_data *ptbl_tcam_data,
982 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
983 {
984 u32 tcam_read_data0;
985 u32 tcam_read_data4;
986
987 spin_lock_bh(&dsaf_dev->tcam_lock);
988
989 /*Write Addr*/
990 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
991
992 /*read tcam item puls*/
993 hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
994
995 /*read tcam data*/
996 ptbl_tcam_data->tbl_tcam_data_high
997 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
998 ptbl_tcam_data->tbl_tcam_data_low
999 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1000
1001 /*read tcam mcast*/
1002 tcam_read_data0 = dsaf_read_dev(dsaf_dev,
1003 DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1004 tcam_read_data4 = dsaf_read_dev(dsaf_dev,
1005 DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1006
1007 ptbl_tcam_ucast->tbl_ucast_item_vld
1008 = dsaf_get_bit(tcam_read_data4,
1009 DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1010 ptbl_tcam_ucast->tbl_ucast_old_en
1011 = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1012 ptbl_tcam_ucast->tbl_ucast_mac_discard
1013 = dsaf_get_bit(tcam_read_data0,
1014 DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S);
1015 ptbl_tcam_ucast->tbl_ucast_out_port
1016 = dsaf_get_field(tcam_read_data0,
1017 DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
1018 DSAF_TBL_UCAST_CFG1_OUT_PORT_S);
1019 ptbl_tcam_ucast->tbl_ucast_dvc
1020 = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S);
1021
1022 spin_unlock_bh(&dsaf_dev->tcam_lock);
1023 }
1024
1025 /**
1026 * hns_dsaf_tcam_mc_get - INT
1027 * @dsaf_id: dsa fabric id
1028 * @address
1029 * @ptbl_tcam_data
1030 * @ptbl_tcam_ucast
1031 */
1032 static void hns_dsaf_tcam_mc_get(
1033 struct dsaf_device *dsaf_dev, u32 address,
1034 struct dsaf_tbl_tcam_data *ptbl_tcam_data,
1035 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
1036 {
1037 u32 data_tmp;
1038
1039 spin_lock_bh(&dsaf_dev->tcam_lock);
1040
1041 /*Write Addr*/
1042 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1043
1044 /*read tcam item puls*/
1045 hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
1046
1047 /*read tcam data*/
1048 ptbl_tcam_data->tbl_tcam_data_high =
1049 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
1050 ptbl_tcam_data->tbl_tcam_data_low =
1051 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1052
1053 /*read tcam mcast*/
1054 ptbl_tcam_mcast->tbl_mcast_port_msk[0] =
1055 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1056 ptbl_tcam_mcast->tbl_mcast_port_msk[1] =
1057 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
1058 ptbl_tcam_mcast->tbl_mcast_port_msk[2] =
1059 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
1060 ptbl_tcam_mcast->tbl_mcast_port_msk[3] =
1061 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
1062
1063 data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1064 ptbl_tcam_mcast->tbl_mcast_item_vld =
1065 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1066 ptbl_tcam_mcast->tbl_mcast_old_en =
1067 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1068 ptbl_tcam_mcast->tbl_mcast_port_msk[4] =
1069 dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M,
1070 DSAF_TBL_MCAST_CFG4_VM128_112_S);
1071
1072 spin_unlock_bh(&dsaf_dev->tcam_lock);
1073 }
1074
1075 /**
1076 * hns_dsaf_tbl_line_init - INT
1077 * @dsaf_id: dsa fabric id
1078 */
1079 static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev)
1080 {
1081 u32 i;
1082 /* defaultly set all lineal mac table entry resulting discard */
1083 struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} };
1084
1085 for (i = 0; i < DSAF_LINE_SUM; i++)
1086 hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line);
1087 }
1088
1089 /**
1090 * hns_dsaf_tbl_tcam_init - INT
1091 * @dsaf_id: dsa fabric id
1092 */
1093 static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev)
1094 {
1095 u32 i;
1096 struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} };
1097 struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} };
1098
1099 /*tcam tbl*/
1100 for (i = 0; i < DSAF_TCAM_SUM; i++)
1101 hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast);
1102 }
1103
1104 /**
1105 * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg
1106 * @mac_cb: mac contrl block
1107 */
1108 static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev,
1109 int mac_id, int tc_en)
1110 {
1111 dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en);
1112 }
1113
1114 static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev,
1115 int mac_id, int tx_en, int rx_en)
1116 {
1117 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1118 if (!tx_en || !rx_en)
1119 dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n");
1120
1121 return;
1122 }
1123
1124 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1125 DSAF_PFC_PAUSE_RX_EN_B, !!rx_en);
1126 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1127 DSAF_PFC_PAUSE_TX_EN_B, !!tx_en);
1128 }
1129
1130 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1131 u32 en)
1132 {
1133 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1134 if (!en) {
1135 dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n");
1136 return -EINVAL;
1137 }
1138 }
1139
1140 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1141 DSAF_MAC_PAUSE_RX_EN_B, !!en);
1142
1143 return 0;
1144 }
1145
1146 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1147 u32 *en)
1148 {
1149 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1150 *en = 1;
1151 else
1152 *en = dsaf_get_dev_bit(dsaf_dev,
1153 DSAF_PAUSE_CFG_REG + mac_id * 4,
1154 DSAF_MAC_PAUSE_RX_EN_B);
1155 }
1156
1157 /**
1158 * hns_dsaf_tbl_tcam_init - INT
1159 * @dsaf_id: dsa fabric id
1160 * @dsaf_mode
1161 */
1162 static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev)
1163 {
1164 u32 i;
1165 u32 o_dsaf_cfg;
1166 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
1167
1168 o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG);
1169 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en);
1170 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode);
1171 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0);
1172 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0);
1173 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0);
1174 dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg);
1175
1176 hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1);
1177 hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD);
1178
1179 /* set 22 queue per tx ppe engine, only used in switch mode */
1180 hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE);
1181
1182 /* set promisc def queue id */
1183 hns_dsaf_mix_def_qid_cfg(dsaf_dev);
1184
1185 /* set inner loopback queue id */
1186 hns_dsaf_inner_qid_cfg(dsaf_dev);
1187
1188 /* in non switch mode, set all port to access mode */
1189 hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN);
1190
1191 /*set dsaf pfc to 0 for parseing rx pause*/
1192 for (i = 0; i < DSAF_COMM_CHN; i++) {
1193 hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0);
1194 hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1);
1195 }
1196
1197 /*msk and clr exception irqs */
1198 for (i = 0; i < DSAF_COMM_CHN; i++) {
1199 hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful);
1200 hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful);
1201 hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful);
1202
1203 hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful);
1204 hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful);
1205 hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful);
1206 }
1207 hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful);
1208 hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful);
1209 }
1210
1211 /**
1212 * hns_dsaf_inode_init - INT
1213 * @dsaf_id: dsa fabric id
1214 */
1215 static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev)
1216 {
1217 u32 reg;
1218 u32 tc_cfg;
1219 u32 i;
1220
1221 if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE)
1222 tc_cfg = HNS_DSAF_I4TC_CFG;
1223 else
1224 tc_cfg = HNS_DSAF_I8TC_CFG;
1225
1226 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1227 for (i = 0; i < DSAF_INODE_NUM; i++) {
1228 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1229 dsaf_set_dev_field(dsaf_dev, reg,
1230 DSAF_INODE_IN_PORT_NUM_M,
1231 DSAF_INODE_IN_PORT_NUM_S,
1232 i % DSAF_XGE_NUM);
1233 }
1234 } else {
1235 for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) {
1236 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1237 dsaf_set_dev_field(dsaf_dev, reg,
1238 DSAF_INODE_IN_PORT_NUM_M,
1239 DSAF_INODE_IN_PORT_NUM_S, 0);
1240 dsaf_set_dev_field(dsaf_dev, reg,
1241 DSAFV2_INODE_IN_PORT1_NUM_M,
1242 DSAFV2_INODE_IN_PORT1_NUM_S, 1);
1243 dsaf_set_dev_field(dsaf_dev, reg,
1244 DSAFV2_INODE_IN_PORT2_NUM_M,
1245 DSAFV2_INODE_IN_PORT2_NUM_S, 2);
1246 dsaf_set_dev_field(dsaf_dev, reg,
1247 DSAFV2_INODE_IN_PORT3_NUM_M,
1248 DSAFV2_INODE_IN_PORT3_NUM_S, 3);
1249 dsaf_set_dev_field(dsaf_dev, reg,
1250 DSAFV2_INODE_IN_PORT4_NUM_M,
1251 DSAFV2_INODE_IN_PORT4_NUM_S, 4);
1252 dsaf_set_dev_field(dsaf_dev, reg,
1253 DSAFV2_INODE_IN_PORT5_NUM_M,
1254 DSAFV2_INODE_IN_PORT5_NUM_S, 5);
1255 }
1256 }
1257 for (i = 0; i < DSAF_INODE_NUM; i++) {
1258 reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i;
1259 dsaf_write_dev(dsaf_dev, reg, tc_cfg);
1260 }
1261 }
1262
1263 /**
1264 * hns_dsaf_sbm_init - INT
1265 * @dsaf_id: dsa fabric id
1266 */
1267 static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev)
1268 {
1269 u32 flag;
1270 u32 finish_msk;
1271 u32 cnt = 0;
1272 int ret;
1273
1274 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1275 hns_dsaf_sbm_bp_wl_cfg(dsaf_dev);
1276 finish_msk = DSAF_SRAM_INIT_OVER_M;
1277 } else {
1278 hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev);
1279 finish_msk = DSAFV2_SRAM_INIT_OVER_M;
1280 }
1281
1282 /* enable sbm chanel, disable sbm chanel shcut function*/
1283 hns_dsaf_sbm_cfg(dsaf_dev);
1284
1285 /* enable sbm mib */
1286 ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev);
1287 if (ret) {
1288 dev_err(dsaf_dev->dev,
1289 "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n",
1290 dsaf_dev->ae_dev.name, ret);
1291 return ret;
1292 }
1293
1294 /* enable sbm initial link sram */
1295 hns_dsaf_sbm_link_sram_init_en(dsaf_dev);
1296
1297 do {
1298 usleep_range(200, 210);/*udelay(200);*/
1299 flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG,
1300 finish_msk, DSAF_SRAM_INIT_OVER_S);
1301 cnt++;
1302 } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) &&
1303 cnt < DSAF_CFG_READ_CNT);
1304
1305 if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) {
1306 dev_err(dsaf_dev->dev,
1307 "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n",
1308 dsaf_dev->ae_dev.name, flag, cnt);
1309 return -ENODEV;
1310 }
1311
1312 hns_dsaf_rocee_bp_en(dsaf_dev);
1313
1314 return 0;
1315 }
1316
1317 /**
1318 * hns_dsaf_tbl_init - INT
1319 * @dsaf_id: dsa fabric id
1320 */
1321 static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev)
1322 {
1323 hns_dsaf_tbl_stat_en(dsaf_dev);
1324
1325 hns_dsaf_tbl_tcam_init(dsaf_dev);
1326 hns_dsaf_tbl_line_init(dsaf_dev);
1327 }
1328
1329 /**
1330 * hns_dsaf_voq_init - INT
1331 * @dsaf_id: dsa fabric id
1332 */
1333 static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev)
1334 {
1335 hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev);
1336 }
1337
1338 /**
1339 * hns_dsaf_init_hw - init dsa fabric hardware
1340 * @dsaf_dev: dsa fabric device struct pointer
1341 */
1342 static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev)
1343 {
1344 int ret;
1345
1346 dev_dbg(dsaf_dev->dev,
1347 "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name);
1348
1349 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1350 mdelay(10);
1351 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 1);
1352
1353 hns_dsaf_comm_init(dsaf_dev);
1354
1355 /*init XBAR_INODE*/
1356 hns_dsaf_inode_init(dsaf_dev);
1357
1358 /*init SBM*/
1359 ret = hns_dsaf_sbm_init(dsaf_dev);
1360 if (ret)
1361 return ret;
1362
1363 /*init TBL*/
1364 hns_dsaf_tbl_init(dsaf_dev);
1365
1366 /*init VOQ*/
1367 hns_dsaf_voq_init(dsaf_dev);
1368
1369 return 0;
1370 }
1371
1372 /**
1373 * hns_dsaf_remove_hw - uninit dsa fabric hardware
1374 * @dsaf_dev: dsa fabric device struct pointer
1375 */
1376 static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev)
1377 {
1378 /*reset*/
1379 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1380 }
1381
1382 /**
1383 * hns_dsaf_init - init dsa fabric
1384 * @dsaf_dev: dsa fabric device struct pointer
1385 * retuen 0 - success , negative --fail
1386 */
1387 static int hns_dsaf_init(struct dsaf_device *dsaf_dev)
1388 {
1389 struct dsaf_drv_priv *priv =
1390 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1391 u32 i;
1392 int ret;
1393
1394 if (HNS_DSAF_IS_DEBUG(dsaf_dev))
1395 return 0;
1396
1397 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1398 dsaf_dev->tcam_max_num = DSAF_TCAM_SUM;
1399 else
1400 dsaf_dev->tcam_max_num =
1401 DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM;
1402
1403 spin_lock_init(&dsaf_dev->tcam_lock);
1404 ret = hns_dsaf_init_hw(dsaf_dev);
1405 if (ret)
1406 return ret;
1407
1408 /* malloc mem for tcam mac key(vlan+mac) */
1409 priv->soft_mac_tbl = vzalloc(sizeof(*priv->soft_mac_tbl)
1410 * DSAF_TCAM_SUM);
1411 if (!priv->soft_mac_tbl) {
1412 ret = -ENOMEM;
1413 goto remove_hw;
1414 }
1415
1416 /*all entry invall */
1417 for (i = 0; i < DSAF_TCAM_SUM; i++)
1418 (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX;
1419
1420 return 0;
1421
1422 remove_hw:
1423 hns_dsaf_remove_hw(dsaf_dev);
1424 return ret;
1425 }
1426
1427 /**
1428 * hns_dsaf_free - free dsa fabric
1429 * @dsaf_dev: dsa fabric device struct pointer
1430 */
1431 static void hns_dsaf_free(struct dsaf_device *dsaf_dev)
1432 {
1433 struct dsaf_drv_priv *priv =
1434 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1435
1436 hns_dsaf_remove_hw(dsaf_dev);
1437
1438 /* free all mac mem */
1439 vfree(priv->soft_mac_tbl);
1440 priv->soft_mac_tbl = NULL;
1441 }
1442
1443 /**
1444 * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry
1445 * @dsaf_dev: dsa fabric device struct pointer
1446 * @mac_key: mac entry struct pointer
1447 */
1448 static u16 hns_dsaf_find_soft_mac_entry(
1449 struct dsaf_device *dsaf_dev,
1450 struct dsaf_drv_tbl_tcam_key *mac_key)
1451 {
1452 struct dsaf_drv_priv *priv =
1453 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1454 struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1455 u32 i;
1456
1457 soft_mac_entry = priv->soft_mac_tbl;
1458 for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
1459 /* invall tab entry */
1460 if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) &&
1461 (soft_mac_entry->tcam_key.high.val == mac_key->high.val) &&
1462 (soft_mac_entry->tcam_key.low.val == mac_key->low.val))
1463 /* return find result --soft index */
1464 return soft_mac_entry->index;
1465
1466 soft_mac_entry++;
1467 }
1468 return DSAF_INVALID_ENTRY_IDX;
1469 }
1470
1471 /**
1472 * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry
1473 * @dsaf_dev: dsa fabric device struct pointer
1474 */
1475 static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev)
1476 {
1477 struct dsaf_drv_priv *priv =
1478 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1479 struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1480 u32 i;
1481
1482 soft_mac_entry = priv->soft_mac_tbl;
1483 for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
1484 /* inv all entry */
1485 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
1486 /* return find result --soft index */
1487 return i;
1488
1489 soft_mac_entry++;
1490 }
1491 return DSAF_INVALID_ENTRY_IDX;
1492 }
1493
1494 /**
1495 * hns_dsaf_set_mac_key - set mac key
1496 * @dsaf_dev: dsa fabric device struct pointer
1497 * @mac_key: tcam key pointer
1498 * @vlan_id: vlan id
1499 * @in_port_num: input port num
1500 * @addr: mac addr
1501 */
1502 static void hns_dsaf_set_mac_key(
1503 struct dsaf_device *dsaf_dev,
1504 struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num,
1505 u8 *addr)
1506 {
1507 u8 port;
1508
1509 if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE)
1510 /*DSAF mode : in port id fixed 0*/
1511 port = 0;
1512 else
1513 /*non-dsaf mode*/
1514 port = in_port_num;
1515
1516 mac_key->high.bits.mac_0 = addr[0];
1517 mac_key->high.bits.mac_1 = addr[1];
1518 mac_key->high.bits.mac_2 = addr[2];
1519 mac_key->high.bits.mac_3 = addr[3];
1520 mac_key->low.bits.mac_4 = addr[4];
1521 mac_key->low.bits.mac_5 = addr[5];
1522 mac_key->low.bits.port_vlan = 0;
1523 dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_VLAN_M,
1524 DSAF_TBL_TCAM_KEY_VLAN_S, vlan_id);
1525 dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_PORT_M,
1526 DSAF_TBL_TCAM_KEY_PORT_S, port);
1527
1528 mac_key->low.bits.port_vlan = le16_to_cpu(mac_key->low.bits.port_vlan);
1529 }
1530
1531 /**
1532 * hns_dsaf_set_mac_uc_entry - set mac uc-entry
1533 * @dsaf_dev: dsa fabric device struct pointer
1534 * @mac_entry: uc-mac entry
1535 */
1536 int hns_dsaf_set_mac_uc_entry(
1537 struct dsaf_device *dsaf_dev,
1538 struct dsaf_drv_mac_single_dest_entry *mac_entry)
1539 {
1540 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1541 struct dsaf_drv_tbl_tcam_key mac_key;
1542 struct dsaf_tbl_tcam_ucast_cfg mac_data;
1543 struct dsaf_drv_priv *priv =
1544 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1545 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1546 struct dsaf_tbl_tcam_data tcam_data;
1547
1548 /* mac addr check */
1549 if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1550 MAC_IS_BROADCAST(mac_entry->addr) ||
1551 MAC_IS_MULTICAST(mac_entry->addr)) {
1552 dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n",
1553 dsaf_dev->ae_dev.name, mac_entry->addr);
1554 return -EINVAL;
1555 }
1556
1557 /* config key */
1558 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1559 mac_entry->in_port_num, mac_entry->addr);
1560
1561 /* entry ie exist? */
1562 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1563 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1564 /*if has not inv entry,find a empty entry */
1565 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1566 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1567 /* has not empty,return error */
1568 dev_err(dsaf_dev->dev,
1569 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1570 dsaf_dev->ae_dev.name,
1571 mac_key.high.val, mac_key.low.val);
1572 return -EINVAL;
1573 }
1574 }
1575
1576 dev_dbg(dsaf_dev->dev,
1577 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1578 dsaf_dev->ae_dev.name, mac_key.high.val,
1579 mac_key.low.val, entry_index);
1580
1581 /* config hardware entry */
1582 mac_data.tbl_ucast_item_vld = 1;
1583 mac_data.tbl_ucast_mac_discard = 0;
1584 mac_data.tbl_ucast_old_en = 0;
1585 /* default config dvc to 0 */
1586 mac_data.tbl_ucast_dvc = 0;
1587 mac_data.tbl_ucast_out_port = mac_entry->port_num;
1588 tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val);
1589 tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val);
1590
1591 hns_dsaf_tcam_uc_cfg(dsaf_dev, entry_index, &tcam_data, &mac_data);
1592
1593 /* config software entry */
1594 soft_mac_entry += entry_index;
1595 soft_mac_entry->index = entry_index;
1596 soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1597 soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1598
1599 return 0;
1600 }
1601
1602 int hns_dsaf_rm_mac_addr(
1603 struct dsaf_device *dsaf_dev,
1604 struct dsaf_drv_mac_single_dest_entry *mac_entry)
1605 {
1606 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1607 struct dsaf_tbl_tcam_ucast_cfg mac_data;
1608 struct dsaf_drv_tbl_tcam_key mac_key;
1609
1610 /* mac addr check */
1611 if (!is_valid_ether_addr(mac_entry->addr)) {
1612 dev_err(dsaf_dev->dev, "rm_uc_addr %s Mac %pM err!\n",
1613 dsaf_dev->ae_dev.name, mac_entry->addr);
1614 return -EINVAL;
1615 }
1616
1617 /* config key */
1618 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1619 mac_entry->in_port_num, mac_entry->addr);
1620
1621 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1622 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1623 /* can not find the tcam entry, return 0 */
1624 dev_info(dsaf_dev->dev,
1625 "rm_uc_addr no tcam, %s Mac key(%#x:%#x)\n",
1626 dsaf_dev->ae_dev.name,
1627 mac_key.high.val, mac_key.low.val);
1628 return 0;
1629 }
1630
1631 dev_dbg(dsaf_dev->dev,
1632 "rm_uc_addr, %s Mac key(%#x:%#x) entry_index%d\n",
1633 dsaf_dev->ae_dev.name, mac_key.high.val,
1634 mac_key.low.val, entry_index);
1635
1636 hns_dsaf_tcam_uc_get(
1637 dsaf_dev, entry_index,
1638 (struct dsaf_tbl_tcam_data *)&mac_key,
1639 &mac_data);
1640
1641 /* unicast entry not used locally should not clear */
1642 if (mac_entry->port_num != mac_data.tbl_ucast_out_port)
1643 return -EFAULT;
1644
1645 return hns_dsaf_del_mac_entry(dsaf_dev,
1646 mac_entry->in_vlan_id,
1647 mac_entry->in_port_num,
1648 mac_entry->addr);
1649 }
1650
1651 static void hns_dsaf_mc_mask_bit_clear(char *dst, const char *src)
1652 {
1653 u16 *a = (u16 *)dst;
1654 const u16 *b = (const u16 *)src;
1655
1656 a[0] &= b[0];
1657 a[1] &= b[1];
1658 a[2] &= b[2];
1659 }
1660
1661 /**
1662 * hns_dsaf_add_mac_mc_port - add mac mc-port
1663 * @dsaf_dev: dsa fabric device struct pointer
1664 * @mac_entry: mc-mac entry
1665 */
1666 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
1667 struct dsaf_drv_mac_single_dest_entry *mac_entry)
1668 {
1669 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1670 struct dsaf_drv_tbl_tcam_key mac_key;
1671 struct dsaf_drv_tbl_tcam_key mask_key;
1672 struct dsaf_tbl_tcam_data *pmask_key = NULL;
1673 struct dsaf_tbl_tcam_mcast_cfg mac_data;
1674 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1675 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1676 struct dsaf_drv_tbl_tcam_key tmp_mac_key;
1677 struct dsaf_tbl_tcam_data tcam_data;
1678 u8 mc_addr[ETH_ALEN];
1679 u8 *mc_mask;
1680 int mskid;
1681
1682 /*chechk mac addr */
1683 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1684 dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n",
1685 mac_entry->addr);
1686 return -EINVAL;
1687 }
1688
1689 ether_addr_copy(mc_addr, mac_entry->addr);
1690 mc_mask = dsaf_dev->mac_cb[mac_entry->in_port_num]->mc_mask;
1691 if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1692 /* prepare for key data setting */
1693 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1694
1695 /* config key mask */
1696 hns_dsaf_set_mac_key(dsaf_dev, &mask_key,
1697 0x0,
1698 0xff,
1699 mc_mask);
1700
1701 mask_key.high.val = le32_to_cpu(mask_key.high.val);
1702 mask_key.low.val = le32_to_cpu(mask_key.low.val);
1703
1704 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1705 }
1706
1707 /*config key */
1708 hns_dsaf_set_mac_key(
1709 dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1710 mac_entry->in_port_num, mc_addr);
1711
1712 memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg));
1713
1714 /* check if the tcam is exist */
1715 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1716 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1717 /*if hasnot , find a empty*/
1718 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1719 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1720 /*if hasnot empty, error*/
1721 dev_err(dsaf_dev->dev,
1722 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1723 dsaf_dev->ae_dev.name, mac_key.high.val,
1724 mac_key.low.val);
1725 return -EINVAL;
1726 }
1727 } else {
1728 /* if exist, add in */
1729 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data,
1730 &mac_data);
1731
1732 tmp_mac_key.high.val =
1733 le32_to_cpu(tcam_data.tbl_tcam_data_high);
1734 tmp_mac_key.low.val = le32_to_cpu(tcam_data.tbl_tcam_data_low);
1735 }
1736
1737 /* config hardware entry */
1738 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1739 mskid = mac_entry->port_num;
1740 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1741 mskid = mac_entry->port_num -
1742 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1743 } else {
1744 dev_err(dsaf_dev->dev,
1745 "%s,pnum(%d)error,key(%#x:%#x)\n",
1746 dsaf_dev->ae_dev.name, mac_entry->port_num,
1747 mac_key.high.val, mac_key.low.val);
1748 return -EINVAL;
1749 }
1750 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1);
1751 mac_data.tbl_mcast_old_en = 0;
1752 mac_data.tbl_mcast_item_vld = 1;
1753
1754 dev_dbg(dsaf_dev->dev,
1755 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1756 dsaf_dev->ae_dev.name, mac_key.high.val,
1757 mac_key.low.val, entry_index);
1758
1759 tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val);
1760 tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val);
1761
1762 /* config mc entry with mask */
1763 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index, &tcam_data,
1764 pmask_key, &mac_data);
1765
1766 /*config software entry */
1767 soft_mac_entry += entry_index;
1768 soft_mac_entry->index = entry_index;
1769 soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1770 soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1771
1772 return 0;
1773 }
1774
1775 /**
1776 * hns_dsaf_del_mac_entry - del mac mc-port
1777 * @dsaf_dev: dsa fabric device struct pointer
1778 * @vlan_id: vlian id
1779 * @in_port_num: input port num
1780 * @addr : mac addr
1781 */
1782 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
1783 u8 in_port_num, u8 *addr)
1784 {
1785 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1786 struct dsaf_drv_tbl_tcam_key mac_key;
1787 struct dsaf_drv_priv *priv =
1788 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1789 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1790
1791 /*check mac addr */
1792 if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) {
1793 dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n",
1794 addr);
1795 return -EINVAL;
1796 }
1797
1798 /*config key */
1799 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr);
1800
1801 /*exist ?*/
1802 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1803 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1804 /*not exist, error */
1805 dev_err(dsaf_dev->dev,
1806 "del_mac_entry failed, %s Mac key(%#x:%#x)\n",
1807 dsaf_dev->ae_dev.name,
1808 mac_key.high.val, mac_key.low.val);
1809 return -EINVAL;
1810 }
1811 dev_dbg(dsaf_dev->dev,
1812 "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1813 dsaf_dev->ae_dev.name, mac_key.high.val,
1814 mac_key.low.val, entry_index);
1815
1816 /*do del opt*/
1817 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1818
1819 /*del soft emtry */
1820 soft_mac_entry += entry_index;
1821 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
1822
1823 return 0;
1824 }
1825
1826 /**
1827 * hns_dsaf_del_mac_mc_port - del mac mc- port
1828 * @dsaf_dev: dsa fabric device struct pointer
1829 * @mac_entry: mac entry
1830 */
1831 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
1832 struct dsaf_drv_mac_single_dest_entry *mac_entry)
1833 {
1834 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1835 struct dsaf_drv_tbl_tcam_key mac_key;
1836 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1837 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1838 u16 vlan_id;
1839 u8 in_port_num;
1840 struct dsaf_tbl_tcam_mcast_cfg mac_data;
1841 struct dsaf_tbl_tcam_data tcam_data;
1842 int mskid;
1843 const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0};
1844 struct dsaf_drv_tbl_tcam_key mask_key, tmp_mac_key;
1845 struct dsaf_tbl_tcam_data *pmask_key = NULL;
1846 u8 mc_addr[ETH_ALEN];
1847 u8 *mc_mask;
1848
1849 if (!(void *)mac_entry) {
1850 dev_err(dsaf_dev->dev,
1851 "hns_dsaf_del_mac_mc_port mac_entry is NULL\n");
1852 return -EINVAL;
1853 }
1854
1855 /*check mac addr */
1856 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1857 dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n",
1858 mac_entry->addr);
1859 return -EINVAL;
1860 }
1861
1862 /* always mask vlan_id field */
1863 ether_addr_copy(mc_addr, mac_entry->addr);
1864 mc_mask = dsaf_dev->mac_cb[mac_entry->in_port_num]->mc_mask;
1865
1866 if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1867 /* prepare for key data setting */
1868 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1869
1870 /* config key mask */
1871 hns_dsaf_set_mac_key(dsaf_dev, &mask_key, 0x00, 0xff, mc_addr);
1872
1873 mask_key.high.val = le32_to_cpu(mask_key.high.val);
1874 mask_key.low.val = le32_to_cpu(mask_key.low.val);
1875
1876 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1877 }
1878
1879 /* get key info */
1880 vlan_id = mac_entry->in_vlan_id;
1881 in_port_num = mac_entry->in_port_num;
1882
1883 /* config key */
1884 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, mc_addr);
1885
1886 /* check if the tcam entry is exist */
1887 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1888 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1889 /*find none */
1890 dev_err(dsaf_dev->dev,
1891 "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n",
1892 dsaf_dev->ae_dev.name,
1893 mac_key.high.val, mac_key.low.val);
1894 return -EINVAL;
1895 }
1896
1897 dev_dbg(dsaf_dev->dev,
1898 "del_mac_mc_port, %s key(%#x:%#x) index%d\n",
1899 dsaf_dev->ae_dev.name, mac_key.high.val,
1900 mac_key.low.val, entry_index);
1901
1902 /* read entry */
1903 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data, &mac_data);
1904
1905 tmp_mac_key.high.val = le32_to_cpu(tcam_data.tbl_tcam_data_high);
1906 tmp_mac_key.low.val = le32_to_cpu(tcam_data.tbl_tcam_data_low);
1907
1908 /*del the port*/
1909 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1910 mskid = mac_entry->port_num;
1911 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1912 mskid = mac_entry->port_num -
1913 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1914 } else {
1915 dev_err(dsaf_dev->dev,
1916 "%s,pnum(%d)error,key(%#x:%#x)\n",
1917 dsaf_dev->ae_dev.name, mac_entry->port_num,
1918 mac_key.high.val, mac_key.low.val);
1919 return -EINVAL;
1920 }
1921 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0);
1922
1923 /*check non port, do del entry */
1924 if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
1925 sizeof(mac_data.tbl_mcast_port_msk))) {
1926 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1927
1928 /* del soft entry */
1929 soft_mac_entry += entry_index;
1930 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
1931 } else { /* not zero, just del port, update */
1932 tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val);
1933 tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val);
1934
1935 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index,
1936 &tcam_data,
1937 pmask_key, &mac_data);
1938 }
1939
1940 return 0;
1941 }
1942
1943 int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev, u8 mac_id,
1944 u8 port_num)
1945 {
1946 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1947 struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1948 struct dsaf_tbl_tcam_mcast_cfg mac_data;
1949 int ret = 0, i;
1950
1951 if (HNS_DSAF_IS_DEBUG(dsaf_dev))
1952 return 0;
1953
1954 for (i = 0; i < DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM; i++) {
1955 u8 addr[ETH_ALEN];
1956 u8 port;
1957
1958 soft_mac_entry = priv->soft_mac_tbl + i;
1959
1960 hns_dsaf_tcam_addr_get(&soft_mac_entry->tcam_key, addr);
1961 port = dsaf_get_field(
1962 soft_mac_entry->tcam_key.low.bits.port_vlan,
1963 DSAF_TBL_TCAM_KEY_PORT_M,
1964 DSAF_TBL_TCAM_KEY_PORT_S);
1965 /* check valid tcam mc entry */
1966 if (soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX &&
1967 port == mac_id &&
1968 is_multicast_ether_addr(addr) &&
1969 !is_broadcast_ether_addr(addr)) {
1970 const u32 empty_msk[DSAF_PORT_MSK_NUM] = {0};
1971 struct dsaf_drv_mac_single_dest_entry mac_entry;
1972
1973 /* disable receiving of this multicast address for
1974 * the VF.
1975 */
1976 ether_addr_copy(mac_entry.addr, addr);
1977 mac_entry.in_vlan_id = dsaf_get_field(
1978 soft_mac_entry->tcam_key.low.bits.port_vlan,
1979 DSAF_TBL_TCAM_KEY_VLAN_M,
1980 DSAF_TBL_TCAM_KEY_VLAN_S);
1981 mac_entry.in_port_num = mac_id;
1982 mac_entry.port_num = port_num;
1983 if (hns_dsaf_del_mac_mc_port(dsaf_dev, &mac_entry)) {
1984 ret = -EINVAL;
1985 continue;
1986 }
1987
1988 /* disable receiving of this multicast address for
1989 * the mac port if all VF are disable
1990 */
1991 hns_dsaf_tcam_mc_get(dsaf_dev, i,
1992 (struct dsaf_tbl_tcam_data *)
1993 (&soft_mac_entry->tcam_key),
1994 &mac_data);
1995 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mac_id / 32],
1996 mac_id % 32, 0);
1997 if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
1998 sizeof(u32) * DSAF_PORT_MSK_NUM)) {
1999 mac_entry.port_num = mac_id;
2000 if (hns_dsaf_del_mac_mc_port(dsaf_dev,
2001 &mac_entry)) {
2002 ret = -EINVAL;
2003 continue;
2004 }
2005 }
2006 }
2007 }
2008
2009 return ret;
2010 }
2011
2012 static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev,
2013 size_t sizeof_priv)
2014 {
2015 struct dsaf_device *dsaf_dev;
2016
2017 dsaf_dev = devm_kzalloc(dev,
2018 sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL);
2019 if (unlikely(!dsaf_dev)) {
2020 dsaf_dev = ERR_PTR(-ENOMEM);
2021 } else {
2022 dsaf_dev->dev = dev;
2023 dev_set_drvdata(dev, dsaf_dev);
2024 }
2025
2026 return dsaf_dev;
2027 }
2028
2029 /**
2030 * hns_dsaf_free_dev - free dev mem
2031 * @dev: struct device pointer
2032 */
2033 static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev)
2034 {
2035 (void)dev_set_drvdata(dsaf_dev->dev, NULL);
2036 }
2037
2038 /**
2039 * dsaf_pfc_unit_cnt - set pfc unit count
2040 * @dsaf_id: dsa fabric id
2041 * @pport_rate: value array
2042 * @pdsaf_pfc_unit_cnt: value array
2043 */
2044 static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int mac_id,
2045 enum dsaf_port_rate_mode rate)
2046 {
2047 u32 unit_cnt;
2048
2049 switch (rate) {
2050 case DSAF_PORT_RATE_10000:
2051 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2052 break;
2053 case DSAF_PORT_RATE_1000:
2054 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2055 break;
2056 case DSAF_PORT_RATE_2500:
2057 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2058 break;
2059 default:
2060 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2061 }
2062
2063 dsaf_set_dev_field(dsaf_dev,
2064 (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id),
2065 DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S,
2066 unit_cnt);
2067 }
2068
2069 /**
2070 * dsaf_port_work_rate_cfg - fifo
2071 * @dsaf_id: dsa fabric id
2072 * @xge_ge_work_mode
2073 */
2074 void hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id,
2075 enum dsaf_port_rate_mode rate_mode)
2076 {
2077 u32 port_work_mode;
2078
2079 port_work_mode = dsaf_read_dev(
2080 dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id);
2081
2082 if (rate_mode == DSAF_PORT_RATE_10000)
2083 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1);
2084 else
2085 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0);
2086
2087 dsaf_write_dev(dsaf_dev,
2088 DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id,
2089 port_work_mode);
2090
2091 hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode);
2092 }
2093
2094 /**
2095 * hns_dsaf_fix_mac_mode - dsaf modify mac mode
2096 * @mac_cb: mac contrl block
2097 */
2098 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb)
2099 {
2100 enum dsaf_port_rate_mode mode;
2101 struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev;
2102 int mac_id = mac_cb->mac_id;
2103
2104 if (mac_cb->mac_type != HNAE_PORT_SERVICE)
2105 return;
2106 if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII)
2107 mode = DSAF_PORT_RATE_10000;
2108 else
2109 mode = DSAF_PORT_RATE_1000;
2110
2111 hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode);
2112 }
2113
2114 static u32 hns_dsaf_get_inode_prio_reg(int index)
2115 {
2116 int base_index, offset;
2117 u32 base_addr = DSAF_INODE_IN_PRIO_PAUSE_BASE_REG;
2118
2119 base_index = (index + 1) / DSAF_REG_PER_ZONE;
2120 offset = (index + 1) % DSAF_REG_PER_ZONE;
2121
2122 return base_addr + DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET * base_index +
2123 DSAF_INODE_IN_PRIO_PAUSE_OFFSET * offset;
2124 }
2125
2126 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num)
2127 {
2128 struct dsaf_hw_stats *hw_stats
2129 = &dsaf_dev->hw_stats[node_num];
2130 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2131 int i;
2132 u32 reg_tmp;
2133
2134 hw_stats->pad_drop += dsaf_read_dev(dsaf_dev,
2135 DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2136 hw_stats->man_pkts += dsaf_read_dev(dsaf_dev,
2137 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num);
2138 hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev,
2139 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num);
2140 hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev,
2141 DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num);
2142
2143 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2144 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2145 hw_stats->rx_pause_frame +=
2146 dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num);
2147
2148 hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev,
2149 DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num);
2150 hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev,
2151 DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num);
2152 hw_stats->crc_false += dsaf_read_dev(dsaf_dev,
2153 DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2154 hw_stats->bp_drop += dsaf_read_dev(dsaf_dev,
2155 DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2156 hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev,
2157 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2158 hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev,
2159 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2160
2161 hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev,
2162 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 0x80 * (u64)node_num);
2163 hw_stats->stp_drop += dsaf_read_dev(dsaf_dev,
2164 DSAF_INODE_IN_DATA_STP_DISC_0_REG + 0x80 * (u64)node_num);
2165
2166 /* pfc pause frame statistics stored in dsaf inode*/
2167 if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) {
2168 for (i = 0; i < DSAF_PRIO_NR; i++) {
2169 reg_tmp = hns_dsaf_get_inode_prio_reg(i);
2170 hw_stats->rx_pfc[i] += dsaf_read_dev(dsaf_dev,
2171 reg_tmp + 0x4 * (u64)node_num);
2172 hw_stats->tx_pfc[i] += dsaf_read_dev(dsaf_dev,
2173 DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG +
2174 DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET * i +
2175 0xF0 * (u64)node_num);
2176 }
2177 }
2178 hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev,
2179 DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num);
2180 }
2181
2182 /**
2183 *hns_dsaf_get_regs - dump dsaf regs
2184 *@dsaf_dev: dsaf device
2185 *@data:data for value of regs
2186 */
2187 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
2188 {
2189 u32 i = 0;
2190 u32 j;
2191 u32 *p = data;
2192 u32 reg_tmp;
2193 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2194
2195 /* dsaf common registers */
2196 p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG);
2197 p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG);
2198 p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG);
2199 p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG);
2200 p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG);
2201 p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG);
2202 p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG);
2203 p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG);
2204 p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG);
2205
2206 p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4);
2207 p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4);
2208 p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2209 p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2210 p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2211 p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2212 p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4);
2213 p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4);
2214 p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2215 p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4);
2216 p[19] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4);
2217 p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2218 p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4);
2219 p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4);
2220 p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4);
2221
2222 for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2223 p[24 + i] = dsaf_read_dev(ddev,
2224 DSAF_SW_PORT_TYPE_0_REG + i * 4);
2225
2226 p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4);
2227
2228 for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2229 p[33 + i] = dsaf_read_dev(ddev,
2230 DSAF_PORT_DEF_VLAN_0_REG + i * 4);
2231
2232 for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++)
2233 p[41 + i] = dsaf_read_dev(ddev,
2234 DSAF_VM_DEF_VLAN_0_REG + i * 4);
2235
2236 /* dsaf inode registers */
2237 p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG);
2238
2239 p[171] = dsaf_read_dev(ddev,
2240 DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80);
2241
2242 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2243 j = i * DSAF_COMM_CHN + port;
2244 p[172 + i] = dsaf_read_dev(ddev,
2245 DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80);
2246 p[175 + i] = dsaf_read_dev(ddev,
2247 DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80);
2248 p[178 + i] = dsaf_read_dev(ddev,
2249 DSAF_INODE_BP_STATUS_0_REG + j * 0x80);
2250 p[181 + i] = dsaf_read_dev(ddev,
2251 DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80);
2252 p[184 + i] = dsaf_read_dev(ddev,
2253 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80);
2254 p[187 + i] = dsaf_read_dev(ddev,
2255 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80);
2256 p[190 + i] = dsaf_read_dev(ddev,
2257 DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80);
2258 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2259 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2260 p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80);
2261 p[196 + i] = dsaf_read_dev(ddev,
2262 DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80);
2263 p[199 + i] = dsaf_read_dev(ddev,
2264 DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80);
2265 p[202 + i] = dsaf_read_dev(ddev,
2266 DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80);
2267 p[205 + i] = dsaf_read_dev(ddev,
2268 DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80);
2269 p[208 + i] = dsaf_read_dev(ddev,
2270 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80);
2271 p[211 + i] = dsaf_read_dev(ddev,
2272 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80);
2273 p[214 + i] = dsaf_read_dev(ddev,
2274 DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80);
2275 p[217 + i] = dsaf_read_dev(ddev,
2276 DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4);
2277 p[220 + i] = dsaf_read_dev(ddev,
2278 DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4);
2279 p[223 + i] = dsaf_read_dev(ddev,
2280 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4);
2281 p[224 + i] = dsaf_read_dev(ddev,
2282 DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4);
2283 }
2284
2285 p[227] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
2286
2287 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2288 j = i * DSAF_COMM_CHN + port;
2289 p[228 + i] = dsaf_read_dev(ddev,
2290 DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4);
2291 }
2292
2293 p[231] = dsaf_read_dev(ddev,
2294 DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 4);
2295
2296 /* dsaf inode registers */
2297 for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) {
2298 j = i * DSAF_COMM_CHN + port;
2299 p[232 + i] = dsaf_read_dev(ddev,
2300 DSAF_SBM_CFG_REG_0_REG + j * 0x80);
2301 p[235 + i] = dsaf_read_dev(ddev,
2302 DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80);
2303 p[238 + i] = dsaf_read_dev(ddev,
2304 DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80);
2305 p[241 + i] = dsaf_read_dev(ddev,
2306 DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80);
2307 p[244 + i] = dsaf_read_dev(ddev,
2308 DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80);
2309 p[245 + i] = dsaf_read_dev(ddev,
2310 DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80);
2311 p[248 + i] = dsaf_read_dev(ddev,
2312 DSAF_SBM_BP_CNT_0_0_REG + j * 0x80);
2313 p[251 + i] = dsaf_read_dev(ddev,
2314 DSAF_SBM_BP_CNT_1_0_REG + j * 0x80);
2315 p[254 + i] = dsaf_read_dev(ddev,
2316 DSAF_SBM_BP_CNT_2_0_REG + j * 0x80);
2317 p[257 + i] = dsaf_read_dev(ddev,
2318 DSAF_SBM_BP_CNT_3_0_REG + j * 0x80);
2319 p[260 + i] = dsaf_read_dev(ddev,
2320 DSAF_SBM_INER_ST_0_REG + j * 0x80);
2321 p[263 + i] = dsaf_read_dev(ddev,
2322 DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80);
2323 p[266 + i] = dsaf_read_dev(ddev,
2324 DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80);
2325 p[269 + i] = dsaf_read_dev(ddev,
2326 DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80);
2327 p[272 + i] = dsaf_read_dev(ddev,
2328 DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80);
2329 p[275 + i] = dsaf_read_dev(ddev,
2330 DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80);
2331 p[278 + i] = dsaf_read_dev(ddev,
2332 DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80);
2333 p[281 + i] = dsaf_read_dev(ddev,
2334 DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80);
2335 p[284 + i] = dsaf_read_dev(ddev,
2336 DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80);
2337 p[287 + i] = dsaf_read_dev(ddev,
2338 DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80);
2339 p[290 + i] = dsaf_read_dev(ddev,
2340 DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80);
2341 p[293 + i] = dsaf_read_dev(ddev,
2342 DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80);
2343 p[296 + i] = dsaf_read_dev(ddev,
2344 DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80);
2345 p[299 + i] = dsaf_read_dev(ddev,
2346 DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80);
2347 p[302 + i] = dsaf_read_dev(ddev,
2348 DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80);
2349 p[305 + i] = dsaf_read_dev(ddev,
2350 DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80);
2351 p[308 + i] = dsaf_read_dev(ddev,
2352 DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80);
2353 }
2354
2355 /* dsaf onode registers */
2356 for (i = 0; i < DSAF_XOD_NUM; i++) {
2357 p[311 + i] = dsaf_read_dev(ddev,
2358 DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90);
2359 p[319 + i] = dsaf_read_dev(ddev,
2360 DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90);
2361 p[327 + i] = dsaf_read_dev(ddev,
2362 DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90);
2363 p[335 + i] = dsaf_read_dev(ddev,
2364 DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90);
2365 p[343 + i] = dsaf_read_dev(ddev,
2366 DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90);
2367 p[351 + i] = dsaf_read_dev(ddev,
2368 DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90);
2369 }
2370
2371 p[359] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
2372 p[360] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
2373 p[361] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
2374
2375 for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) {
2376 j = i * DSAF_COMM_CHN + port;
2377 p[362 + i] = dsaf_read_dev(ddev,
2378 DSAF_XOD_GNT_L_0_REG + j * 0x90);
2379 p[365 + i] = dsaf_read_dev(ddev,
2380 DSAF_XOD_GNT_H_0_REG + j * 0x90);
2381 p[368 + i] = dsaf_read_dev(ddev,
2382 DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90);
2383 p[371 + i] = dsaf_read_dev(ddev,
2384 DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90);
2385 p[374 + i] = dsaf_read_dev(ddev,
2386 DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90);
2387 p[377 + i] = dsaf_read_dev(ddev,
2388 DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90);
2389 p[380 + i] = dsaf_read_dev(ddev,
2390 DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90);
2391 p[383 + i] = dsaf_read_dev(ddev,
2392 DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90);
2393 p[386 + i] = dsaf_read_dev(ddev,
2394 DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90);
2395 p[389 + i] = dsaf_read_dev(ddev,
2396 DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90);
2397 }
2398
2399 p[392] = dsaf_read_dev(ddev,
2400 DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
2401 p[393] = dsaf_read_dev(ddev,
2402 DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
2403 p[394] = dsaf_read_dev(ddev,
2404 DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
2405 p[395] = dsaf_read_dev(ddev,
2406 DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
2407 p[396] = dsaf_read_dev(ddev,
2408 DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
2409 p[397] = dsaf_read_dev(ddev,
2410 DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
2411 p[398] = dsaf_read_dev(ddev,
2412 DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
2413 p[399] = dsaf_read_dev(ddev,
2414 DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
2415 p[400] = dsaf_read_dev(ddev,
2416 DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
2417 p[401] = dsaf_read_dev(ddev,
2418 DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
2419 p[402] = dsaf_read_dev(ddev,
2420 DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
2421 p[403] = dsaf_read_dev(ddev,
2422 DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
2423 p[404] = dsaf_read_dev(ddev,
2424 DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90);
2425
2426 /* dsaf voq registers */
2427 for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) {
2428 j = (i * DSAF_COMM_CHN + port) * 0x90;
2429 p[405 + i] = dsaf_read_dev(ddev,
2430 DSAF_VOQ_ECC_INVERT_EN_0_REG + j);
2431 p[408 + i] = dsaf_read_dev(ddev,
2432 DSAF_VOQ_SRAM_PKT_NUM_0_REG + j);
2433 p[411 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
2434 p[414 + i] = dsaf_read_dev(ddev,
2435 DSAF_VOQ_OUT_PKT_NUM_0_REG + j);
2436 p[417 + i] = dsaf_read_dev(ddev,
2437 DSAF_VOQ_ECC_ERR_ADDR_0_REG + j);
2438 p[420 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
2439 p[423 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
2440 p[426 + i] = dsaf_read_dev(ddev,
2441 DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j);
2442 p[429 + i] = dsaf_read_dev(ddev,
2443 DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j);
2444 p[432 + i] = dsaf_read_dev(ddev,
2445 DSAF_VOQ_PPE_XOD_REQ_0_REG + j);
2446 p[435 + i] = dsaf_read_dev(ddev,
2447 DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j);
2448 p[438 + i] = dsaf_read_dev(ddev,
2449 DSAF_VOQ_BP_ALL_THRD_0_REG + j);
2450 }
2451
2452 /* dsaf tbl registers */
2453 p[441] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
2454 p[442] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
2455 p[443] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
2456 p[444] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
2457 p[445] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
2458 p[446] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
2459 p[447] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
2460 p[448] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
2461 p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
2462 p[450] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
2463 p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
2464 p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
2465 p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
2466 p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
2467 p[455] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
2468 p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
2469 p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
2470 p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
2471 p[459] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
2472 p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
2473 p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
2474 p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
2475 p[463] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
2476
2477 for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
2478 j = i * 0x8;
2479 p[464 + 2 * i] = dsaf_read_dev(ddev,
2480 DSAF_TBL_DA0_MIS_INFO1_0_REG + j);
2481 p[465 + 2 * i] = dsaf_read_dev(ddev,
2482 DSAF_TBL_DA0_MIS_INFO0_0_REG + j);
2483 }
2484
2485 p[480] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
2486 p[481] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
2487 p[482] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
2488 p[483] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
2489 p[484] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
2490 p[485] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
2491 p[486] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
2492 p[487] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
2493 p[488] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
2494 p[489] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
2495 p[490] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
2496 p[491] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
2497
2498 /* dsaf other registers */
2499 p[492] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
2500 p[493] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
2501 p[494] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
2502 p[495] = dsaf_read_dev(ddev,
2503 DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4);
2504 p[496] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
2505 p[497] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
2506
2507 if (!is_ver1)
2508 p[498] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
2509
2510 /* mark end of dsaf regs */
2511 for (i = 499; i < 504; i++)
2512 p[i] = 0xdddddddd;
2513 }
2514
2515 static char *hns_dsaf_get_node_stats_strings(char *data, int node,
2516 struct dsaf_device *dsaf_dev)
2517 {
2518 char *buff = data;
2519 int i;
2520 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2521
2522 snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node);
2523 buff += ETH_GSTRING_LEN;
2524 snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node);
2525 buff += ETH_GSTRING_LEN;
2526 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node);
2527 buff += ETH_GSTRING_LEN;
2528 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node);
2529 buff += ETH_GSTRING_LEN;
2530 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node);
2531 buff += ETH_GSTRING_LEN;
2532 snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node);
2533 buff += ETH_GSTRING_LEN;
2534 snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node);
2535 buff += ETH_GSTRING_LEN;
2536 snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node);
2537 buff += ETH_GSTRING_LEN;
2538 snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node);
2539 buff += ETH_GSTRING_LEN;
2540 snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node);
2541 buff += ETH_GSTRING_LEN;
2542 snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node);
2543 buff += ETH_GSTRING_LEN;
2544 snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node);
2545 buff += ETH_GSTRING_LEN;
2546 snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node);
2547 buff += ETH_GSTRING_LEN;
2548 if (node < DSAF_SERVICE_NW_NUM && !is_ver1) {
2549 for (i = 0; i < DSAF_PRIO_NR; i++) {
2550 snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2551 ETH_GSTRING_LEN, "inod%d_pfc_prio%d_pkts",
2552 node, i);
2553 snprintf(buff + 1 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2554 ETH_GSTRING_LEN, "onod%d_pfc_prio%d_pkts",
2555 node, i);
2556 buff += ETH_GSTRING_LEN;
2557 }
2558 buff += 1 * DSAF_PRIO_NR * ETH_GSTRING_LEN;
2559 }
2560 snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node);
2561 buff += ETH_GSTRING_LEN;
2562
2563 return buff;
2564 }
2565
2566 static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data,
2567 int node_num)
2568 {
2569 u64 *p = data;
2570 int i;
2571 struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num];
2572 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2573
2574 p[0] = hw_stats->pad_drop;
2575 p[1] = hw_stats->man_pkts;
2576 p[2] = hw_stats->rx_pkts;
2577 p[3] = hw_stats->rx_pkt_id;
2578 p[4] = hw_stats->rx_pause_frame;
2579 p[5] = hw_stats->release_buf_num;
2580 p[6] = hw_stats->sbm_drop;
2581 p[7] = hw_stats->crc_false;
2582 p[8] = hw_stats->bp_drop;
2583 p[9] = hw_stats->rslt_drop;
2584 p[10] = hw_stats->local_addr_false;
2585 p[11] = hw_stats->vlan_drop;
2586 p[12] = hw_stats->stp_drop;
2587 if (node_num < DSAF_SERVICE_NW_NUM && !is_ver1) {
2588 for (i = 0; i < DSAF_PRIO_NR; i++) {
2589 p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i];
2590 p[13 + i + 1 * DSAF_PRIO_NR] = hw_stats->tx_pfc[i];
2591 }
2592 p[29] = hw_stats->tx_pkts;
2593 return &p[30];
2594 }
2595
2596 p[13] = hw_stats->tx_pkts;
2597 return &p[14];
2598 }
2599
2600 /**
2601 *hns_dsaf_get_stats - get dsaf statistic
2602 *@ddev: dsaf device
2603 *@data:statistic value
2604 *@port: port num
2605 */
2606 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port)
2607 {
2608 u64 *p = data;
2609 int node_num = port;
2610
2611 /* for ge/xge node info */
2612 p = hns_dsaf_get_node_stats(ddev, p, node_num);
2613
2614 /* for ppe node info */
2615 node_num = port + DSAF_PPE_INODE_BASE;
2616 (void)hns_dsaf_get_node_stats(ddev, p, node_num);
2617 }
2618
2619 /**
2620 *hns_dsaf_get_sset_count - get dsaf string set count
2621 *@stringset: type of values in data
2622 *return dsaf string name count
2623 */
2624 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset)
2625 {
2626 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2627
2628 if (stringset == ETH_SS_STATS) {
2629 if (is_ver1)
2630 return DSAF_STATIC_NUM;
2631 else
2632 return DSAF_V2_STATIC_NUM;
2633 }
2634 return 0;
2635 }
2636
2637 /**
2638 *hns_dsaf_get_strings - get dsaf string set
2639 *@stringset:srting set index
2640 *@data:strings name value
2641 *@port:port index
2642 */
2643 void hns_dsaf_get_strings(int stringset, u8 *data, int port,
2644 struct dsaf_device *dsaf_dev)
2645 {
2646 char *buff = (char *)data;
2647 int node = port;
2648
2649 if (stringset != ETH_SS_STATS)
2650 return;
2651
2652 /* for ge/xge node info */
2653 buff = hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2654
2655 /* for ppe node info */
2656 node = port + DSAF_PPE_INODE_BASE;
2657 (void)hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2658 }
2659
2660 /**
2661 *hns_dsaf_get_sset_count - get dsaf regs count
2662 *return dsaf regs count
2663 */
2664 int hns_dsaf_get_regs_count(void)
2665 {
2666 return DSAF_DUMP_REGS_NUM;
2667 }
2668
2669 /* Reserve the last TCAM entry for promisc support */
2670 #define dsaf_promisc_tcam_entry(port) \
2671 (DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM + (port))
2672 void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev,
2673 u32 port, bool enable)
2674 {
2675 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2676 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
2677 u16 entry_index;
2678 struct dsaf_drv_tbl_tcam_key tbl_tcam_data, tbl_tcam_mask;
2679 struct dsaf_tbl_tcam_mcast_cfg mac_data = {0};
2680
2681 if ((AE_IS_VER1(dsaf_dev->dsaf_ver)) || HNS_DSAF_IS_DEBUG(dsaf_dev))
2682 return;
2683
2684 /* find the tcam entry index for promisc */
2685 entry_index = dsaf_promisc_tcam_entry(port);
2686
2687 memset(&tbl_tcam_data, 0, sizeof(tbl_tcam_data));
2688 memset(&tbl_tcam_mask, 0, sizeof(tbl_tcam_mask));
2689
2690 /* config key mask */
2691 if (enable) {
2692 dsaf_set_field(tbl_tcam_data.low.bits.port_vlan,
2693 DSAF_TBL_TCAM_KEY_PORT_M,
2694 DSAF_TBL_TCAM_KEY_PORT_S, port);
2695 dsaf_set_field(tbl_tcam_mask.low.bits.port_vlan,
2696 DSAF_TBL_TCAM_KEY_PORT_M,
2697 DSAF_TBL_TCAM_KEY_PORT_S, 0xf);
2698
2699 /* SUB_QID */
2700 dsaf_set_bit(mac_data.tbl_mcast_port_msk[0],
2701 DSAF_SERVICE_NW_NUM, true);
2702 mac_data.tbl_mcast_item_vld = true; /* item_vld bit */
2703 } else {
2704 mac_data.tbl_mcast_item_vld = false; /* item_vld bit */
2705 }
2706
2707 dev_dbg(dsaf_dev->dev,
2708 "set_promisc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
2709 dsaf_dev->ae_dev.name, tbl_tcam_data.high.val,
2710 tbl_tcam_data.low.val, entry_index);
2711
2712 /* config promisc entry with mask */
2713 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index,
2714 (struct dsaf_tbl_tcam_data *)&tbl_tcam_data,
2715 (struct dsaf_tbl_tcam_data *)&tbl_tcam_mask,
2716 &mac_data);
2717
2718 /* config software entry */
2719 soft_mac_entry += entry_index;
2720 soft_mac_entry->index = enable ? entry_index : DSAF_INVALID_ENTRY_IDX;
2721 }
2722
2723 /**
2724 * dsaf_probe - probo dsaf dev
2725 * @pdev: dasf platform device
2726 * retuen 0 - success , negative --fail
2727 */
2728 static int hns_dsaf_probe(struct platform_device *pdev)
2729 {
2730 struct dsaf_device *dsaf_dev;
2731 int ret;
2732
2733 dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv));
2734 if (IS_ERR(dsaf_dev)) {
2735 ret = PTR_ERR(dsaf_dev);
2736 dev_err(&pdev->dev,
2737 "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret);
2738 return ret;
2739 }
2740
2741 ret = hns_dsaf_get_cfg(dsaf_dev);
2742 if (ret)
2743 goto free_dev;
2744
2745 ret = hns_dsaf_init(dsaf_dev);
2746 if (ret)
2747 goto free_dev;
2748
2749 ret = hns_mac_init(dsaf_dev);
2750 if (ret)
2751 goto uninit_dsaf;
2752
2753 ret = hns_ppe_init(dsaf_dev);
2754 if (ret)
2755 goto uninit_mac;
2756
2757 ret = hns_dsaf_ae_init(dsaf_dev);
2758 if (ret)
2759 goto uninit_ppe;
2760
2761 return 0;
2762
2763 uninit_ppe:
2764 hns_ppe_uninit(dsaf_dev);
2765
2766 uninit_mac:
2767 hns_mac_uninit(dsaf_dev);
2768
2769 uninit_dsaf:
2770 hns_dsaf_free(dsaf_dev);
2771
2772 free_dev:
2773 hns_dsaf_free_dev(dsaf_dev);
2774
2775 return ret;
2776 }
2777
2778 /**
2779 * dsaf_remove - remove dsaf dev
2780 * @pdev: dasf platform device
2781 */
2782 static int hns_dsaf_remove(struct platform_device *pdev)
2783 {
2784 struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev);
2785
2786 hns_dsaf_ae_uninit(dsaf_dev);
2787
2788 hns_ppe_uninit(dsaf_dev);
2789
2790 hns_mac_uninit(dsaf_dev);
2791
2792 hns_dsaf_free(dsaf_dev);
2793
2794 hns_dsaf_free_dev(dsaf_dev);
2795
2796 return 0;
2797 }
2798
2799 static const struct of_device_id g_dsaf_match[] = {
2800 {.compatible = "hisilicon,hns-dsaf-v1"},
2801 {.compatible = "hisilicon,hns-dsaf-v2"},
2802 {}
2803 };
2804 MODULE_DEVICE_TABLE(of, g_dsaf_match);
2805
2806 static struct platform_driver g_dsaf_driver = {
2807 .probe = hns_dsaf_probe,
2808 .remove = hns_dsaf_remove,
2809 .driver = {
2810 .name = DSAF_DRV_NAME,
2811 .of_match_table = g_dsaf_match,
2812 .acpi_match_table = hns_dsaf_acpi_match,
2813 },
2814 };
2815
2816 module_platform_driver(g_dsaf_driver);
2817
2818 /**
2819 * hns_dsaf_roce_reset - reset dsaf and roce
2820 * @dsaf_fwnode: Pointer to framework node for the dasf
2821 * @enable: false - request reset , true - drop reset
2822 * retuen 0 - success , negative -fail
2823 */
2824 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset)
2825 {
2826 struct dsaf_device *dsaf_dev;
2827 struct platform_device *pdev;
2828 u32 mp;
2829 u32 sl;
2830 u32 credit;
2831 int i;
2832 const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
2833 {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
2834 {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
2835 {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
2836 {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
2837 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
2838 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
2839 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
2840 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
2841 };
2842 const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
2843 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
2844 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
2845 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
2846 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
2847 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
2848 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
2849 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
2850 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
2851 };
2852
2853 /* find the platform device corresponding to fwnode */
2854 if (is_of_node(dsaf_fwnode)) {
2855 pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
2856 } else if (is_acpi_device_node(dsaf_fwnode)) {
2857 pdev = hns_dsaf_find_platform_device(dsaf_fwnode);
2858 } else {
2859 pr_err("fwnode is neither OF or ACPI type\n");
2860 return -EINVAL;
2861 }
2862
2863 /* check if we were a success in fetching pdev */
2864 if (!pdev) {
2865 pr_err("couldn't find platform device for node\n");
2866 return -ENODEV;
2867 }
2868
2869 /* retrieve the dsaf_device from the driver data */
2870 dsaf_dev = dev_get_drvdata(&pdev->dev);
2871 if (!dsaf_dev) {
2872 dev_err(&pdev->dev, "dsaf_dev is NULL\n");
2873 return -ENODEV;
2874 }
2875
2876 /* now, make sure we are running on compatible SoC */
2877 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
2878 dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n",
2879 dsaf_dev->ae_dev.name);
2880 return -ENODEV;
2881 }
2882
2883 /* do reset or de-reset according to the flag */
2884 if (!dereset) {
2885 /* reset rocee-channels in dsaf and rocee */
2886 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
2887 false);
2888 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false);
2889 } else {
2890 /* configure dsaf tx roce correspond to port map and sl map */
2891 mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
2892 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
2893 dsaf_set_field(mp, 7 << i * 3, i * 3,
2894 port_map[i][DSAF_ROCE_6PORT_MODE]);
2895 dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
2896 dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
2897
2898 sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
2899 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
2900 dsaf_set_field(sl, 3 << i * 2, i * 2,
2901 sl_map[i][DSAF_ROCE_6PORT_MODE]);
2902 dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
2903
2904 /* de-reset rocee-channels in dsaf and rocee */
2905 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
2906 true);
2907 msleep(SRST_TIME_INTERVAL);
2908 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true);
2909
2910 /* enable dsaf channel rocee credit */
2911 credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
2912 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);
2913 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
2914
2915 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);
2916 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
2917 }
2918 return 0;
2919 }
2920 EXPORT_SYMBOL(hns_dsaf_roce_reset);
2921
2922 MODULE_LICENSE("GPL");
2923 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
2924 MODULE_DESCRIPTION("HNS DSAF driver");
2925 MODULE_VERSION(DSAF_MOD_VERSION);
Linux with added FPC-III support