drivers/net/ethernet/huawei/hinic/hinic_hw_if.h

   1 /*
   2  * Huawei HiNIC PCI Express Linux driver
   3  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  */
  15
  16 #ifndef HINIC_HW_IF_H
  17 #define HINIC_HW_IF_H
  18
  19 #include <linux/pci.h>
  20 #include <linux/io.h>
  21 #include <linux/types.h>
  22 #include <asm/byteorder.h>
  23
  24 #define HINIC_DMA_ATTR_ST_SHIFT                                 0
  25 #define HINIC_DMA_ATTR_AT_SHIFT                                 8
  26 #define HINIC_DMA_ATTR_PH_SHIFT                                 10
  27 #define HINIC_DMA_ATTR_NO_SNOOPING_SHIFT                        12
  28 #define HINIC_DMA_ATTR_TPH_EN_SHIFT                             13
  29
  30 #define HINIC_DMA_ATTR_ST_MASK                                  0xFF
  31 #define HINIC_DMA_ATTR_AT_MASK                                  0x3
  32 #define HINIC_DMA_ATTR_PH_MASK                                  0x3
  33 #define HINIC_DMA_ATTR_NO_SNOOPING_MASK                         0x1
  34 #define HINIC_DMA_ATTR_TPH_EN_MASK                              0x1
  35
  36 #define HINIC_DMA_ATTR_SET(val, member)                         \
  37         (((u32)(val) & HINIC_DMA_ATTR_##member##_MASK) <<       \
  38          HINIC_DMA_ATTR_##member##_SHIFT)
  39
  40 #define HINIC_DMA_ATTR_CLEAR(val, member)                       \
  41         ((val) & (~(HINIC_DMA_ATTR_##member##_MASK              \
  42          << HINIC_DMA_ATTR_##member##_SHIFT)))
  43
  44 #define HINIC_FA0_FUNC_IDX_SHIFT                                0
  45 #define HINIC_FA0_PF_IDX_SHIFT                                  10
  46 #define HINIC_FA0_PCI_INTF_IDX_SHIFT                            14
  47 /* reserved members - off 16 */
  48 #define HINIC_FA0_FUNC_TYPE_SHIFT                               24
  49
  50 #define HINIC_FA0_FUNC_IDX_MASK                                 0x3FF
  51 #define HINIC_FA0_PF_IDX_MASK                                   0xF
  52 #define HINIC_FA0_PCI_INTF_IDX_MASK                             0x3
  53 #define HINIC_FA0_FUNC_TYPE_MASK                                0x1
  54
  55 #define HINIC_FA0_GET(val, member)                              \
  56         (((val) >> HINIC_FA0_##member##_SHIFT) & HINIC_FA0_##member##_MASK)
  57
  58 #define HINIC_FA1_AEQS_PER_FUNC_SHIFT                           8
  59 /* reserved members - off 10 */
  60 #define HINIC_FA1_CEQS_PER_FUNC_SHIFT                           12
  61 /* reserved members - off 15 */
  62 #define HINIC_FA1_IRQS_PER_FUNC_SHIFT                           20
  63 #define HINIC_FA1_DMA_ATTR_PER_FUNC_SHIFT                       24
  64 /* reserved members - off 27 */
  65 #define HINIC_FA1_INIT_STATUS_SHIFT                             30
  66
  67 #define HINIC_FA1_AEQS_PER_FUNC_MASK                            0x3
  68 #define HINIC_FA1_CEQS_PER_FUNC_MASK                            0x7
  69 #define HINIC_FA1_IRQS_PER_FUNC_MASK                            0xF
  70 #define HINIC_FA1_DMA_ATTR_PER_FUNC_MASK                        0x7
  71 #define HINIC_FA1_INIT_STATUS_MASK                              0x1
  72
  73 #define HINIC_FA1_GET(val, member)                              \
  74         (((val) >> HINIC_FA1_##member##_SHIFT) & HINIC_FA1_##member##_MASK)
  75
  76 #define HINIC_FA4_OUTBOUND_STATE_SHIFT                          0
  77 #define HINIC_FA4_DB_STATE_SHIFT                                1
  78
  79 #define HINIC_FA4_OUTBOUND_STATE_MASK                           0x1
  80 #define HINIC_FA4_DB_STATE_MASK                                 0x1
  81
  82 #define HINIC_FA4_GET(val, member)                              \
  83         (((val) >> HINIC_FA4_##member##_SHIFT) & HINIC_FA4_##member##_MASK)
  84
  85 #define HINIC_FA4_SET(val, member)                              \
  86         ((((u32)val) & HINIC_FA4_##member##_MASK) << HINIC_FA4_##member##_SHIFT)
  87
  88 #define HINIC_FA4_CLEAR(val, member)                            \
  89         ((val) & (~(HINIC_FA4_##member##_MASK << HINIC_FA4_##member##_SHIFT)))
  90
  91 #define HINIC_FA5_PF_ACTION_SHIFT                               0
  92 #define HINIC_FA5_PF_ACTION_MASK                                0xFFFF
  93
  94 #define HINIC_FA5_SET(val, member)                              \
  95         (((u32)(val) & HINIC_FA5_##member##_MASK) << HINIC_FA5_##member##_SHIFT)
  96
  97 #define HINIC_FA5_CLEAR(val, member)                            \
  98         ((val) & (~(HINIC_FA5_##member##_MASK << HINIC_FA5_##member##_SHIFT)))
  99
 100 #define HINIC_PPF_ELECTION_IDX_SHIFT                            0
 101 #define HINIC_PPF_ELECTION_IDX_MASK                             0x1F
 102
 103 #define HINIC_PPF_ELECTION_SET(val, member)                     \
 104         (((u32)(val) & HINIC_PPF_ELECTION_##member##_MASK) <<   \
 105          HINIC_PPF_ELECTION_##member##_SHIFT)
 106
 107 #define HINIC_PPF_ELECTION_GET(val, member)                     \
 108         (((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) &       \
 109          HINIC_PPF_ELECTION_##member##_MASK)
 110
 111 #define HINIC_PPF_ELECTION_CLEAR(val, member)                   \
 112         ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK          \
 113          << HINIC_PPF_ELECTION_##member##_SHIFT)))
 114
 115 #define HINIC_MSIX_PENDING_LIMIT_SHIFT                          0
 116 #define HINIC_MSIX_COALESC_TIMER_SHIFT                          8
 117 #define HINIC_MSIX_LLI_TIMER_SHIFT                              16
 118 #define HINIC_MSIX_LLI_CREDIT_SHIFT                             24
 119 #define HINIC_MSIX_RESEND_TIMER_SHIFT                           29
 120
 121 #define HINIC_MSIX_PENDING_LIMIT_MASK                           0xFF
 122 #define HINIC_MSIX_COALESC_TIMER_MASK                           0xFF
 123 #define HINIC_MSIX_LLI_TIMER_MASK                               0xFF
 124 #define HINIC_MSIX_LLI_CREDIT_MASK                              0x1F
 125 #define HINIC_MSIX_RESEND_TIMER_MASK                            0x7
 126
 127 #define HINIC_MSIX_ATTR_SET(val, member)                        \
 128         (((u32)(val) & HINIC_MSIX_##member##_MASK) <<           \
 129          HINIC_MSIX_##member##_SHIFT)
 130
 131 #define HINIC_MSIX_ATTR_GET(val, member)                        \
 132         (((val) >> HINIC_MSIX_##member##_SHIFT) &               \
 133          HINIC_MSIX_##member##_MASK)
 134
 135 #define HINIC_MSIX_CNT_RESEND_TIMER_SHIFT                       29
 136
 137 #define HINIC_MSIX_CNT_RESEND_TIMER_MASK                        0x1
 138
 139 #define HINIC_MSIX_CNT_SET(val, member)                         \
 140         (((u32)(val) & HINIC_MSIX_CNT_##member##_MASK) <<       \
 141          HINIC_MSIX_CNT_##member##_SHIFT)
 142
 143 #define HINIC_HWIF_NUM_AEQS(hwif)       ((hwif)->attr.num_aeqs)
 144 #define HINIC_HWIF_NUM_CEQS(hwif)       ((hwif)->attr.num_ceqs)
 145 #define HINIC_HWIF_NUM_IRQS(hwif)       ((hwif)->attr.num_irqs)
 146 #define HINIC_HWIF_FUNC_IDX(hwif)       ((hwif)->attr.func_idx)
 147 #define HINIC_HWIF_PCI_INTF(hwif)       ((hwif)->attr.pci_intf_idx)
 148 #define HINIC_HWIF_PF_IDX(hwif)         ((hwif)->attr.pf_idx)
 149
 150 #define HINIC_FUNC_TYPE(hwif)           ((hwif)->attr.func_type)
 151 #define HINIC_IS_PF(hwif)               (HINIC_FUNC_TYPE(hwif) == HINIC_PF)
 152 #define HINIC_IS_PPF(hwif)              (HINIC_FUNC_TYPE(hwif) == HINIC_PPF)
 153
 154 #define HINIC_PCI_CFG_REGS_BAR          0
 155 #define HINIC_PCI_DB_BAR                4
 156
 157 #define HINIC_PCIE_ST_DISABLE           0
 158 #define HINIC_PCIE_AT_DISABLE           0
 159 #define HINIC_PCIE_PH_DISABLE           0
 160
 161 #define HINIC_EQ_MSIX_PENDING_LIMIT_DEFAULT     0       /* Disabled */
 162 #define HINIC_EQ_MSIX_COALESC_TIMER_DEFAULT     0xFF    /* max */
 163 #define HINIC_EQ_MSIX_LLI_TIMER_DEFAULT         0       /* Disabled */
 164 #define HINIC_EQ_MSIX_LLI_CREDIT_LIMIT_DEFAULT  0       /* Disabled */
 165 #define HINIC_EQ_MSIX_RESEND_TIMER_DEFAULT      7       /* max */
 166
 167 enum hinic_pcie_nosnoop {
 168         HINIC_PCIE_SNOOP        = 0,
 169         HINIC_PCIE_NO_SNOOP     = 1,
 170 };
 171
 172 enum hinic_pcie_tph {
 173         HINIC_PCIE_TPH_DISABLE  = 0,
 174         HINIC_PCIE_TPH_ENABLE   = 1,
 175 };
 176
 177 enum hinic_func_type {
 178         HINIC_PF        = 0,
 179         HINIC_PPF       = 2,
 180 };
 181
 182 enum hinic_mod_type {
 183         HINIC_MOD_COMM  = 0,    /* HW communication module */
 184         HINIC_MOD_L2NIC = 1,    /* L2NIC module */
 185         HINIC_MOD_CFGM  = 7,    /* Configuration module */
 186
 187         HINIC_MOD_MAX   = 15
 188 };
 189
 190 enum hinic_node_id {
 191         HINIC_NODE_ID_MGMT = 21,
 192 };
 193
 194 enum hinic_pf_action {
 195         HINIC_PF_MGMT_INIT = 0x0,
 196
 197         HINIC_PF_MGMT_ACTIVE = 0x11,
 198 };
 199
 200 enum hinic_outbound_state {
 201         HINIC_OUTBOUND_ENABLE  = 0,
 202         HINIC_OUTBOUND_DISABLE = 1,
 203 };
 204
 205 enum hinic_db_state {
 206         HINIC_DB_ENABLE  = 0,
 207         HINIC_DB_DISABLE = 1,
 208 };
 209
 210 struct hinic_func_attr {
 211         u16                     func_idx;
 212         u8                      pf_idx;
 213         u8                      pci_intf_idx;
 214
 215         enum hinic_func_type    func_type;
 216
 217         u8                      ppf_idx;
 218
 219         u16                     num_irqs;
 220         u8                      num_aeqs;
 221         u8                      num_ceqs;
 222
 223         u8                      num_dma_attr;
 224 };
 225
 226 struct hinic_hwif {
 227         struct pci_dev          *pdev;
 228         void __iomem            *cfg_regs_bar;
 229
 230         struct hinic_func_attr  attr;
 231 };
 232
 233 static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg)
 234 {
 235         return be32_to_cpu(readl(hwif->cfg_regs_bar + reg));
 236 }
 237
 238 static inline void hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg,
 239                                         u32 val)
 240 {
 241         writel(cpu_to_be32(val), hwif->cfg_regs_bar + reg);
 242 }
 243
 244 int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index,
 245                         u8 pending_limit, u8 coalesc_timer,
 246                         u8 lli_timer_cfg, u8 lli_credit_limit,
 247                         u8 resend_timer);
 248
 249 int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index,
 250                         u8 *pending_limit, u8 *coalesc_timer_cfg,
 251                         u8 *lli_timer, u8 *lli_credit_limit,
 252                         u8 *resend_timer);
 253
 254 int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index);
 255
 256 void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action);
 257
 258 enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif);
 259
 260 void hinic_outbound_state_set(struct hinic_hwif *hwif,
 261                               enum hinic_outbound_state outbound_state);
 262
 263 enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif);
 264
 265 void hinic_db_state_set(struct hinic_hwif *hwif,
 266                         enum hinic_db_state db_state);
 267
 268 int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev);
 269
 270 void hinic_free_hwif(struct hinic_hwif *hwif);
 271
 272 #endif