1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 #include <linux/if_ether.h>
25 #include <linux/delay.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
30 #include "e1000_mac.h"
34 static s32
igb_set_default_fc(struct e1000_hw
*hw
);
35 static s32
igb_set_fc_watermarks(struct e1000_hw
*hw
);
38 * igb_get_bus_info_pcie - Get PCIe bus information
39 * @hw: pointer to the HW structure
41 * Determines and stores the system bus information for a particular
42 * network interface. The following bus information is determined and stored:
43 * bus speed, bus width, type (PCIe), and PCIe function.
45 s32
igb_get_bus_info_pcie(struct e1000_hw
*hw
)
47 struct e1000_bus_info
*bus
= &hw
->bus
;
52 bus
->type
= e1000_bus_type_pci_express
;
54 ret_val
= igb_read_pcie_cap_reg(hw
,
58 bus
->width
= e1000_bus_width_unknown
;
59 bus
->speed
= e1000_bus_speed_unknown
;
61 switch (pcie_link_status
& PCI_EXP_LNKSTA_CLS
) {
62 case PCI_EXP_LNKSTA_CLS_2_5GB
:
63 bus
->speed
= e1000_bus_speed_2500
;
65 case PCI_EXP_LNKSTA_CLS_5_0GB
:
66 bus
->speed
= e1000_bus_speed_5000
;
69 bus
->speed
= e1000_bus_speed_unknown
;
73 bus
->width
= (enum e1000_bus_width
)((pcie_link_status
&
74 PCI_EXP_LNKSTA_NLW
) >>
75 PCI_EXP_LNKSTA_NLW_SHIFT
);
78 reg
= rd32(E1000_STATUS
);
79 bus
->func
= (reg
& E1000_STATUS_FUNC_MASK
) >> E1000_STATUS_FUNC_SHIFT
;
85 * igb_clear_vfta - Clear VLAN filter table
86 * @hw: pointer to the HW structure
88 * Clears the register array which contains the VLAN filter table by
89 * setting all the values to 0.
91 void igb_clear_vfta(struct e1000_hw
*hw
)
95 for (offset
= E1000_VLAN_FILTER_TBL_SIZE
; offset
--;)
96 hw
->mac
.ops
.write_vfta(hw
, offset
, 0);
100 * igb_write_vfta - Write value to VLAN filter table
101 * @hw: pointer to the HW structure
102 * @offset: register offset in VLAN filter table
103 * @value: register value written to VLAN filter table
105 * Writes value at the given offset in the register array which stores
106 * the VLAN filter table.
108 void igb_write_vfta(struct e1000_hw
*hw
, u32 offset
, u32 value
)
110 struct igb_adapter
*adapter
= hw
->back
;
112 array_wr32(E1000_VFTA
, offset
, value
);
115 adapter
->shadow_vfta
[offset
] = value
;
119 * igb_init_rx_addrs - Initialize receive address's
120 * @hw: pointer to the HW structure
121 * @rar_count: receive address registers
123 * Setups the receive address registers by setting the base receive address
124 * register to the devices MAC address and clearing all the other receive
125 * address registers to 0.
127 void igb_init_rx_addrs(struct e1000_hw
*hw
, u16 rar_count
)
130 u8 mac_addr
[ETH_ALEN
] = {0};
132 /* Setup the receive address */
133 hw_dbg("Programming MAC Address into RAR[0]\n");
135 hw
->mac
.ops
.rar_set(hw
, hw
->mac
.addr
, 0);
137 /* Zero out the other (rar_entry_count - 1) receive addresses */
138 hw_dbg("Clearing RAR[1-%u]\n", rar_count
-1);
139 for (i
= 1; i
< rar_count
; i
++)
140 hw
->mac
.ops
.rar_set(hw
, mac_addr
, i
);
144 * igb_find_vlvf_slot - find the VLAN id or the first empty slot
145 * @hw: pointer to hardware structure
146 * @vlan: VLAN id to write to VLAN filter
147 * @vlvf_bypass: skip VLVF if no match is found
149 * return the VLVF index where this VLAN id should be placed
152 static s32
igb_find_vlvf_slot(struct e1000_hw
*hw
, u32 vlan
, bool vlvf_bypass
)
154 s32 regindex
, first_empty_slot
;
157 /* short cut the special case */
161 /* if vlvf_bypass is set we don't want to use an empty slot, we
162 * will simply bypass the VLVF if there are no entries present in the
163 * VLVF that contain our VLAN
165 first_empty_slot
= vlvf_bypass
? -E1000_ERR_NO_SPACE
: 0;
167 /* Search for the VLAN id in the VLVF entries. Save off the first empty
168 * slot found along the way.
170 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
172 for (regindex
= E1000_VLVF_ARRAY_SIZE
; --regindex
> 0;) {
173 bits
= rd32(E1000_VLVF(regindex
)) & E1000_VLVF_VLANID_MASK
;
176 if (!first_empty_slot
&& !bits
)
177 first_empty_slot
= regindex
;
180 return first_empty_slot
? : -E1000_ERR_NO_SPACE
;
184 * igb_vfta_set - enable or disable vlan in VLAN filter table
185 * @hw: pointer to the HW structure
186 * @vlan: VLAN id to add or remove
187 * @vind: VMDq output index that maps queue to VLAN id
188 * @vlan_on: if true add filter, if false remove
190 * Sets or clears a bit in the VLAN filter table array based on VLAN id
191 * and if we are adding or removing the filter
193 s32
igb_vfta_set(struct e1000_hw
*hw
, u32 vlan
, u32 vind
,
194 bool vlan_on
, bool vlvf_bypass
)
196 struct igb_adapter
*adapter
= hw
->back
;
197 u32 regidx
, vfta_delta
, vfta
, bits
;
200 if ((vlan
> 4095) || (vind
> 7))
201 return -E1000_ERR_PARAM
;
203 /* this is a 2 part operation - first the VFTA, then the
204 * VLVF and VLVFB if VT Mode is set
205 * We don't write the VFTA until we know the VLVF part succeeded.
209 * The VFTA is a bitstring made up of 128 32-bit registers
210 * that enable the particular VLAN id, much like the MTA:
211 * bits[11-5]: which register
212 * bits[4-0]: which bit in the register
215 vfta_delta
= BIT(vlan
% 32);
216 vfta
= adapter
->shadow_vfta
[regidx
];
218 /* vfta_delta represents the difference between the current value
219 * of vfta and the value we want in the register. Since the diff
220 * is an XOR mask we can just update vfta using an XOR.
222 vfta_delta
&= vlan_on
? ~vfta
: vfta
;
228 * make sure the VLAN is in VLVF
229 * set the vind bit in the matching VLVFB
231 * clear the pool bit and possibly the vind
233 if (!adapter
->vfs_allocated_count
)
236 vlvf_index
= igb_find_vlvf_slot(hw
, vlan
, vlvf_bypass
);
237 if (vlvf_index
< 0) {
243 bits
= rd32(E1000_VLVF(vlvf_index
));
245 /* set the pool bit */
246 bits
|= BIT(E1000_VLVF_POOLSEL_SHIFT
+ vind
);
250 /* clear the pool bit */
251 bits
^= BIT(E1000_VLVF_POOLSEL_SHIFT
+ vind
);
253 if (!(bits
& E1000_VLVF_POOLSEL_MASK
)) {
254 /* Clear VFTA first, then disable VLVF. Otherwise
255 * we run the risk of stray packets leaking into
256 * the PF via the default pool
259 hw
->mac
.ops
.write_vfta(hw
, regidx
, vfta
);
261 /* disable VLVF and clear remaining bit from pool */
262 wr32(E1000_VLVF(vlvf_index
), 0);
267 /* If there are still bits set in the VLVFB registers
268 * for the VLAN ID indicated we need to see if the
269 * caller is requesting that we clear the VFTA entry bit.
270 * If the caller has requested that we clear the VFTA
271 * entry bit but there are still pools/VFs using this VLAN
272 * ID entry then ignore the request. We're not worried
273 * about the case where we're turning the VFTA VLAN ID
274 * entry bit on, only when requested to turn it off as
275 * there may be multiple pools and/or VFs using the
276 * VLAN ID entry. In that case we cannot clear the
277 * VFTA bit until all pools/VFs using that VLAN ID have also
278 * been cleared. This will be indicated by "bits" being
284 /* record pool change and enable VLAN ID if not already enabled */
285 wr32(E1000_VLVF(vlvf_index
), bits
| vlan
| E1000_VLVF_VLANID_ENABLE
);
288 /* bit was set/cleared before we started */
290 hw
->mac
.ops
.write_vfta(hw
, regidx
, vfta
);
296 * igb_check_alt_mac_addr - Check for alternate MAC addr
297 * @hw: pointer to the HW structure
299 * Checks the nvm for an alternate MAC address. An alternate MAC address
300 * can be setup by pre-boot software and must be treated like a permanent
301 * address and must override the actual permanent MAC address. If an
302 * alternate MAC address is found it is saved in the hw struct and
303 * programmed into RAR0 and the function returns success, otherwise the
304 * function returns an error.
306 s32
igb_check_alt_mac_addr(struct e1000_hw
*hw
)
310 u16 offset
, nvm_alt_mac_addr_offset
, nvm_data
;
311 u8 alt_mac_addr
[ETH_ALEN
];
313 /* Alternate MAC address is handled by the option ROM for 82580
314 * and newer. SW support not required.
316 if (hw
->mac
.type
>= e1000_82580
)
319 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ALT_MAC_ADDR_PTR
, 1,
320 &nvm_alt_mac_addr_offset
);
322 hw_dbg("NVM Read Error\n");
326 if ((nvm_alt_mac_addr_offset
== 0xFFFF) ||
327 (nvm_alt_mac_addr_offset
== 0x0000))
328 /* There is no Alternate MAC Address */
331 if (hw
->bus
.func
== E1000_FUNC_1
)
332 nvm_alt_mac_addr_offset
+= E1000_ALT_MAC_ADDRESS_OFFSET_LAN1
;
333 if (hw
->bus
.func
== E1000_FUNC_2
)
334 nvm_alt_mac_addr_offset
+= E1000_ALT_MAC_ADDRESS_OFFSET_LAN2
;
336 if (hw
->bus
.func
== E1000_FUNC_3
)
337 nvm_alt_mac_addr_offset
+= E1000_ALT_MAC_ADDRESS_OFFSET_LAN3
;
338 for (i
= 0; i
< ETH_ALEN
; i
+= 2) {
339 offset
= nvm_alt_mac_addr_offset
+ (i
>> 1);
340 ret_val
= hw
->nvm
.ops
.read(hw
, offset
, 1, &nvm_data
);
342 hw_dbg("NVM Read Error\n");
346 alt_mac_addr
[i
] = (u8
)(nvm_data
& 0xFF);
347 alt_mac_addr
[i
+ 1] = (u8
)(nvm_data
>> 8);
350 /* if multicast bit is set, the alternate address will not be used */
351 if (is_multicast_ether_addr(alt_mac_addr
)) {
352 hw_dbg("Ignoring Alternate Mac Address with MC bit set\n");
356 /* We have a valid alternate MAC address, and we want to treat it the
357 * same as the normal permanent MAC address stored by the HW into the
358 * RAR. Do this by mapping this address into RAR0.
360 hw
->mac
.ops
.rar_set(hw
, alt_mac_addr
, 0);
367 * igb_rar_set - Set receive address register
368 * @hw: pointer to the HW structure
369 * @addr: pointer to the receive address
370 * @index: receive address array register
372 * Sets the receive address array register at index to the address passed
375 void igb_rar_set(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
377 u32 rar_low
, rar_high
;
379 /* HW expects these in little endian so we reverse the byte order
380 * from network order (big endian) to little endian
382 rar_low
= ((u32
) addr
[0] |
383 ((u32
) addr
[1] << 8) |
384 ((u32
) addr
[2] << 16) | ((u32
) addr
[3] << 24));
386 rar_high
= ((u32
) addr
[4] | ((u32
) addr
[5] << 8));
388 /* If MAC address zero, no need to set the AV bit */
389 if (rar_low
|| rar_high
)
390 rar_high
|= E1000_RAH_AV
;
392 /* Some bridges will combine consecutive 32-bit writes into
393 * a single burst write, which will malfunction on some parts.
394 * The flushes avoid this.
396 wr32(E1000_RAL(index
), rar_low
);
398 wr32(E1000_RAH(index
), rar_high
);
403 * igb_mta_set - Set multicast filter table address
404 * @hw: pointer to the HW structure
405 * @hash_value: determines the MTA register and bit to set
407 * The multicast table address is a register array of 32-bit registers.
408 * The hash_value is used to determine what register the bit is in, the
409 * current value is read, the new bit is OR'd in and the new value is
410 * written back into the register.
412 void igb_mta_set(struct e1000_hw
*hw
, u32 hash_value
)
414 u32 hash_bit
, hash_reg
, mta
;
416 /* The MTA is a register array of 32-bit registers. It is
417 * treated like an array of (32*mta_reg_count) bits. We want to
418 * set bit BitArray[hash_value]. So we figure out what register
419 * the bit is in, read it, OR in the new bit, then write
420 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
421 * mask to bits 31:5 of the hash value which gives us the
422 * register we're modifying. The hash bit within that register
423 * is determined by the lower 5 bits of the hash value.
425 hash_reg
= (hash_value
>> 5) & (hw
->mac
.mta_reg_count
- 1);
426 hash_bit
= hash_value
& 0x1F;
428 mta
= array_rd32(E1000_MTA
, hash_reg
);
430 mta
|= BIT(hash_bit
);
432 array_wr32(E1000_MTA
, hash_reg
, mta
);
437 * igb_hash_mc_addr - Generate a multicast hash value
438 * @hw: pointer to the HW structure
439 * @mc_addr: pointer to a multicast address
441 * Generates a multicast address hash value which is used to determine
442 * the multicast filter table array address and new table value. See
445 static u32
igb_hash_mc_addr(struct e1000_hw
*hw
, u8
*mc_addr
)
447 u32 hash_value
, hash_mask
;
450 /* Register count multiplied by bits per register */
451 hash_mask
= (hw
->mac
.mta_reg_count
* 32) - 1;
453 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
454 * where 0xFF would still fall within the hash mask.
456 while (hash_mask
>> bit_shift
!= 0xFF)
459 /* The portion of the address that is used for the hash table
460 * is determined by the mc_filter_type setting.
461 * The algorithm is such that there is a total of 8 bits of shifting.
462 * The bit_shift for a mc_filter_type of 0 represents the number of
463 * left-shifts where the MSB of mc_addr[5] would still fall within
464 * the hash_mask. Case 0 does this exactly. Since there are a total
465 * of 8 bits of shifting, then mc_addr[4] will shift right the
466 * remaining number of bits. Thus 8 - bit_shift. The rest of the
467 * cases are a variation of this algorithm...essentially raising the
468 * number of bits to shift mc_addr[5] left, while still keeping the
469 * 8-bit shifting total.
471 * For example, given the following Destination MAC Address and an
472 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
473 * we can see that the bit_shift for case 0 is 4. These are the hash
474 * values resulting from each mc_filter_type...
475 * [0] [1] [2] [3] [4] [5]
479 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
480 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
481 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
482 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
484 switch (hw
->mac
.mc_filter_type
) {
499 hash_value
= hash_mask
& (((mc_addr
[4] >> (8 - bit_shift
)) |
500 (((u16
) mc_addr
[5]) << bit_shift
)));
506 * igb_update_mc_addr_list - Update Multicast addresses
507 * @hw: pointer to the HW structure
508 * @mc_addr_list: array of multicast addresses to program
509 * @mc_addr_count: number of multicast addresses to program
511 * Updates entire Multicast Table Array.
512 * The caller must have a packed mc_addr_list of multicast addresses.
514 void igb_update_mc_addr_list(struct e1000_hw
*hw
,
515 u8
*mc_addr_list
, u32 mc_addr_count
)
517 u32 hash_value
, hash_bit
, hash_reg
;
520 /* clear mta_shadow */
521 memset(&hw
->mac
.mta_shadow
, 0, sizeof(hw
->mac
.mta_shadow
));
523 /* update mta_shadow from mc_addr_list */
524 for (i
= 0; (u32
) i
< mc_addr_count
; i
++) {
525 hash_value
= igb_hash_mc_addr(hw
, mc_addr_list
);
527 hash_reg
= (hash_value
>> 5) & (hw
->mac
.mta_reg_count
- 1);
528 hash_bit
= hash_value
& 0x1F;
530 hw
->mac
.mta_shadow
[hash_reg
] |= BIT(hash_bit
);
531 mc_addr_list
+= (ETH_ALEN
);
534 /* replace the entire MTA table */
535 for (i
= hw
->mac
.mta_reg_count
- 1; i
>= 0; i
--)
536 array_wr32(E1000_MTA
, i
, hw
->mac
.mta_shadow
[i
]);
541 * igb_clear_hw_cntrs_base - Clear base hardware counters
542 * @hw: pointer to the HW structure
544 * Clears the base hardware counters by reading the counter registers.
546 void igb_clear_hw_cntrs_base(struct e1000_hw
*hw
)
588 * igb_check_for_copper_link - Check for link (Copper)
589 * @hw: pointer to the HW structure
591 * Checks to see of the link status of the hardware has changed. If a
592 * change in link status has been detected, then we read the PHY registers
593 * to get the current speed/duplex if link exists.
595 s32
igb_check_for_copper_link(struct e1000_hw
*hw
)
597 struct e1000_mac_info
*mac
= &hw
->mac
;
601 /* We only want to go out to the PHY registers to see if Auto-Neg
602 * has completed and/or if our link status has changed. The
603 * get_link_status flag is set upon receiving a Link Status
604 * Change or Rx Sequence Error interrupt.
606 if (!mac
->get_link_status
) {
611 /* First we want to see if the MII Status Register reports
612 * link. If so, then we want to get the current speed/duplex
615 ret_val
= igb_phy_has_link(hw
, 1, 0, &link
);
620 goto out
; /* No link detected */
622 mac
->get_link_status
= false;
624 /* Check if there was DownShift, must be checked
625 * immediately after link-up
627 igb_check_downshift(hw
);
629 /* If we are forcing speed/duplex, then we simply return since
630 * we have already determined whether we have link or not.
633 ret_val
= -E1000_ERR_CONFIG
;
637 /* Auto-Neg is enabled. Auto Speed Detection takes care
638 * of MAC speed/duplex configuration. So we only need to
639 * configure Collision Distance in the MAC.
641 igb_config_collision_dist(hw
);
643 /* Configure Flow Control now that Auto-Neg has completed.
644 * First, we need to restore the desired flow control
645 * settings because we may have had to re-autoneg with a
646 * different link partner.
648 ret_val
= igb_config_fc_after_link_up(hw
);
650 hw_dbg("Error configuring flow control\n");
657 * igb_setup_link - Setup flow control and link settings
658 * @hw: pointer to the HW structure
660 * Determines which flow control settings to use, then configures flow
661 * control. Calls the appropriate media-specific link configuration
662 * function. Assuming the adapter has a valid link partner, a valid link
663 * should be established. Assumes the hardware has previously been reset
664 * and the transmitter and receiver are not enabled.
666 s32
igb_setup_link(struct e1000_hw
*hw
)
670 /* In the case of the phy reset being blocked, we already have a link.
671 * We do not need to set it up again.
673 if (igb_check_reset_block(hw
))
676 /* If requested flow control is set to default, set flow control
677 * based on the EEPROM flow control settings.
679 if (hw
->fc
.requested_mode
== e1000_fc_default
) {
680 ret_val
= igb_set_default_fc(hw
);
685 /* We want to save off the original Flow Control configuration just
686 * in case we get disconnected and then reconnected into a different
687 * hub or switch with different Flow Control capabilities.
689 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
691 hw_dbg("After fix-ups FlowControl is now = %x\n", hw
->fc
.current_mode
);
693 /* Call the necessary media_type subroutine to configure the link. */
694 ret_val
= hw
->mac
.ops
.setup_physical_interface(hw
);
698 /* Initialize the flow control address, type, and PAUSE timer
699 * registers to their default values. This is done even if flow
700 * control is disabled, because it does not hurt anything to
701 * initialize these registers.
703 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
704 wr32(E1000_FCT
, FLOW_CONTROL_TYPE
);
705 wr32(E1000_FCAH
, FLOW_CONTROL_ADDRESS_HIGH
);
706 wr32(E1000_FCAL
, FLOW_CONTROL_ADDRESS_LOW
);
708 wr32(E1000_FCTTV
, hw
->fc
.pause_time
);
710 ret_val
= igb_set_fc_watermarks(hw
);
718 * igb_config_collision_dist - Configure collision distance
719 * @hw: pointer to the HW structure
721 * Configures the collision distance to the default value and is used
722 * during link setup. Currently no func pointer exists and all
723 * implementations are handled in the generic version of this function.
725 void igb_config_collision_dist(struct e1000_hw
*hw
)
729 tctl
= rd32(E1000_TCTL
);
731 tctl
&= ~E1000_TCTL_COLD
;
732 tctl
|= E1000_COLLISION_DISTANCE
<< E1000_COLD_SHIFT
;
734 wr32(E1000_TCTL
, tctl
);
739 * igb_set_fc_watermarks - Set flow control high/low watermarks
740 * @hw: pointer to the HW structure
742 * Sets the flow control high/low threshold (watermark) registers. If
743 * flow control XON frame transmission is enabled, then set XON frame
744 * tansmission as well.
746 static s32
igb_set_fc_watermarks(struct e1000_hw
*hw
)
749 u32 fcrtl
= 0, fcrth
= 0;
751 /* Set the flow control receive threshold registers. Normally,
752 * these registers will be set to a default threshold that may be
753 * adjusted later by the driver's runtime code. However, if the
754 * ability to transmit pause frames is not enabled, then these
755 * registers will be set to 0.
757 if (hw
->fc
.current_mode
& e1000_fc_tx_pause
) {
758 /* We need to set up the Receive Threshold high and low water
759 * marks as well as (optionally) enabling the transmission of
762 fcrtl
= hw
->fc
.low_water
;
764 fcrtl
|= E1000_FCRTL_XONE
;
766 fcrth
= hw
->fc
.high_water
;
768 wr32(E1000_FCRTL
, fcrtl
);
769 wr32(E1000_FCRTH
, fcrth
);
775 * igb_set_default_fc - Set flow control default values
776 * @hw: pointer to the HW structure
778 * Read the EEPROM for the default values for flow control and store the
781 static s32
igb_set_default_fc(struct e1000_hw
*hw
)
787 /* Read and store word 0x0F of the EEPROM. This word contains bits
788 * that determine the hardware's default PAUSE (flow control) mode,
789 * a bit that determines whether the HW defaults to enabling or
790 * disabling auto-negotiation, and the direction of the
791 * SW defined pins. If there is no SW over-ride of the flow
792 * control setting, then the variable hw->fc will
793 * be initialized based on a value in the EEPROM.
795 if (hw
->mac
.type
== e1000_i350
)
796 lan_offset
= NVM_82580_LAN_FUNC_OFFSET(hw
->bus
.func
);
800 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL2_REG
+ lan_offset
,
803 hw_dbg("NVM Read Error\n");
807 if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) == 0)
808 hw
->fc
.requested_mode
= e1000_fc_none
;
809 else if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) == NVM_WORD0F_ASM_DIR
)
810 hw
->fc
.requested_mode
= e1000_fc_tx_pause
;
812 hw
->fc
.requested_mode
= e1000_fc_full
;
819 * igb_force_mac_fc - Force the MAC's flow control settings
820 * @hw: pointer to the HW structure
822 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
823 * device control register to reflect the adapter settings. TFCE and RFCE
824 * need to be explicitly set by software when a copper PHY is used because
825 * autonegotiation is managed by the PHY rather than the MAC. Software must
826 * also configure these bits when link is forced on a fiber connection.
828 s32
igb_force_mac_fc(struct e1000_hw
*hw
)
833 ctrl
= rd32(E1000_CTRL
);
835 /* Because we didn't get link via the internal auto-negotiation
836 * mechanism (we either forced link or we got link via PHY
837 * auto-neg), we have to manually enable/disable transmit an
838 * receive flow control.
840 * The "Case" statement below enables/disable flow control
841 * according to the "hw->fc.current_mode" parameter.
843 * The possible values of the "fc" parameter are:
844 * 0: Flow control is completely disabled
845 * 1: Rx flow control is enabled (we can receive pause
846 * frames but not send pause frames).
847 * 2: Tx flow control is enabled (we can send pause frames
848 * frames but we do not receive pause frames).
849 * 3: Both Rx and TX flow control (symmetric) is enabled.
850 * other: No other values should be possible at this point.
852 hw_dbg("hw->fc.current_mode = %u\n", hw
->fc
.current_mode
);
854 switch (hw
->fc
.current_mode
) {
856 ctrl
&= (~(E1000_CTRL_TFCE
| E1000_CTRL_RFCE
));
858 case e1000_fc_rx_pause
:
859 ctrl
&= (~E1000_CTRL_TFCE
);
860 ctrl
|= E1000_CTRL_RFCE
;
862 case e1000_fc_tx_pause
:
863 ctrl
&= (~E1000_CTRL_RFCE
);
864 ctrl
|= E1000_CTRL_TFCE
;
867 ctrl
|= (E1000_CTRL_TFCE
| E1000_CTRL_RFCE
);
870 hw_dbg("Flow control param set incorrectly\n");
871 ret_val
= -E1000_ERR_CONFIG
;
875 wr32(E1000_CTRL
, ctrl
);
882 * igb_config_fc_after_link_up - Configures flow control after link
883 * @hw: pointer to the HW structure
885 * Checks the status of auto-negotiation after link up to ensure that the
886 * speed and duplex were not forced. If the link needed to be forced, then
887 * flow control needs to be forced also. If auto-negotiation is enabled
888 * and did not fail, then we configure flow control based on our link
891 s32
igb_config_fc_after_link_up(struct e1000_hw
*hw
)
893 struct e1000_mac_info
*mac
= &hw
->mac
;
895 u32 pcs_status_reg
, pcs_adv_reg
, pcs_lp_ability_reg
, pcs_ctrl_reg
;
896 u16 mii_status_reg
, mii_nway_adv_reg
, mii_nway_lp_ability_reg
;
899 /* Check for the case where we have fiber media and auto-neg failed
900 * so we had to force link. In this case, we need to force the
901 * configuration of the MAC to match the "fc" parameter.
903 if (mac
->autoneg_failed
) {
904 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
905 ret_val
= igb_force_mac_fc(hw
);
907 if (hw
->phy
.media_type
== e1000_media_type_copper
)
908 ret_val
= igb_force_mac_fc(hw
);
912 hw_dbg("Error forcing flow control settings\n");
916 /* Check for the case where we have copper media and auto-neg is
917 * enabled. In this case, we need to check and see if Auto-Neg
918 * has completed, and if so, how the PHY and link partner has
919 * flow control configured.
921 if ((hw
->phy
.media_type
== e1000_media_type_copper
) && mac
->autoneg
) {
922 /* Read the MII Status Register and check to see if AutoNeg
923 * has completed. We read this twice because this reg has
924 * some "sticky" (latched) bits.
926 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
,
930 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
,
935 if (!(mii_status_reg
& MII_SR_AUTONEG_COMPLETE
)) {
936 hw_dbg("Copper PHY and Auto Neg has not completed.\n");
940 /* The AutoNeg process has completed, so we now need to
941 * read both the Auto Negotiation Advertisement
942 * Register (Address 4) and the Auto_Negotiation Base
943 * Page Ability Register (Address 5) to determine how
944 * flow control was negotiated.
946 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_AUTONEG_ADV
,
950 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_LP_ABILITY
,
951 &mii_nway_lp_ability_reg
);
955 /* Two bits in the Auto Negotiation Advertisement Register
956 * (Address 4) and two bits in the Auto Negotiation Base
957 * Page Ability Register (Address 5) determine flow control
958 * for both the PHY and the link partner. The following
959 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
960 * 1999, describes these PAUSE resolution bits and how flow
961 * control is determined based upon these settings.
962 * NOTE: DC = Don't Care
964 * LOCAL DEVICE | LINK PARTNER
965 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
966 *-------|---------|-------|---------|--------------------
967 * 0 | 0 | DC | DC | e1000_fc_none
968 * 0 | 1 | 0 | DC | e1000_fc_none
969 * 0 | 1 | 1 | 0 | e1000_fc_none
970 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
971 * 1 | 0 | 0 | DC | e1000_fc_none
972 * 1 | DC | 1 | DC | e1000_fc_full
973 * 1 | 1 | 0 | 0 | e1000_fc_none
974 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
976 * Are both PAUSE bits set to 1? If so, this implies
977 * Symmetric Flow Control is enabled at both ends. The
978 * ASM_DIR bits are irrelevant per the spec.
980 * For Symmetric Flow Control:
982 * LOCAL DEVICE | LINK PARTNER
983 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
984 *-------|---------|-------|---------|--------------------
985 * 1 | DC | 1 | DC | E1000_fc_full
988 if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
989 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
)) {
990 /* Now we need to check if the user selected RX ONLY
991 * of pause frames. In this case, we had to advertise
992 * FULL flow control because we could not advertise RX
993 * ONLY. Hence, we must now check to see if we need to
994 * turn OFF the TRANSMISSION of PAUSE frames.
996 if (hw
->fc
.requested_mode
== e1000_fc_full
) {
997 hw
->fc
.current_mode
= e1000_fc_full
;
998 hw_dbg("Flow Control = FULL.\n");
1000 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
1001 hw_dbg("Flow Control = RX PAUSE frames only.\n");
1004 /* For receiving PAUSE frames ONLY.
1006 * LOCAL DEVICE | LINK PARTNER
1007 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1008 *-------|---------|-------|---------|--------------------
1009 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1011 else if (!(mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
1012 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
1013 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
1014 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
1015 hw
->fc
.current_mode
= e1000_fc_tx_pause
;
1016 hw_dbg("Flow Control = TX PAUSE frames only.\n");
1018 /* For transmitting PAUSE frames ONLY.
1020 * LOCAL DEVICE | LINK PARTNER
1021 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1022 *-------|---------|-------|---------|--------------------
1023 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1025 else if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
1026 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
1027 !(mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
1028 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
1029 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
1030 hw_dbg("Flow Control = RX PAUSE frames only.\n");
1032 /* Per the IEEE spec, at this point flow control should be
1033 * disabled. However, we want to consider that we could
1034 * be connected to a legacy switch that doesn't advertise
1035 * desired flow control, but can be forced on the link
1036 * partner. So if we advertised no flow control, that is
1037 * what we will resolve to. If we advertised some kind of
1038 * receive capability (Rx Pause Only or Full Flow Control)
1039 * and the link partner advertised none, we will configure
1040 * ourselves to enable Rx Flow Control only. We can do
1041 * this safely for two reasons: If the link partner really
1042 * didn't want flow control enabled, and we enable Rx, no
1043 * harm done since we won't be receiving any PAUSE frames
1044 * anyway. If the intent on the link partner was to have
1045 * flow control enabled, then by us enabling RX only, we
1046 * can at least receive pause frames and process them.
1047 * This is a good idea because in most cases, since we are
1048 * predominantly a server NIC, more times than not we will
1049 * be asked to delay transmission of packets than asking
1050 * our link partner to pause transmission of frames.
1052 else if ((hw
->fc
.requested_mode
== e1000_fc_none
) ||
1053 (hw
->fc
.requested_mode
== e1000_fc_tx_pause
) ||
1054 (hw
->fc
.strict_ieee
)) {
1055 hw
->fc
.current_mode
= e1000_fc_none
;
1056 hw_dbg("Flow Control = NONE.\n");
1058 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
1059 hw_dbg("Flow Control = RX PAUSE frames only.\n");
1062 /* Now we need to do one last check... If we auto-
1063 * negotiated to HALF DUPLEX, flow control should not be
1064 * enabled per IEEE 802.3 spec.
1066 ret_val
= hw
->mac
.ops
.get_speed_and_duplex(hw
, &speed
, &duplex
);
1068 hw_dbg("Error getting link speed and duplex\n");
1072 if (duplex
== HALF_DUPLEX
)
1073 hw
->fc
.current_mode
= e1000_fc_none
;
1075 /* Now we call a subroutine to actually force the MAC
1076 * controller to use the correct flow control settings.
1078 ret_val
= igb_force_mac_fc(hw
);
1080 hw_dbg("Error forcing flow control settings\n");
1084 /* Check for the case where we have SerDes media and auto-neg is
1085 * enabled. In this case, we need to check and see if Auto-Neg
1086 * has completed, and if so, how the PHY and link partner has
1087 * flow control configured.
1089 if ((hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
1091 /* Read the PCS_LSTS and check to see if AutoNeg
1094 pcs_status_reg
= rd32(E1000_PCS_LSTAT
);
1096 if (!(pcs_status_reg
& E1000_PCS_LSTS_AN_COMPLETE
)) {
1097 hw_dbg("PCS Auto Neg has not completed.\n");
1101 /* The AutoNeg process has completed, so we now need to
1102 * read both the Auto Negotiation Advertisement
1103 * Register (PCS_ANADV) and the Auto_Negotiation Base
1104 * Page Ability Register (PCS_LPAB) to determine how
1105 * flow control was negotiated.
1107 pcs_adv_reg
= rd32(E1000_PCS_ANADV
);
1108 pcs_lp_ability_reg
= rd32(E1000_PCS_LPAB
);
1110 /* Two bits in the Auto Negotiation Advertisement Register
1111 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1112 * Page Ability Register (PCS_LPAB) determine flow control
1113 * for both the PHY and the link partner. The following
1114 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1115 * 1999, describes these PAUSE resolution bits and how flow
1116 * control is determined based upon these settings.
1117 * NOTE: DC = Don't Care
1119 * LOCAL DEVICE | LINK PARTNER
1120 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1121 *-------|---------|-------|---------|--------------------
1122 * 0 | 0 | DC | DC | e1000_fc_none
1123 * 0 | 1 | 0 | DC | e1000_fc_none
1124 * 0 | 1 | 1 | 0 | e1000_fc_none
1125 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1126 * 1 | 0 | 0 | DC | e1000_fc_none
1127 * 1 | DC | 1 | DC | e1000_fc_full
1128 * 1 | 1 | 0 | 0 | e1000_fc_none
1129 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1131 * Are both PAUSE bits set to 1? If so, this implies
1132 * Symmetric Flow Control is enabled at both ends. The
1133 * ASM_DIR bits are irrelevant per the spec.
1135 * For Symmetric Flow Control:
1137 * LOCAL DEVICE | LINK PARTNER
1138 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1139 *-------|---------|-------|---------|--------------------
1140 * 1 | DC | 1 | DC | e1000_fc_full
1143 if ((pcs_adv_reg
& E1000_TXCW_PAUSE
) &&
1144 (pcs_lp_ability_reg
& E1000_TXCW_PAUSE
)) {
1145 /* Now we need to check if the user selected Rx ONLY
1146 * of pause frames. In this case, we had to advertise
1147 * FULL flow control because we could not advertise Rx
1148 * ONLY. Hence, we must now check to see if we need to
1149 * turn OFF the TRANSMISSION of PAUSE frames.
1151 if (hw
->fc
.requested_mode
== e1000_fc_full
) {
1152 hw
->fc
.current_mode
= e1000_fc_full
;
1153 hw_dbg("Flow Control = FULL.\n");
1155 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
1156 hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1159 /* For receiving PAUSE frames ONLY.
1161 * LOCAL DEVICE | LINK PARTNER
1162 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1163 *-------|---------|-------|---------|--------------------
1164 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1166 else if (!(pcs_adv_reg
& E1000_TXCW_PAUSE
) &&
1167 (pcs_adv_reg
& E1000_TXCW_ASM_DIR
) &&
1168 (pcs_lp_ability_reg
& E1000_TXCW_PAUSE
) &&
1169 (pcs_lp_ability_reg
& E1000_TXCW_ASM_DIR
)) {
1170 hw
->fc
.current_mode
= e1000_fc_tx_pause
;
1171 hw_dbg("Flow Control = Tx PAUSE frames only.\n");
1173 /* For transmitting PAUSE frames ONLY.
1175 * LOCAL DEVICE | LINK PARTNER
1176 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1177 *-------|---------|-------|---------|--------------------
1178 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1180 else if ((pcs_adv_reg
& E1000_TXCW_PAUSE
) &&
1181 (pcs_adv_reg
& E1000_TXCW_ASM_DIR
) &&
1182 !(pcs_lp_ability_reg
& E1000_TXCW_PAUSE
) &&
1183 (pcs_lp_ability_reg
& E1000_TXCW_ASM_DIR
)) {
1184 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
1185 hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1187 /* Per the IEEE spec, at this point flow control
1188 * should be disabled.
1190 hw
->fc
.current_mode
= e1000_fc_none
;
1191 hw_dbg("Flow Control = NONE.\n");
1194 /* Now we call a subroutine to actually force the MAC
1195 * controller to use the correct flow control settings.
1197 pcs_ctrl_reg
= rd32(E1000_PCS_LCTL
);
1198 pcs_ctrl_reg
|= E1000_PCS_LCTL_FORCE_FCTRL
;
1199 wr32(E1000_PCS_LCTL
, pcs_ctrl_reg
);
1201 ret_val
= igb_force_mac_fc(hw
);
1203 hw_dbg("Error forcing flow control settings\n");
1213 * igb_get_speed_and_duplex_copper - Retrieve current speed/duplex
1214 * @hw: pointer to the HW structure
1215 * @speed: stores the current speed
1216 * @duplex: stores the current duplex
1218 * Read the status register for the current speed/duplex and store the current
1219 * speed and duplex for copper connections.
1221 s32
igb_get_speed_and_duplex_copper(struct e1000_hw
*hw
, u16
*speed
,
1226 status
= rd32(E1000_STATUS
);
1227 if (status
& E1000_STATUS_SPEED_1000
) {
1228 *speed
= SPEED_1000
;
1229 hw_dbg("1000 Mbs, ");
1230 } else if (status
& E1000_STATUS_SPEED_100
) {
1232 hw_dbg("100 Mbs, ");
1238 if (status
& E1000_STATUS_FD
) {
1239 *duplex
= FULL_DUPLEX
;
1240 hw_dbg("Full Duplex\n");
1242 *duplex
= HALF_DUPLEX
;
1243 hw_dbg("Half Duplex\n");
1250 * igb_get_hw_semaphore - Acquire hardware semaphore
1251 * @hw: pointer to the HW structure
1253 * Acquire the HW semaphore to access the PHY or NVM
1255 s32
igb_get_hw_semaphore(struct e1000_hw
*hw
)
1259 s32 timeout
= hw
->nvm
.word_size
+ 1;
1262 /* Get the SW semaphore */
1263 while (i
< timeout
) {
1264 swsm
= rd32(E1000_SWSM
);
1265 if (!(swsm
& E1000_SWSM_SMBI
))
1273 hw_dbg("Driver can't access device - SMBI bit is set.\n");
1274 ret_val
= -E1000_ERR_NVM
;
1278 /* Get the FW semaphore. */
1279 for (i
= 0; i
< timeout
; i
++) {
1280 swsm
= rd32(E1000_SWSM
);
1281 wr32(E1000_SWSM
, swsm
| E1000_SWSM_SWESMBI
);
1283 /* Semaphore acquired if bit latched */
1284 if (rd32(E1000_SWSM
) & E1000_SWSM_SWESMBI
)
1291 /* Release semaphores */
1292 igb_put_hw_semaphore(hw
);
1293 hw_dbg("Driver can't access the NVM\n");
1294 ret_val
= -E1000_ERR_NVM
;
1303 * igb_put_hw_semaphore - Release hardware semaphore
1304 * @hw: pointer to the HW structure
1306 * Release hardware semaphore used to access the PHY or NVM
1308 void igb_put_hw_semaphore(struct e1000_hw
*hw
)
1312 swsm
= rd32(E1000_SWSM
);
1314 swsm
&= ~(E1000_SWSM_SMBI
| E1000_SWSM_SWESMBI
);
1316 wr32(E1000_SWSM
, swsm
);
1320 * igb_get_auto_rd_done - Check for auto read completion
1321 * @hw: pointer to the HW structure
1323 * Check EEPROM for Auto Read done bit.
1325 s32
igb_get_auto_rd_done(struct e1000_hw
*hw
)
1331 while (i
< AUTO_READ_DONE_TIMEOUT
) {
1332 if (rd32(E1000_EECD
) & E1000_EECD_AUTO_RD
)
1334 usleep_range(1000, 2000);
1338 if (i
== AUTO_READ_DONE_TIMEOUT
) {
1339 hw_dbg("Auto read by HW from NVM has not completed.\n");
1340 ret_val
= -E1000_ERR_RESET
;
1349 * igb_valid_led_default - Verify a valid default LED config
1350 * @hw: pointer to the HW structure
1351 * @data: pointer to the NVM (EEPROM)
1353 * Read the EEPROM for the current default LED configuration. If the
1354 * LED configuration is not valid, set to a valid LED configuration.
1356 static s32
igb_valid_led_default(struct e1000_hw
*hw
, u16
*data
)
1360 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1362 hw_dbg("NVM Read Error\n");
1366 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
) {
1367 switch (hw
->phy
.media_type
) {
1368 case e1000_media_type_internal_serdes
:
1369 *data
= ID_LED_DEFAULT_82575_SERDES
;
1371 case e1000_media_type_copper
:
1373 *data
= ID_LED_DEFAULT
;
1383 * @hw: pointer to the HW structure
1386 s32
igb_id_led_init(struct e1000_hw
*hw
)
1388 struct e1000_mac_info
*mac
= &hw
->mac
;
1390 const u32 ledctl_mask
= 0x000000FF;
1391 const u32 ledctl_on
= E1000_LEDCTL_MODE_LED_ON
;
1392 const u32 ledctl_off
= E1000_LEDCTL_MODE_LED_OFF
;
1394 const u16 led_mask
= 0x0F;
1396 /* i210 and i211 devices have different LED mechanism */
1397 if ((hw
->mac
.type
== e1000_i210
) ||
1398 (hw
->mac
.type
== e1000_i211
))
1399 ret_val
= igb_valid_led_default_i210(hw
, &data
);
1401 ret_val
= igb_valid_led_default(hw
, &data
);
1406 mac
->ledctl_default
= rd32(E1000_LEDCTL
);
1407 mac
->ledctl_mode1
= mac
->ledctl_default
;
1408 mac
->ledctl_mode2
= mac
->ledctl_default
;
1410 for (i
= 0; i
< 4; i
++) {
1411 temp
= (data
>> (i
<< 2)) & led_mask
;
1413 case ID_LED_ON1_DEF2
:
1414 case ID_LED_ON1_ON2
:
1415 case ID_LED_ON1_OFF2
:
1416 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1417 mac
->ledctl_mode1
|= ledctl_on
<< (i
<< 3);
1419 case ID_LED_OFF1_DEF2
:
1420 case ID_LED_OFF1_ON2
:
1421 case ID_LED_OFF1_OFF2
:
1422 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1423 mac
->ledctl_mode1
|= ledctl_off
<< (i
<< 3);
1430 case ID_LED_DEF1_ON2
:
1431 case ID_LED_ON1_ON2
:
1432 case ID_LED_OFF1_ON2
:
1433 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1434 mac
->ledctl_mode2
|= ledctl_on
<< (i
<< 3);
1436 case ID_LED_DEF1_OFF2
:
1437 case ID_LED_ON1_OFF2
:
1438 case ID_LED_OFF1_OFF2
:
1439 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1440 mac
->ledctl_mode2
|= ledctl_off
<< (i
<< 3);
1453 * igb_cleanup_led - Set LED config to default operation
1454 * @hw: pointer to the HW structure
1456 * Remove the current LED configuration and set the LED configuration
1457 * to the default value, saved from the EEPROM.
1459 s32
igb_cleanup_led(struct e1000_hw
*hw
)
1461 wr32(E1000_LEDCTL
, hw
->mac
.ledctl_default
);
1466 * igb_blink_led - Blink LED
1467 * @hw: pointer to the HW structure
1469 * Blink the led's which are set to be on.
1471 s32
igb_blink_led(struct e1000_hw
*hw
)
1473 u32 ledctl_blink
= 0;
1476 if (hw
->phy
.media_type
== e1000_media_type_fiber
) {
1477 /* always blink LED0 for PCI-E fiber */
1478 ledctl_blink
= E1000_LEDCTL_LED0_BLINK
|
1479 (E1000_LEDCTL_MODE_LED_ON
<< E1000_LEDCTL_LED0_MODE_SHIFT
);
1481 /* Set the blink bit for each LED that's "on" (0x0E)
1482 * (or "off" if inverted) in ledctl_mode2. The blink
1483 * logic in hardware only works when mode is set to "on"
1484 * so it must be changed accordingly when the mode is
1485 * "off" and inverted.
1487 ledctl_blink
= hw
->mac
.ledctl_mode2
;
1488 for (i
= 0; i
< 32; i
+= 8) {
1489 u32 mode
= (hw
->mac
.ledctl_mode2
>> i
) &
1490 E1000_LEDCTL_LED0_MODE_MASK
;
1491 u32 led_default
= hw
->mac
.ledctl_default
>> i
;
1493 if ((!(led_default
& E1000_LEDCTL_LED0_IVRT
) &&
1494 (mode
== E1000_LEDCTL_MODE_LED_ON
)) ||
1495 ((led_default
& E1000_LEDCTL_LED0_IVRT
) &&
1496 (mode
== E1000_LEDCTL_MODE_LED_OFF
))) {
1498 ~(E1000_LEDCTL_LED0_MODE_MASK
<< i
);
1499 ledctl_blink
|= (E1000_LEDCTL_LED0_BLINK
|
1500 E1000_LEDCTL_MODE_LED_ON
) << i
;
1505 wr32(E1000_LEDCTL
, ledctl_blink
);
1511 * igb_led_off - Turn LED off
1512 * @hw: pointer to the HW structure
1516 s32
igb_led_off(struct e1000_hw
*hw
)
1518 switch (hw
->phy
.media_type
) {
1519 case e1000_media_type_copper
:
1520 wr32(E1000_LEDCTL
, hw
->mac
.ledctl_mode1
);
1530 * igb_disable_pcie_master - Disables PCI-express master access
1531 * @hw: pointer to the HW structure
1533 * Returns 0 (0) if successful, else returns -10
1534 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1535 * the master requests to be disabled.
1537 * Disables PCI-Express master access and verifies there are no pending
1540 s32
igb_disable_pcie_master(struct e1000_hw
*hw
)
1543 s32 timeout
= MASTER_DISABLE_TIMEOUT
;
1546 if (hw
->bus
.type
!= e1000_bus_type_pci_express
)
1549 ctrl
= rd32(E1000_CTRL
);
1550 ctrl
|= E1000_CTRL_GIO_MASTER_DISABLE
;
1551 wr32(E1000_CTRL
, ctrl
);
1554 if (!(rd32(E1000_STATUS
) &
1555 E1000_STATUS_GIO_MASTER_ENABLE
))
1562 hw_dbg("Master requests are pending.\n");
1563 ret_val
= -E1000_ERR_MASTER_REQUESTS_PENDING
;
1572 * igb_validate_mdi_setting - Verify MDI/MDIx settings
1573 * @hw: pointer to the HW structure
1575 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1576 * set, which is forced to MDI mode only.
1578 s32
igb_validate_mdi_setting(struct e1000_hw
*hw
)
1582 /* All MDI settings are supported on 82580 and newer. */
1583 if (hw
->mac
.type
>= e1000_82580
)
1586 if (!hw
->mac
.autoneg
&& (hw
->phy
.mdix
== 0 || hw
->phy
.mdix
== 3)) {
1587 hw_dbg("Invalid MDI setting detected\n");
1589 ret_val
= -E1000_ERR_CONFIG
;
1598 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1599 * @hw: pointer to the HW structure
1600 * @reg: 32bit register offset such as E1000_SCTL
1601 * @offset: register offset to write to
1602 * @data: data to write at register offset
1604 * Writes an address/data control type register. There are several of these
1605 * and they all have the format address << 8 | data and bit 31 is polled for
1608 s32
igb_write_8bit_ctrl_reg(struct e1000_hw
*hw
, u32 reg
,
1609 u32 offset
, u8 data
)
1611 u32 i
, regvalue
= 0;
1614 /* Set up the address and data */
1615 regvalue
= ((u32
)data
) | (offset
<< E1000_GEN_CTL_ADDRESS_SHIFT
);
1616 wr32(reg
, regvalue
);
1618 /* Poll the ready bit to see if the MDI read completed */
1619 for (i
= 0; i
< E1000_GEN_POLL_TIMEOUT
; i
++) {
1621 regvalue
= rd32(reg
);
1622 if (regvalue
& E1000_GEN_CTL_READY
)
1625 if (!(regvalue
& E1000_GEN_CTL_READY
)) {
1626 hw_dbg("Reg %08x did not indicate ready\n", reg
);
1627 ret_val
= -E1000_ERR_PHY
;
1636 * igb_enable_mng_pass_thru - Enable processing of ARP's
1637 * @hw: pointer to the HW structure
1639 * Verifies the hardware needs to leave interface enabled so that frames can
1640 * be directed to and from the management interface.
1642 bool igb_enable_mng_pass_thru(struct e1000_hw
*hw
)
1646 bool ret_val
= false;
1648 if (!hw
->mac
.asf_firmware_present
)
1651 manc
= rd32(E1000_MANC
);
1653 if (!(manc
& E1000_MANC_RCV_TCO_EN
))
1656 if (hw
->mac
.arc_subsystem_valid
) {
1657 fwsm
= rd32(E1000_FWSM
);
1658 factps
= rd32(E1000_FACTPS
);
1660 if (!(factps
& E1000_FACTPS_MNGCG
) &&
1661 ((fwsm
& E1000_FWSM_MODE_MASK
) ==
1662 (e1000_mng_mode_pt
<< E1000_FWSM_MODE_SHIFT
))) {
1667 if ((manc
& E1000_MANC_SMBUS_EN
) &&
1668 !(manc
& E1000_MANC_ASF_EN
)) {