Linux 4.16.11
[linux/fpc-iii.git] / drivers / net / ethernet / jme.c
blob8a165842fa8558123e611507cd39a00d9c534f86
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/pci-aspm.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/crc32.h>
36 #include <linux/delay.h>
37 #include <linux/spinlock.h>
38 #include <linux/in.h>
39 #include <linux/ip.h>
40 #include <linux/ipv6.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/if_vlan.h>
44 #include <linux/slab.h>
45 #include <net/ip6_checksum.h>
46 #include "jme.h"
48 static int force_pseudohp = -1;
49 static int no_pseudohp = -1;
50 static int no_extplug = -1;
51 module_param(force_pseudohp, int, 0);
52 MODULE_PARM_DESC(force_pseudohp,
53 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
54 module_param(no_pseudohp, int, 0);
55 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
56 module_param(no_extplug, int, 0);
57 MODULE_PARM_DESC(no_extplug,
58 "Do not use external plug signal for pseudo hot-plug.");
60 static int
61 jme_mdio_read(struct net_device *netdev, int phy, int reg)
63 struct jme_adapter *jme = netdev_priv(netdev);
64 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
66 read_again:
67 jwrite32(jme, JME_SMI, SMI_OP_REQ |
68 smi_phy_addr(phy) |
69 smi_reg_addr(reg));
71 wmb();
72 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
73 udelay(20);
74 val = jread32(jme, JME_SMI);
75 if ((val & SMI_OP_REQ) == 0)
76 break;
79 if (i == 0) {
80 pr_err("phy(%d) read timeout : %d\n", phy, reg);
81 return 0;
84 if (again--)
85 goto read_again;
87 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
90 static void
91 jme_mdio_write(struct net_device *netdev,
92 int phy, int reg, int val)
94 struct jme_adapter *jme = netdev_priv(netdev);
95 int i;
97 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
98 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
99 smi_phy_addr(phy) | smi_reg_addr(reg));
101 wmb();
102 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
103 udelay(20);
104 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
105 break;
108 if (i == 0)
109 pr_err("phy(%d) write timeout : %d\n", phy, reg);
112 static inline void
113 jme_reset_phy_processor(struct jme_adapter *jme)
115 u32 val;
117 jme_mdio_write(jme->dev,
118 jme->mii_if.phy_id,
119 MII_ADVERTISE, ADVERTISE_ALL |
120 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
122 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
123 jme_mdio_write(jme->dev,
124 jme->mii_if.phy_id,
125 MII_CTRL1000,
126 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
128 val = jme_mdio_read(jme->dev,
129 jme->mii_if.phy_id,
130 MII_BMCR);
132 jme_mdio_write(jme->dev,
133 jme->mii_if.phy_id,
134 MII_BMCR, val | BMCR_RESET);
137 static void
138 jme_setup_wakeup_frame(struct jme_adapter *jme,
139 const u32 *mask, u32 crc, int fnr)
141 int i;
144 * Setup CRC pattern
146 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
147 wmb();
148 jwrite32(jme, JME_WFODP, crc);
149 wmb();
152 * Setup Mask
154 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
155 jwrite32(jme, JME_WFOI,
156 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
157 (fnr & WFOI_FRAME_SEL));
158 wmb();
159 jwrite32(jme, JME_WFODP, mask[i]);
160 wmb();
164 static inline void
165 jme_mac_rxclk_off(struct jme_adapter *jme)
167 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
168 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
171 static inline void
172 jme_mac_rxclk_on(struct jme_adapter *jme)
174 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
175 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
178 static inline void
179 jme_mac_txclk_off(struct jme_adapter *jme)
181 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
182 jwrite32f(jme, JME_GHC, jme->reg_ghc);
185 static inline void
186 jme_mac_txclk_on(struct jme_adapter *jme)
188 u32 speed = jme->reg_ghc & GHC_SPEED;
189 if (speed == GHC_SPEED_1000M)
190 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
191 else
192 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
193 jwrite32f(jme, JME_GHC, jme->reg_ghc);
196 static inline void
197 jme_reset_ghc_speed(struct jme_adapter *jme)
199 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
200 jwrite32f(jme, JME_GHC, jme->reg_ghc);
203 static inline void
204 jme_reset_250A2_workaround(struct jme_adapter *jme)
206 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
207 GPREG1_RSSPATCH);
208 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
211 static inline void
212 jme_assert_ghc_reset(struct jme_adapter *jme)
214 jme->reg_ghc |= GHC_SWRST;
215 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218 static inline void
219 jme_clear_ghc_reset(struct jme_adapter *jme)
221 jme->reg_ghc &= ~GHC_SWRST;
222 jwrite32f(jme, JME_GHC, jme->reg_ghc);
225 static void
226 jme_reset_mac_processor(struct jme_adapter *jme)
228 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
229 u32 crc = 0xCDCDCDCD;
230 u32 gpreg0;
231 int i;
233 jme_reset_ghc_speed(jme);
234 jme_reset_250A2_workaround(jme);
236 jme_mac_rxclk_on(jme);
237 jme_mac_txclk_on(jme);
238 udelay(1);
239 jme_assert_ghc_reset(jme);
240 udelay(1);
241 jme_mac_rxclk_off(jme);
242 jme_mac_txclk_off(jme);
243 udelay(1);
244 jme_clear_ghc_reset(jme);
245 udelay(1);
246 jme_mac_rxclk_on(jme);
247 jme_mac_txclk_on(jme);
248 udelay(1);
249 jme_mac_rxclk_off(jme);
250 jme_mac_txclk_off(jme);
252 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
253 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
254 jwrite32(jme, JME_RXQDC, 0x00000000);
255 jwrite32(jme, JME_RXNDA, 0x00000000);
256 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
257 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
258 jwrite32(jme, JME_TXQDC, 0x00000000);
259 jwrite32(jme, JME_TXNDA, 0x00000000);
261 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
262 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
263 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
264 jme_setup_wakeup_frame(jme, mask, crc, i);
265 if (jme->fpgaver)
266 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
267 else
268 gpreg0 = GPREG0_DEFAULT;
269 jwrite32(jme, JME_GPREG0, gpreg0);
272 static inline void
273 jme_clear_pm_enable_wol(struct jme_adapter *jme)
275 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
278 static inline void
279 jme_clear_pm_disable_wol(struct jme_adapter *jme)
281 jwrite32(jme, JME_PMCS, PMCS_STMASK);
284 static int
285 jme_reload_eeprom(struct jme_adapter *jme)
287 u32 val;
288 int i;
290 val = jread32(jme, JME_SMBCSR);
292 if (val & SMBCSR_EEPROMD) {
293 val |= SMBCSR_CNACK;
294 jwrite32(jme, JME_SMBCSR, val);
295 val |= SMBCSR_RELOAD;
296 jwrite32(jme, JME_SMBCSR, val);
297 mdelay(12);
299 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
300 mdelay(1);
301 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
302 break;
305 if (i == 0) {
306 pr_err("eeprom reload timeout\n");
307 return -EIO;
311 return 0;
314 static void
315 jme_load_macaddr(struct net_device *netdev)
317 struct jme_adapter *jme = netdev_priv(netdev);
318 unsigned char macaddr[ETH_ALEN];
319 u32 val;
321 spin_lock_bh(&jme->macaddr_lock);
322 val = jread32(jme, JME_RXUMA_LO);
323 macaddr[0] = (val >> 0) & 0xFF;
324 macaddr[1] = (val >> 8) & 0xFF;
325 macaddr[2] = (val >> 16) & 0xFF;
326 macaddr[3] = (val >> 24) & 0xFF;
327 val = jread32(jme, JME_RXUMA_HI);
328 macaddr[4] = (val >> 0) & 0xFF;
329 macaddr[5] = (val >> 8) & 0xFF;
330 memcpy(netdev->dev_addr, macaddr, ETH_ALEN);
331 spin_unlock_bh(&jme->macaddr_lock);
334 static inline void
335 jme_set_rx_pcc(struct jme_adapter *jme, int p)
337 switch (p) {
338 case PCC_OFF:
339 jwrite32(jme, JME_PCCRX0,
340 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
341 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
342 break;
343 case PCC_P1:
344 jwrite32(jme, JME_PCCRX0,
345 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
346 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
347 break;
348 case PCC_P2:
349 jwrite32(jme, JME_PCCRX0,
350 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
351 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
352 break;
353 case PCC_P3:
354 jwrite32(jme, JME_PCCRX0,
355 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
356 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
357 break;
358 default:
359 break;
361 wmb();
363 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
364 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
367 static void
368 jme_start_irq(struct jme_adapter *jme)
370 register struct dynpcc_info *dpi = &(jme->dpi);
372 jme_set_rx_pcc(jme, PCC_P1);
373 dpi->cur = PCC_P1;
374 dpi->attempt = PCC_P1;
375 dpi->cnt = 0;
377 jwrite32(jme, JME_PCCTX,
378 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
379 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
380 PCCTXQ0_EN
384 * Enable Interrupts
386 jwrite32(jme, JME_IENS, INTR_ENABLE);
389 static inline void
390 jme_stop_irq(struct jme_adapter *jme)
393 * Disable Interrupts
395 jwrite32f(jme, JME_IENC, INTR_ENABLE);
398 static u32
399 jme_linkstat_from_phy(struct jme_adapter *jme)
401 u32 phylink, bmsr;
403 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
404 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
405 if (bmsr & BMSR_ANCOMP)
406 phylink |= PHY_LINK_AUTONEG_COMPLETE;
408 return phylink;
411 static inline void
412 jme_set_phyfifo_5level(struct jme_adapter *jme)
414 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
417 static inline void
418 jme_set_phyfifo_8level(struct jme_adapter *jme)
420 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
423 static int
424 jme_check_link(struct net_device *netdev, int testonly)
426 struct jme_adapter *jme = netdev_priv(netdev);
427 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
428 char linkmsg[64];
429 int rc = 0;
431 linkmsg[0] = '\0';
433 if (jme->fpgaver)
434 phylink = jme_linkstat_from_phy(jme);
435 else
436 phylink = jread32(jme, JME_PHY_LINK);
438 if (phylink & PHY_LINK_UP) {
439 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
441 * If we did not enable AN
442 * Speed/Duplex Info should be obtained from SMI
444 phylink = PHY_LINK_UP;
446 bmcr = jme_mdio_read(jme->dev,
447 jme->mii_if.phy_id,
448 MII_BMCR);
450 phylink |= ((bmcr & BMCR_SPEED1000) &&
451 (bmcr & BMCR_SPEED100) == 0) ?
452 PHY_LINK_SPEED_1000M :
453 (bmcr & BMCR_SPEED100) ?
454 PHY_LINK_SPEED_100M :
455 PHY_LINK_SPEED_10M;
457 phylink |= (bmcr & BMCR_FULLDPLX) ?
458 PHY_LINK_DUPLEX : 0;
460 strcat(linkmsg, "Forced: ");
461 } else {
463 * Keep polling for speed/duplex resolve complete
465 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
466 --cnt) {
468 udelay(1);
470 if (jme->fpgaver)
471 phylink = jme_linkstat_from_phy(jme);
472 else
473 phylink = jread32(jme, JME_PHY_LINK);
475 if (!cnt)
476 pr_err("Waiting speed resolve timeout\n");
478 strcat(linkmsg, "ANed: ");
481 if (jme->phylink == phylink) {
482 rc = 1;
483 goto out;
485 if (testonly)
486 goto out;
488 jme->phylink = phylink;
491 * The speed/duplex setting of jme->reg_ghc already cleared
492 * by jme_reset_mac_processor()
494 switch (phylink & PHY_LINK_SPEED_MASK) {
495 case PHY_LINK_SPEED_10M:
496 jme->reg_ghc |= GHC_SPEED_10M;
497 strcat(linkmsg, "10 Mbps, ");
498 break;
499 case PHY_LINK_SPEED_100M:
500 jme->reg_ghc |= GHC_SPEED_100M;
501 strcat(linkmsg, "100 Mbps, ");
502 break;
503 case PHY_LINK_SPEED_1000M:
504 jme->reg_ghc |= GHC_SPEED_1000M;
505 strcat(linkmsg, "1000 Mbps, ");
506 break;
507 default:
508 break;
511 if (phylink & PHY_LINK_DUPLEX) {
512 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
513 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
514 jme->reg_ghc |= GHC_DPX;
515 } else {
516 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
517 TXMCS_BACKOFF |
518 TXMCS_CARRIERSENSE |
519 TXMCS_COLLISION);
520 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
523 jwrite32(jme, JME_GHC, jme->reg_ghc);
525 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
526 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
527 GPREG1_RSSPATCH);
528 if (!(phylink & PHY_LINK_DUPLEX))
529 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
530 switch (phylink & PHY_LINK_SPEED_MASK) {
531 case PHY_LINK_SPEED_10M:
532 jme_set_phyfifo_8level(jme);
533 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
534 break;
535 case PHY_LINK_SPEED_100M:
536 jme_set_phyfifo_5level(jme);
537 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
538 break;
539 case PHY_LINK_SPEED_1000M:
540 jme_set_phyfifo_8level(jme);
541 break;
542 default:
543 break;
546 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
548 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
549 "Full-Duplex, " :
550 "Half-Duplex, ");
551 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
552 "MDI-X" :
553 "MDI");
554 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
555 netif_carrier_on(netdev);
556 } else {
557 if (testonly)
558 goto out;
560 netif_info(jme, link, jme->dev, "Link is down\n");
561 jme->phylink = 0;
562 netif_carrier_off(netdev);
565 out:
566 return rc;
569 static int
570 jme_setup_tx_resources(struct jme_adapter *jme)
572 struct jme_ring *txring = &(jme->txring[0]);
574 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
575 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
576 &(txring->dmaalloc),
577 GFP_ATOMIC);
579 if (!txring->alloc)
580 goto err_set_null;
583 * 16 Bytes align
585 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
586 RING_DESC_ALIGN);
587 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
588 txring->next_to_use = 0;
589 atomic_set(&txring->next_to_clean, 0);
590 atomic_set(&txring->nr_free, jme->tx_ring_size);
592 txring->bufinf = kzalloc(sizeof(struct jme_buffer_info) *
593 jme->tx_ring_size, GFP_ATOMIC);
594 if (unlikely(!(txring->bufinf)))
595 goto err_free_txring;
598 * Initialize Transmit Descriptors
600 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
602 return 0;
604 err_free_txring:
605 dma_free_coherent(&(jme->pdev->dev),
606 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
607 txring->alloc,
608 txring->dmaalloc);
610 err_set_null:
611 txring->desc = NULL;
612 txring->dmaalloc = 0;
613 txring->dma = 0;
614 txring->bufinf = NULL;
616 return -ENOMEM;
619 static void
620 jme_free_tx_resources(struct jme_adapter *jme)
622 int i;
623 struct jme_ring *txring = &(jme->txring[0]);
624 struct jme_buffer_info *txbi;
626 if (txring->alloc) {
627 if (txring->bufinf) {
628 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
629 txbi = txring->bufinf + i;
630 if (txbi->skb) {
631 dev_kfree_skb(txbi->skb);
632 txbi->skb = NULL;
634 txbi->mapping = 0;
635 txbi->len = 0;
636 txbi->nr_desc = 0;
637 txbi->start_xmit = 0;
639 kfree(txring->bufinf);
642 dma_free_coherent(&(jme->pdev->dev),
643 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
644 txring->alloc,
645 txring->dmaalloc);
647 txring->alloc = NULL;
648 txring->desc = NULL;
649 txring->dmaalloc = 0;
650 txring->dma = 0;
651 txring->bufinf = NULL;
653 txring->next_to_use = 0;
654 atomic_set(&txring->next_to_clean, 0);
655 atomic_set(&txring->nr_free, 0);
658 static inline void
659 jme_enable_tx_engine(struct jme_adapter *jme)
662 * Select Queue 0
664 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
665 wmb();
668 * Setup TX Queue 0 DMA Bass Address
670 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
671 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
672 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
675 * Setup TX Descptor Count
677 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
680 * Enable TX Engine
682 wmb();
683 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
684 TXCS_SELECT_QUEUE0 |
685 TXCS_ENABLE);
688 * Start clock for TX MAC Processor
690 jme_mac_txclk_on(jme);
693 static inline void
694 jme_disable_tx_engine(struct jme_adapter *jme)
696 int i;
697 u32 val;
700 * Disable TX Engine
702 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
703 wmb();
705 val = jread32(jme, JME_TXCS);
706 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
707 mdelay(1);
708 val = jread32(jme, JME_TXCS);
709 rmb();
712 if (!i)
713 pr_err("Disable TX engine timeout\n");
716 * Stop clock for TX MAC Processor
718 jme_mac_txclk_off(jme);
721 static void
722 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
724 struct jme_ring *rxring = &(jme->rxring[0]);
725 register struct rxdesc *rxdesc = rxring->desc;
726 struct jme_buffer_info *rxbi = rxring->bufinf;
727 rxdesc += i;
728 rxbi += i;
730 rxdesc->dw[0] = 0;
731 rxdesc->dw[1] = 0;
732 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
733 rxdesc->desc1.bufaddrl = cpu_to_le32(
734 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
735 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
736 if (jme->dev->features & NETIF_F_HIGHDMA)
737 rxdesc->desc1.flags = RXFLAG_64BIT;
738 wmb();
739 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
742 static int
743 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
745 struct jme_ring *rxring = &(jme->rxring[0]);
746 struct jme_buffer_info *rxbi = rxring->bufinf + i;
747 struct sk_buff *skb;
748 dma_addr_t mapping;
750 skb = netdev_alloc_skb(jme->dev,
751 jme->dev->mtu + RX_EXTRA_LEN);
752 if (unlikely(!skb))
753 return -ENOMEM;
755 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
756 offset_in_page(skb->data), skb_tailroom(skb),
757 PCI_DMA_FROMDEVICE);
758 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
759 dev_kfree_skb(skb);
760 return -ENOMEM;
763 if (likely(rxbi->mapping))
764 pci_unmap_page(jme->pdev, rxbi->mapping,
765 rxbi->len, PCI_DMA_FROMDEVICE);
767 rxbi->skb = skb;
768 rxbi->len = skb_tailroom(skb);
769 rxbi->mapping = mapping;
770 return 0;
773 static void
774 jme_free_rx_buf(struct jme_adapter *jme, int i)
776 struct jme_ring *rxring = &(jme->rxring[0]);
777 struct jme_buffer_info *rxbi = rxring->bufinf;
778 rxbi += i;
780 if (rxbi->skb) {
781 pci_unmap_page(jme->pdev,
782 rxbi->mapping,
783 rxbi->len,
784 PCI_DMA_FROMDEVICE);
785 dev_kfree_skb(rxbi->skb);
786 rxbi->skb = NULL;
787 rxbi->mapping = 0;
788 rxbi->len = 0;
792 static void
793 jme_free_rx_resources(struct jme_adapter *jme)
795 int i;
796 struct jme_ring *rxring = &(jme->rxring[0]);
798 if (rxring->alloc) {
799 if (rxring->bufinf) {
800 for (i = 0 ; i < jme->rx_ring_size ; ++i)
801 jme_free_rx_buf(jme, i);
802 kfree(rxring->bufinf);
805 dma_free_coherent(&(jme->pdev->dev),
806 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
807 rxring->alloc,
808 rxring->dmaalloc);
809 rxring->alloc = NULL;
810 rxring->desc = NULL;
811 rxring->dmaalloc = 0;
812 rxring->dma = 0;
813 rxring->bufinf = NULL;
815 rxring->next_to_use = 0;
816 atomic_set(&rxring->next_to_clean, 0);
819 static int
820 jme_setup_rx_resources(struct jme_adapter *jme)
822 int i;
823 struct jme_ring *rxring = &(jme->rxring[0]);
825 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
826 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
827 &(rxring->dmaalloc),
828 GFP_ATOMIC);
829 if (!rxring->alloc)
830 goto err_set_null;
833 * 16 Bytes align
835 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
836 RING_DESC_ALIGN);
837 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
838 rxring->next_to_use = 0;
839 atomic_set(&rxring->next_to_clean, 0);
841 rxring->bufinf = kzalloc(sizeof(struct jme_buffer_info) *
842 jme->rx_ring_size, GFP_ATOMIC);
843 if (unlikely(!(rxring->bufinf)))
844 goto err_free_rxring;
847 * Initiallize Receive Descriptors
849 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
850 if (unlikely(jme_make_new_rx_buf(jme, i))) {
851 jme_free_rx_resources(jme);
852 return -ENOMEM;
855 jme_set_clean_rxdesc(jme, i);
858 return 0;
860 err_free_rxring:
861 dma_free_coherent(&(jme->pdev->dev),
862 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
863 rxring->alloc,
864 rxring->dmaalloc);
865 err_set_null:
866 rxring->desc = NULL;
867 rxring->dmaalloc = 0;
868 rxring->dma = 0;
869 rxring->bufinf = NULL;
871 return -ENOMEM;
874 static inline void
875 jme_enable_rx_engine(struct jme_adapter *jme)
878 * Select Queue 0
880 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
881 RXCS_QUEUESEL_Q0);
882 wmb();
885 * Setup RX DMA Bass Address
887 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
888 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
889 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
892 * Setup RX Descriptor Count
894 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
897 * Setup Unicast Filter
899 jme_set_unicastaddr(jme->dev);
900 jme_set_multi(jme->dev);
903 * Enable RX Engine
905 wmb();
906 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
907 RXCS_QUEUESEL_Q0 |
908 RXCS_ENABLE |
909 RXCS_QST);
912 * Start clock for RX MAC Processor
914 jme_mac_rxclk_on(jme);
917 static inline void
918 jme_restart_rx_engine(struct jme_adapter *jme)
921 * Start RX Engine
923 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
924 RXCS_QUEUESEL_Q0 |
925 RXCS_ENABLE |
926 RXCS_QST);
929 static inline void
930 jme_disable_rx_engine(struct jme_adapter *jme)
932 int i;
933 u32 val;
936 * Disable RX Engine
938 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
939 wmb();
941 val = jread32(jme, JME_RXCS);
942 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
943 mdelay(1);
944 val = jread32(jme, JME_RXCS);
945 rmb();
948 if (!i)
949 pr_err("Disable RX engine timeout\n");
952 * Stop clock for RX MAC Processor
954 jme_mac_rxclk_off(jme);
957 static u16
958 jme_udpsum(struct sk_buff *skb)
960 u16 csum = 0xFFFFu;
962 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
963 return csum;
964 if (skb->protocol != htons(ETH_P_IP))
965 return csum;
966 skb_set_network_header(skb, ETH_HLEN);
967 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
968 (skb->len < (ETH_HLEN +
969 (ip_hdr(skb)->ihl << 2) +
970 sizeof(struct udphdr)))) {
971 skb_reset_network_header(skb);
972 return csum;
974 skb_set_transport_header(skb,
975 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
976 csum = udp_hdr(skb)->check;
977 skb_reset_transport_header(skb);
978 skb_reset_network_header(skb);
980 return csum;
983 static int
984 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
986 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
987 return false;
989 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
990 == RXWBFLAG_TCPON)) {
991 if (flags & RXWBFLAG_IPV4)
992 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
993 return false;
996 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
997 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
998 if (flags & RXWBFLAG_IPV4)
999 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1000 return false;
1003 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1004 == RXWBFLAG_IPV4)) {
1005 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1006 return false;
1009 return true;
1012 static void
1013 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1015 struct jme_ring *rxring = &(jme->rxring[0]);
1016 struct rxdesc *rxdesc = rxring->desc;
1017 struct jme_buffer_info *rxbi = rxring->bufinf;
1018 struct sk_buff *skb;
1019 int framesize;
1021 rxdesc += idx;
1022 rxbi += idx;
1024 skb = rxbi->skb;
1025 pci_dma_sync_single_for_cpu(jme->pdev,
1026 rxbi->mapping,
1027 rxbi->len,
1028 PCI_DMA_FROMDEVICE);
1030 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1031 pci_dma_sync_single_for_device(jme->pdev,
1032 rxbi->mapping,
1033 rxbi->len,
1034 PCI_DMA_FROMDEVICE);
1036 ++(NET_STAT(jme).rx_dropped);
1037 } else {
1038 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1039 - RX_PREPAD_SIZE;
1041 skb_reserve(skb, RX_PREPAD_SIZE);
1042 skb_put(skb, framesize);
1043 skb->protocol = eth_type_trans(skb, jme->dev);
1045 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1046 skb->ip_summed = CHECKSUM_UNNECESSARY;
1047 else
1048 skb_checksum_none_assert(skb);
1050 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1051 u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1053 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1054 NET_STAT(jme).rx_bytes += 4;
1056 jme->jme_rx(skb);
1058 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1059 cpu_to_le16(RXWBFLAG_DEST_MUL))
1060 ++(NET_STAT(jme).multicast);
1062 NET_STAT(jme).rx_bytes += framesize;
1063 ++(NET_STAT(jme).rx_packets);
1066 jme_set_clean_rxdesc(jme, idx);
1070 static int
1071 jme_process_receive(struct jme_adapter *jme, int limit)
1073 struct jme_ring *rxring = &(jme->rxring[0]);
1074 struct rxdesc *rxdesc;
1075 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1077 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1078 goto out_inc;
1080 if (unlikely(atomic_read(&jme->link_changing) != 1))
1081 goto out_inc;
1083 if (unlikely(!netif_carrier_ok(jme->dev)))
1084 goto out_inc;
1086 i = atomic_read(&rxring->next_to_clean);
1087 while (limit > 0) {
1088 rxdesc = rxring->desc;
1089 rxdesc += i;
1091 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1092 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1093 goto out;
1094 --limit;
1096 rmb();
1097 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1099 if (unlikely(desccnt > 1 ||
1100 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1102 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1103 ++(NET_STAT(jme).rx_crc_errors);
1104 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1105 ++(NET_STAT(jme).rx_fifo_errors);
1106 else
1107 ++(NET_STAT(jme).rx_errors);
1109 if (desccnt > 1)
1110 limit -= desccnt - 1;
1112 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1113 jme_set_clean_rxdesc(jme, j);
1114 j = (j + 1) & (mask);
1117 } else {
1118 jme_alloc_and_feed_skb(jme, i);
1121 i = (i + desccnt) & (mask);
1124 out:
1125 atomic_set(&rxring->next_to_clean, i);
1127 out_inc:
1128 atomic_inc(&jme->rx_cleaning);
1130 return limit > 0 ? limit : 0;
1134 static void
1135 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1137 if (likely(atmp == dpi->cur)) {
1138 dpi->cnt = 0;
1139 return;
1142 if (dpi->attempt == atmp) {
1143 ++(dpi->cnt);
1144 } else {
1145 dpi->attempt = atmp;
1146 dpi->cnt = 0;
1151 static void
1152 jme_dynamic_pcc(struct jme_adapter *jme)
1154 register struct dynpcc_info *dpi = &(jme->dpi);
1156 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1157 jme_attempt_pcc(dpi, PCC_P3);
1158 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1159 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1160 jme_attempt_pcc(dpi, PCC_P2);
1161 else
1162 jme_attempt_pcc(dpi, PCC_P1);
1164 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1165 if (dpi->attempt < dpi->cur)
1166 tasklet_schedule(&jme->rxclean_task);
1167 jme_set_rx_pcc(jme, dpi->attempt);
1168 dpi->cur = dpi->attempt;
1169 dpi->cnt = 0;
1173 static void
1174 jme_start_pcc_timer(struct jme_adapter *jme)
1176 struct dynpcc_info *dpi = &(jme->dpi);
1177 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1178 dpi->last_pkts = NET_STAT(jme).rx_packets;
1179 dpi->intr_cnt = 0;
1180 jwrite32(jme, JME_TMCSR,
1181 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1184 static inline void
1185 jme_stop_pcc_timer(struct jme_adapter *jme)
1187 jwrite32(jme, JME_TMCSR, 0);
1190 static void
1191 jme_shutdown_nic(struct jme_adapter *jme)
1193 u32 phylink;
1195 phylink = jme_linkstat_from_phy(jme);
1197 if (!(phylink & PHY_LINK_UP)) {
1199 * Disable all interrupt before issue timer
1201 jme_stop_irq(jme);
1202 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1206 static void
1207 jme_pcc_tasklet(unsigned long arg)
1209 struct jme_adapter *jme = (struct jme_adapter *)arg;
1210 struct net_device *netdev = jme->dev;
1212 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1213 jme_shutdown_nic(jme);
1214 return;
1217 if (unlikely(!netif_carrier_ok(netdev) ||
1218 (atomic_read(&jme->link_changing) != 1)
1219 )) {
1220 jme_stop_pcc_timer(jme);
1221 return;
1224 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1225 jme_dynamic_pcc(jme);
1227 jme_start_pcc_timer(jme);
1230 static inline void
1231 jme_polling_mode(struct jme_adapter *jme)
1233 jme_set_rx_pcc(jme, PCC_OFF);
1236 static inline void
1237 jme_interrupt_mode(struct jme_adapter *jme)
1239 jme_set_rx_pcc(jme, PCC_P1);
1242 static inline int
1243 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1245 u32 apmc;
1246 apmc = jread32(jme, JME_APMC);
1247 return apmc & JME_APMC_PSEUDO_HP_EN;
1250 static void
1251 jme_start_shutdown_timer(struct jme_adapter *jme)
1253 u32 apmc;
1255 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1256 apmc &= ~JME_APMC_EPIEN_CTRL;
1257 if (!no_extplug) {
1258 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1259 wmb();
1261 jwrite32f(jme, JME_APMC, apmc);
1263 jwrite32f(jme, JME_TIMER2, 0);
1264 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1265 jwrite32(jme, JME_TMCSR,
1266 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1269 static void
1270 jme_stop_shutdown_timer(struct jme_adapter *jme)
1272 u32 apmc;
1274 jwrite32f(jme, JME_TMCSR, 0);
1275 jwrite32f(jme, JME_TIMER2, 0);
1276 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1278 apmc = jread32(jme, JME_APMC);
1279 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1280 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1281 wmb();
1282 jwrite32f(jme, JME_APMC, apmc);
1285 static void
1286 jme_link_change_tasklet(unsigned long arg)
1288 struct jme_adapter *jme = (struct jme_adapter *)arg;
1289 struct net_device *netdev = jme->dev;
1290 int rc;
1292 while (!atomic_dec_and_test(&jme->link_changing)) {
1293 atomic_inc(&jme->link_changing);
1294 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1295 while (atomic_read(&jme->link_changing) != 1)
1296 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1299 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1300 goto out;
1302 jme->old_mtu = netdev->mtu;
1303 netif_stop_queue(netdev);
1304 if (jme_pseudo_hotplug_enabled(jme))
1305 jme_stop_shutdown_timer(jme);
1307 jme_stop_pcc_timer(jme);
1308 tasklet_disable(&jme->txclean_task);
1309 tasklet_disable(&jme->rxclean_task);
1310 tasklet_disable(&jme->rxempty_task);
1312 if (netif_carrier_ok(netdev)) {
1313 jme_disable_rx_engine(jme);
1314 jme_disable_tx_engine(jme);
1315 jme_reset_mac_processor(jme);
1316 jme_free_rx_resources(jme);
1317 jme_free_tx_resources(jme);
1319 if (test_bit(JME_FLAG_POLL, &jme->flags))
1320 jme_polling_mode(jme);
1322 netif_carrier_off(netdev);
1325 jme_check_link(netdev, 0);
1326 if (netif_carrier_ok(netdev)) {
1327 rc = jme_setup_rx_resources(jme);
1328 if (rc) {
1329 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1330 goto out_enable_tasklet;
1333 rc = jme_setup_tx_resources(jme);
1334 if (rc) {
1335 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1336 goto err_out_free_rx_resources;
1339 jme_enable_rx_engine(jme);
1340 jme_enable_tx_engine(jme);
1342 netif_start_queue(netdev);
1344 if (test_bit(JME_FLAG_POLL, &jme->flags))
1345 jme_interrupt_mode(jme);
1347 jme_start_pcc_timer(jme);
1348 } else if (jme_pseudo_hotplug_enabled(jme)) {
1349 jme_start_shutdown_timer(jme);
1352 goto out_enable_tasklet;
1354 err_out_free_rx_resources:
1355 jme_free_rx_resources(jme);
1356 out_enable_tasklet:
1357 tasklet_enable(&jme->txclean_task);
1358 tasklet_enable(&jme->rxclean_task);
1359 tasklet_enable(&jme->rxempty_task);
1360 out:
1361 atomic_inc(&jme->link_changing);
1364 static void
1365 jme_rx_clean_tasklet(unsigned long arg)
1367 struct jme_adapter *jme = (struct jme_adapter *)arg;
1368 struct dynpcc_info *dpi = &(jme->dpi);
1370 jme_process_receive(jme, jme->rx_ring_size);
1371 ++(dpi->intr_cnt);
1375 static int
1376 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1378 struct jme_adapter *jme = jme_napi_priv(holder);
1379 int rest;
1381 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1383 while (atomic_read(&jme->rx_empty) > 0) {
1384 atomic_dec(&jme->rx_empty);
1385 ++(NET_STAT(jme).rx_dropped);
1386 jme_restart_rx_engine(jme);
1388 atomic_inc(&jme->rx_empty);
1390 if (rest) {
1391 JME_RX_COMPLETE(netdev, holder);
1392 jme_interrupt_mode(jme);
1395 JME_NAPI_WEIGHT_SET(budget, rest);
1396 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1399 static void
1400 jme_rx_empty_tasklet(unsigned long arg)
1402 struct jme_adapter *jme = (struct jme_adapter *)arg;
1404 if (unlikely(atomic_read(&jme->link_changing) != 1))
1405 return;
1407 if (unlikely(!netif_carrier_ok(jme->dev)))
1408 return;
1410 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1412 jme_rx_clean_tasklet(arg);
1414 while (atomic_read(&jme->rx_empty) > 0) {
1415 atomic_dec(&jme->rx_empty);
1416 ++(NET_STAT(jme).rx_dropped);
1417 jme_restart_rx_engine(jme);
1419 atomic_inc(&jme->rx_empty);
1422 static void
1423 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1425 struct jme_ring *txring = &(jme->txring[0]);
1427 smp_wmb();
1428 if (unlikely(netif_queue_stopped(jme->dev) &&
1429 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1430 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1431 netif_wake_queue(jme->dev);
1436 static void
1437 jme_tx_clean_tasklet(unsigned long arg)
1439 struct jme_adapter *jme = (struct jme_adapter *)arg;
1440 struct jme_ring *txring = &(jme->txring[0]);
1441 struct txdesc *txdesc = txring->desc;
1442 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1443 int i, j, cnt = 0, max, err, mask;
1445 tx_dbg(jme, "Into txclean\n");
1447 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1448 goto out;
1450 if (unlikely(atomic_read(&jme->link_changing) != 1))
1451 goto out;
1453 if (unlikely(!netif_carrier_ok(jme->dev)))
1454 goto out;
1456 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1457 mask = jme->tx_ring_mask;
1459 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1461 ctxbi = txbi + i;
1463 if (likely(ctxbi->skb &&
1464 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1466 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1467 i, ctxbi->nr_desc, jiffies);
1469 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1471 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1472 ttxbi = txbi + ((i + j) & (mask));
1473 txdesc[(i + j) & (mask)].dw[0] = 0;
1475 pci_unmap_page(jme->pdev,
1476 ttxbi->mapping,
1477 ttxbi->len,
1478 PCI_DMA_TODEVICE);
1480 ttxbi->mapping = 0;
1481 ttxbi->len = 0;
1484 dev_kfree_skb(ctxbi->skb);
1486 cnt += ctxbi->nr_desc;
1488 if (unlikely(err)) {
1489 ++(NET_STAT(jme).tx_carrier_errors);
1490 } else {
1491 ++(NET_STAT(jme).tx_packets);
1492 NET_STAT(jme).tx_bytes += ctxbi->len;
1495 ctxbi->skb = NULL;
1496 ctxbi->len = 0;
1497 ctxbi->start_xmit = 0;
1499 } else {
1500 break;
1503 i = (i + ctxbi->nr_desc) & mask;
1505 ctxbi->nr_desc = 0;
1508 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1509 atomic_set(&txring->next_to_clean, i);
1510 atomic_add(cnt, &txring->nr_free);
1512 jme_wake_queue_if_stopped(jme);
1514 out:
1515 atomic_inc(&jme->tx_cleaning);
1518 static void
1519 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1522 * Disable interrupt
1524 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1526 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1528 * Link change event is critical
1529 * all other events are ignored
1531 jwrite32(jme, JME_IEVE, intrstat);
1532 tasklet_schedule(&jme->linkch_task);
1533 goto out_reenable;
1536 if (intrstat & INTR_TMINTR) {
1537 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1538 tasklet_schedule(&jme->pcc_task);
1541 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1542 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1543 tasklet_schedule(&jme->txclean_task);
1546 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1547 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1548 INTR_PCCRX0 |
1549 INTR_RX0EMP)) |
1550 INTR_RX0);
1553 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1554 if (intrstat & INTR_RX0EMP)
1555 atomic_inc(&jme->rx_empty);
1557 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1558 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1559 jme_polling_mode(jme);
1560 JME_RX_SCHEDULE(jme);
1563 } else {
1564 if (intrstat & INTR_RX0EMP) {
1565 atomic_inc(&jme->rx_empty);
1566 tasklet_hi_schedule(&jme->rxempty_task);
1567 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1568 tasklet_hi_schedule(&jme->rxclean_task);
1572 out_reenable:
1574 * Re-enable interrupt
1576 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1579 static irqreturn_t
1580 jme_intr(int irq, void *dev_id)
1582 struct net_device *netdev = dev_id;
1583 struct jme_adapter *jme = netdev_priv(netdev);
1584 u32 intrstat;
1586 intrstat = jread32(jme, JME_IEVE);
1589 * Check if it's really an interrupt for us
1591 if (unlikely((intrstat & INTR_ENABLE) == 0))
1592 return IRQ_NONE;
1595 * Check if the device still exist
1597 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1598 return IRQ_NONE;
1600 jme_intr_msi(jme, intrstat);
1602 return IRQ_HANDLED;
1605 static irqreturn_t
1606 jme_msi(int irq, void *dev_id)
1608 struct net_device *netdev = dev_id;
1609 struct jme_adapter *jme = netdev_priv(netdev);
1610 u32 intrstat;
1612 intrstat = jread32(jme, JME_IEVE);
1614 jme_intr_msi(jme, intrstat);
1616 return IRQ_HANDLED;
1619 static void
1620 jme_reset_link(struct jme_adapter *jme)
1622 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1625 static void
1626 jme_restart_an(struct jme_adapter *jme)
1628 u32 bmcr;
1630 spin_lock_bh(&jme->phy_lock);
1631 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1632 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1633 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1634 spin_unlock_bh(&jme->phy_lock);
1637 static int
1638 jme_request_irq(struct jme_adapter *jme)
1640 int rc;
1641 struct net_device *netdev = jme->dev;
1642 irq_handler_t handler = jme_intr;
1643 int irq_flags = IRQF_SHARED;
1645 if (!pci_enable_msi(jme->pdev)) {
1646 set_bit(JME_FLAG_MSI, &jme->flags);
1647 handler = jme_msi;
1648 irq_flags = 0;
1651 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1652 netdev);
1653 if (rc) {
1654 netdev_err(netdev,
1655 "Unable to request %s interrupt (return: %d)\n",
1656 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1657 rc);
1659 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1660 pci_disable_msi(jme->pdev);
1661 clear_bit(JME_FLAG_MSI, &jme->flags);
1663 } else {
1664 netdev->irq = jme->pdev->irq;
1667 return rc;
1670 static void
1671 jme_free_irq(struct jme_adapter *jme)
1673 free_irq(jme->pdev->irq, jme->dev);
1674 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1675 pci_disable_msi(jme->pdev);
1676 clear_bit(JME_FLAG_MSI, &jme->flags);
1677 jme->dev->irq = jme->pdev->irq;
1681 static inline void
1682 jme_new_phy_on(struct jme_adapter *jme)
1684 u32 reg;
1686 reg = jread32(jme, JME_PHY_PWR);
1687 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1688 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1689 jwrite32(jme, JME_PHY_PWR, reg);
1691 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1692 reg &= ~PE1_GPREG0_PBG;
1693 reg |= PE1_GPREG0_ENBG;
1694 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1697 static inline void
1698 jme_new_phy_off(struct jme_adapter *jme)
1700 u32 reg;
1702 reg = jread32(jme, JME_PHY_PWR);
1703 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1704 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1705 jwrite32(jme, JME_PHY_PWR, reg);
1707 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1708 reg &= ~PE1_GPREG0_PBG;
1709 reg |= PE1_GPREG0_PDD3COLD;
1710 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1713 static inline void
1714 jme_phy_on(struct jme_adapter *jme)
1716 u32 bmcr;
1718 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1719 bmcr &= ~BMCR_PDOWN;
1720 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1722 if (new_phy_power_ctrl(jme->chip_main_rev))
1723 jme_new_phy_on(jme);
1726 static inline void
1727 jme_phy_off(struct jme_adapter *jme)
1729 u32 bmcr;
1731 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1732 bmcr |= BMCR_PDOWN;
1733 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1735 if (new_phy_power_ctrl(jme->chip_main_rev))
1736 jme_new_phy_off(jme);
1739 static int
1740 jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg)
1742 u32 phy_addr;
1744 phy_addr = JM_PHY_SPEC_REG_READ | specreg;
1745 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1746 phy_addr);
1747 return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
1748 JM_PHY_SPEC_DATA_REG);
1751 static void
1752 jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data)
1754 u32 phy_addr;
1756 phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg;
1757 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG,
1758 phy_data);
1759 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1760 phy_addr);
1763 static int
1764 jme_phy_calibration(struct jme_adapter *jme)
1766 u32 ctrl1000, phy_data;
1768 jme_phy_off(jme);
1769 jme_phy_on(jme);
1770 /* Enabel PHY test mode 1 */
1771 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1772 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1773 ctrl1000 |= PHY_GAD_TEST_MODE_1;
1774 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1776 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1777 phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0;
1778 phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH |
1779 JM_PHY_EXT_COMM_2_CALI_ENABLE;
1780 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1781 msleep(20);
1782 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1783 phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE |
1784 JM_PHY_EXT_COMM_2_CALI_MODE_0 |
1785 JM_PHY_EXT_COMM_2_CALI_LATCH);
1786 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1788 /* Disable PHY test mode */
1789 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1790 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1791 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1792 return 0;
1795 static int
1796 jme_phy_setEA(struct jme_adapter *jme)
1798 u32 phy_comm0 = 0, phy_comm1 = 0;
1799 u8 nic_ctrl;
1801 pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl);
1802 if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE)
1803 return 0;
1805 switch (jme->pdev->device) {
1806 case PCI_DEVICE_ID_JMICRON_JMC250:
1807 if (((jme->chip_main_rev == 5) &&
1808 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1809 (jme->chip_sub_rev == 3))) ||
1810 (jme->chip_main_rev >= 6)) {
1811 phy_comm0 = 0x008A;
1812 phy_comm1 = 0x4109;
1814 if ((jme->chip_main_rev == 3) &&
1815 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1816 phy_comm0 = 0xE088;
1817 break;
1818 case PCI_DEVICE_ID_JMICRON_JMC260:
1819 if (((jme->chip_main_rev == 5) &&
1820 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1821 (jme->chip_sub_rev == 3))) ||
1822 (jme->chip_main_rev >= 6)) {
1823 phy_comm0 = 0x008A;
1824 phy_comm1 = 0x4109;
1826 if ((jme->chip_main_rev == 3) &&
1827 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1828 phy_comm0 = 0xE088;
1829 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0))
1830 phy_comm0 = 0x608A;
1831 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2))
1832 phy_comm0 = 0x408A;
1833 break;
1834 default:
1835 return -ENODEV;
1837 if (phy_comm0)
1838 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0);
1839 if (phy_comm1)
1840 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1);
1842 return 0;
1845 static int
1846 jme_open(struct net_device *netdev)
1848 struct jme_adapter *jme = netdev_priv(netdev);
1849 int rc;
1851 jme_clear_pm_disable_wol(jme);
1852 JME_NAPI_ENABLE(jme);
1854 tasklet_init(&jme->linkch_task, jme_link_change_tasklet,
1855 (unsigned long) jme);
1856 tasklet_init(&jme->txclean_task, jme_tx_clean_tasklet,
1857 (unsigned long) jme);
1858 tasklet_init(&jme->rxclean_task, jme_rx_clean_tasklet,
1859 (unsigned long) jme);
1860 tasklet_init(&jme->rxempty_task, jme_rx_empty_tasklet,
1861 (unsigned long) jme);
1863 rc = jme_request_irq(jme);
1864 if (rc)
1865 goto err_out;
1867 jme_start_irq(jme);
1869 jme_phy_on(jme);
1870 if (test_bit(JME_FLAG_SSET, &jme->flags))
1871 jme_set_link_ksettings(netdev, &jme->old_cmd);
1872 else
1873 jme_reset_phy_processor(jme);
1874 jme_phy_calibration(jme);
1875 jme_phy_setEA(jme);
1876 jme_reset_link(jme);
1878 return 0;
1880 err_out:
1881 netif_stop_queue(netdev);
1882 netif_carrier_off(netdev);
1883 return rc;
1886 static void
1887 jme_set_100m_half(struct jme_adapter *jme)
1889 u32 bmcr, tmp;
1891 jme_phy_on(jme);
1892 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1893 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1894 BMCR_SPEED1000 | BMCR_FULLDPLX);
1895 tmp |= BMCR_SPEED100;
1897 if (bmcr != tmp)
1898 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1900 if (jme->fpgaver)
1901 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1902 else
1903 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1906 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1907 static void
1908 jme_wait_link(struct jme_adapter *jme)
1910 u32 phylink, to = JME_WAIT_LINK_TIME;
1912 mdelay(1000);
1913 phylink = jme_linkstat_from_phy(jme);
1914 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1915 mdelay(10);
1916 phylink = jme_linkstat_from_phy(jme);
1920 static void
1921 jme_powersave_phy(struct jme_adapter *jme)
1923 if (jme->reg_pmcs && device_may_wakeup(&jme->pdev->dev)) {
1924 jme_set_100m_half(jme);
1925 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1926 jme_wait_link(jme);
1927 jme_clear_pm_enable_wol(jme);
1928 } else {
1929 jme_phy_off(jme);
1933 static int
1934 jme_close(struct net_device *netdev)
1936 struct jme_adapter *jme = netdev_priv(netdev);
1938 netif_stop_queue(netdev);
1939 netif_carrier_off(netdev);
1941 jme_stop_irq(jme);
1942 jme_free_irq(jme);
1944 JME_NAPI_DISABLE(jme);
1946 tasklet_kill(&jme->linkch_task);
1947 tasklet_kill(&jme->txclean_task);
1948 tasklet_kill(&jme->rxclean_task);
1949 tasklet_kill(&jme->rxempty_task);
1951 jme_disable_rx_engine(jme);
1952 jme_disable_tx_engine(jme);
1953 jme_reset_mac_processor(jme);
1954 jme_free_rx_resources(jme);
1955 jme_free_tx_resources(jme);
1956 jme->phylink = 0;
1957 jme_phy_off(jme);
1959 return 0;
1962 static int
1963 jme_alloc_txdesc(struct jme_adapter *jme,
1964 struct sk_buff *skb)
1966 struct jme_ring *txring = &(jme->txring[0]);
1967 int idx, nr_alloc, mask = jme->tx_ring_mask;
1969 idx = txring->next_to_use;
1970 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1972 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1973 return -1;
1975 atomic_sub(nr_alloc, &txring->nr_free);
1977 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1979 return idx;
1982 static int
1983 jme_fill_tx_map(struct pci_dev *pdev,
1984 struct txdesc *txdesc,
1985 struct jme_buffer_info *txbi,
1986 struct page *page,
1987 u32 page_offset,
1988 u32 len,
1989 bool hidma)
1991 dma_addr_t dmaaddr;
1993 dmaaddr = pci_map_page(pdev,
1994 page,
1995 page_offset,
1996 len,
1997 PCI_DMA_TODEVICE);
1999 if (unlikely(pci_dma_mapping_error(pdev, dmaaddr)))
2000 return -EINVAL;
2002 pci_dma_sync_single_for_device(pdev,
2003 dmaaddr,
2004 len,
2005 PCI_DMA_TODEVICE);
2007 txdesc->dw[0] = 0;
2008 txdesc->dw[1] = 0;
2009 txdesc->desc2.flags = TXFLAG_OWN;
2010 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
2011 txdesc->desc2.datalen = cpu_to_le16(len);
2012 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
2013 txdesc->desc2.bufaddrl = cpu_to_le32(
2014 (__u64)dmaaddr & 0xFFFFFFFFUL);
2016 txbi->mapping = dmaaddr;
2017 txbi->len = len;
2018 return 0;
2021 static void jme_drop_tx_map(struct jme_adapter *jme, int startidx, int count)
2023 struct jme_ring *txring = &(jme->txring[0]);
2024 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2025 int mask = jme->tx_ring_mask;
2026 int j;
2028 for (j = 0 ; j < count ; j++) {
2029 ctxbi = txbi + ((startidx + j + 2) & (mask));
2030 pci_unmap_page(jme->pdev,
2031 ctxbi->mapping,
2032 ctxbi->len,
2033 PCI_DMA_TODEVICE);
2035 ctxbi->mapping = 0;
2036 ctxbi->len = 0;
2041 static int
2042 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2044 struct jme_ring *txring = &(jme->txring[0]);
2045 struct txdesc *txdesc = txring->desc, *ctxdesc;
2046 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2047 bool hidma = jme->dev->features & NETIF_F_HIGHDMA;
2048 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2049 int mask = jme->tx_ring_mask;
2050 const struct skb_frag_struct *frag;
2051 u32 len;
2052 int ret = 0;
2054 for (i = 0 ; i < nr_frags ; ++i) {
2055 frag = &skb_shinfo(skb)->frags[i];
2056 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2057 ctxbi = txbi + ((idx + i + 2) & (mask));
2059 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
2060 skb_frag_page(frag),
2061 frag->page_offset, skb_frag_size(frag), hidma);
2062 if (ret) {
2063 jme_drop_tx_map(jme, idx, i);
2064 goto out;
2069 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
2070 ctxdesc = txdesc + ((idx + 1) & (mask));
2071 ctxbi = txbi + ((idx + 1) & (mask));
2072 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2073 offset_in_page(skb->data), len, hidma);
2074 if (ret)
2075 jme_drop_tx_map(jme, idx, i);
2077 out:
2078 return ret;
2083 static int
2084 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2086 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2087 if (*mss) {
2088 *flags |= TXFLAG_LSEN;
2090 if (skb->protocol == htons(ETH_P_IP)) {
2091 struct iphdr *iph = ip_hdr(skb);
2093 iph->check = 0;
2094 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2095 iph->daddr, 0,
2096 IPPROTO_TCP,
2098 } else {
2099 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2101 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2102 &ip6h->daddr, 0,
2103 IPPROTO_TCP,
2107 return 0;
2110 return 1;
2113 static void
2114 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2116 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2117 u8 ip_proto;
2119 switch (skb->protocol) {
2120 case htons(ETH_P_IP):
2121 ip_proto = ip_hdr(skb)->protocol;
2122 break;
2123 case htons(ETH_P_IPV6):
2124 ip_proto = ipv6_hdr(skb)->nexthdr;
2125 break;
2126 default:
2127 ip_proto = 0;
2128 break;
2131 switch (ip_proto) {
2132 case IPPROTO_TCP:
2133 *flags |= TXFLAG_TCPCS;
2134 break;
2135 case IPPROTO_UDP:
2136 *flags |= TXFLAG_UDPCS;
2137 break;
2138 default:
2139 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2140 break;
2145 static inline void
2146 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2148 if (skb_vlan_tag_present(skb)) {
2149 *flags |= TXFLAG_TAGON;
2150 *vlan = cpu_to_le16(skb_vlan_tag_get(skb));
2154 static int
2155 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2157 struct jme_ring *txring = &(jme->txring[0]);
2158 struct txdesc *txdesc;
2159 struct jme_buffer_info *txbi;
2160 u8 flags;
2161 int ret = 0;
2163 txdesc = (struct txdesc *)txring->desc + idx;
2164 txbi = txring->bufinf + idx;
2166 txdesc->dw[0] = 0;
2167 txdesc->dw[1] = 0;
2168 txdesc->dw[2] = 0;
2169 txdesc->dw[3] = 0;
2170 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2172 * Set OWN bit at final.
2173 * When kernel transmit faster than NIC.
2174 * And NIC trying to send this descriptor before we tell
2175 * it to start sending this TX queue.
2176 * Other fields are already filled correctly.
2178 wmb();
2179 flags = TXFLAG_OWN | TXFLAG_INT;
2181 * Set checksum flags while not tso
2183 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2184 jme_tx_csum(jme, skb, &flags);
2185 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2186 ret = jme_map_tx_skb(jme, skb, idx);
2187 if (ret)
2188 return ret;
2190 txdesc->desc1.flags = flags;
2192 * Set tx buffer info after telling NIC to send
2193 * For better tx_clean timing
2195 wmb();
2196 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2197 txbi->skb = skb;
2198 txbi->len = skb->len;
2199 txbi->start_xmit = jiffies;
2200 if (!txbi->start_xmit)
2201 txbi->start_xmit = (0UL-1);
2203 return 0;
2206 static void
2207 jme_stop_queue_if_full(struct jme_adapter *jme)
2209 struct jme_ring *txring = &(jme->txring[0]);
2210 struct jme_buffer_info *txbi = txring->bufinf;
2211 int idx = atomic_read(&txring->next_to_clean);
2213 txbi += idx;
2215 smp_wmb();
2216 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2217 netif_stop_queue(jme->dev);
2218 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2219 smp_wmb();
2220 if (atomic_read(&txring->nr_free)
2221 >= (jme->tx_wake_threshold)) {
2222 netif_wake_queue(jme->dev);
2223 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2227 if (unlikely(txbi->start_xmit &&
2228 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2229 txbi->skb)) {
2230 netif_stop_queue(jme->dev);
2231 netif_info(jme, tx_queued, jme->dev,
2232 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2237 * This function is already protected by netif_tx_lock()
2240 static netdev_tx_t
2241 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2243 struct jme_adapter *jme = netdev_priv(netdev);
2244 int idx;
2246 if (unlikely(skb_is_gso(skb) && skb_cow_head(skb, 0))) {
2247 dev_kfree_skb_any(skb);
2248 ++(NET_STAT(jme).tx_dropped);
2249 return NETDEV_TX_OK;
2252 idx = jme_alloc_txdesc(jme, skb);
2254 if (unlikely(idx < 0)) {
2255 netif_stop_queue(netdev);
2256 netif_err(jme, tx_err, jme->dev,
2257 "BUG! Tx ring full when queue awake!\n");
2259 return NETDEV_TX_BUSY;
2262 if (jme_fill_tx_desc(jme, skb, idx))
2263 return NETDEV_TX_OK;
2265 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2266 TXCS_SELECT_QUEUE0 |
2267 TXCS_QUEUE0S |
2268 TXCS_ENABLE);
2270 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2271 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2272 jme_stop_queue_if_full(jme);
2274 return NETDEV_TX_OK;
2277 static void
2278 jme_set_unicastaddr(struct net_device *netdev)
2280 struct jme_adapter *jme = netdev_priv(netdev);
2281 u32 val;
2283 val = (netdev->dev_addr[3] & 0xff) << 24 |
2284 (netdev->dev_addr[2] & 0xff) << 16 |
2285 (netdev->dev_addr[1] & 0xff) << 8 |
2286 (netdev->dev_addr[0] & 0xff);
2287 jwrite32(jme, JME_RXUMA_LO, val);
2288 val = (netdev->dev_addr[5] & 0xff) << 8 |
2289 (netdev->dev_addr[4] & 0xff);
2290 jwrite32(jme, JME_RXUMA_HI, val);
2293 static int
2294 jme_set_macaddr(struct net_device *netdev, void *p)
2296 struct jme_adapter *jme = netdev_priv(netdev);
2297 struct sockaddr *addr = p;
2299 if (netif_running(netdev))
2300 return -EBUSY;
2302 spin_lock_bh(&jme->macaddr_lock);
2303 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2304 jme_set_unicastaddr(netdev);
2305 spin_unlock_bh(&jme->macaddr_lock);
2307 return 0;
2310 static void
2311 jme_set_multi(struct net_device *netdev)
2313 struct jme_adapter *jme = netdev_priv(netdev);
2314 u32 mc_hash[2] = {};
2316 spin_lock_bh(&jme->rxmcs_lock);
2318 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2320 if (netdev->flags & IFF_PROMISC) {
2321 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2322 } else if (netdev->flags & IFF_ALLMULTI) {
2323 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2324 } else if (netdev->flags & IFF_MULTICAST) {
2325 struct netdev_hw_addr *ha;
2326 int bit_nr;
2328 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2329 netdev_for_each_mc_addr(ha, netdev) {
2330 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2331 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2334 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2335 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2338 wmb();
2339 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2341 spin_unlock_bh(&jme->rxmcs_lock);
2344 static int
2345 jme_change_mtu(struct net_device *netdev, int new_mtu)
2347 struct jme_adapter *jme = netdev_priv(netdev);
2349 netdev->mtu = new_mtu;
2350 netdev_update_features(netdev);
2352 jme_restart_rx_engine(jme);
2353 jme_reset_link(jme);
2355 return 0;
2358 static void
2359 jme_tx_timeout(struct net_device *netdev)
2361 struct jme_adapter *jme = netdev_priv(netdev);
2363 jme->phylink = 0;
2364 jme_reset_phy_processor(jme);
2365 if (test_bit(JME_FLAG_SSET, &jme->flags))
2366 jme_set_link_ksettings(netdev, &jme->old_cmd);
2369 * Force to Reset the link again
2371 jme_reset_link(jme);
2374 static void
2375 jme_get_drvinfo(struct net_device *netdev,
2376 struct ethtool_drvinfo *info)
2378 struct jme_adapter *jme = netdev_priv(netdev);
2380 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2381 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2382 strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
2385 static int
2386 jme_get_regs_len(struct net_device *netdev)
2388 return JME_REG_LEN;
2391 static void
2392 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2394 int i;
2396 for (i = 0 ; i < len ; i += 4)
2397 p[i >> 2] = jread32(jme, reg + i);
2400 static void
2401 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2403 int i;
2404 u16 *p16 = (u16 *)p;
2406 for (i = 0 ; i < reg_nr ; ++i)
2407 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2410 static void
2411 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2413 struct jme_adapter *jme = netdev_priv(netdev);
2414 u32 *p32 = (u32 *)p;
2416 memset(p, 0xFF, JME_REG_LEN);
2418 regs->version = 1;
2419 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2421 p32 += 0x100 >> 2;
2422 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2424 p32 += 0x100 >> 2;
2425 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2427 p32 += 0x100 >> 2;
2428 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2430 p32 += 0x100 >> 2;
2431 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2434 static int
2435 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2437 struct jme_adapter *jme = netdev_priv(netdev);
2439 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2440 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2442 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2443 ecmd->use_adaptive_rx_coalesce = false;
2444 ecmd->rx_coalesce_usecs = 0;
2445 ecmd->rx_max_coalesced_frames = 0;
2446 return 0;
2449 ecmd->use_adaptive_rx_coalesce = true;
2451 switch (jme->dpi.cur) {
2452 case PCC_P1:
2453 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2454 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2455 break;
2456 case PCC_P2:
2457 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2458 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2459 break;
2460 case PCC_P3:
2461 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2462 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2463 break;
2464 default:
2465 break;
2468 return 0;
2471 static int
2472 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2474 struct jme_adapter *jme = netdev_priv(netdev);
2475 struct dynpcc_info *dpi = &(jme->dpi);
2477 if (netif_running(netdev))
2478 return -EBUSY;
2480 if (ecmd->use_adaptive_rx_coalesce &&
2481 test_bit(JME_FLAG_POLL, &jme->flags)) {
2482 clear_bit(JME_FLAG_POLL, &jme->flags);
2483 jme->jme_rx = netif_rx;
2484 dpi->cur = PCC_P1;
2485 dpi->attempt = PCC_P1;
2486 dpi->cnt = 0;
2487 jme_set_rx_pcc(jme, PCC_P1);
2488 jme_interrupt_mode(jme);
2489 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2490 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2491 set_bit(JME_FLAG_POLL, &jme->flags);
2492 jme->jme_rx = netif_receive_skb;
2493 jme_interrupt_mode(jme);
2496 return 0;
2499 static void
2500 jme_get_pauseparam(struct net_device *netdev,
2501 struct ethtool_pauseparam *ecmd)
2503 struct jme_adapter *jme = netdev_priv(netdev);
2504 u32 val;
2506 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2507 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2509 spin_lock_bh(&jme->phy_lock);
2510 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2511 spin_unlock_bh(&jme->phy_lock);
2513 ecmd->autoneg =
2514 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2517 static int
2518 jme_set_pauseparam(struct net_device *netdev,
2519 struct ethtool_pauseparam *ecmd)
2521 struct jme_adapter *jme = netdev_priv(netdev);
2522 u32 val;
2524 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2525 (ecmd->tx_pause != 0)) {
2527 if (ecmd->tx_pause)
2528 jme->reg_txpfc |= TXPFC_PF_EN;
2529 else
2530 jme->reg_txpfc &= ~TXPFC_PF_EN;
2532 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2535 spin_lock_bh(&jme->rxmcs_lock);
2536 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2537 (ecmd->rx_pause != 0)) {
2539 if (ecmd->rx_pause)
2540 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2541 else
2542 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2544 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2546 spin_unlock_bh(&jme->rxmcs_lock);
2548 spin_lock_bh(&jme->phy_lock);
2549 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2550 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2551 (ecmd->autoneg != 0)) {
2553 if (ecmd->autoneg)
2554 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2555 else
2556 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2558 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2559 MII_ADVERTISE, val);
2561 spin_unlock_bh(&jme->phy_lock);
2563 return 0;
2566 static void
2567 jme_get_wol(struct net_device *netdev,
2568 struct ethtool_wolinfo *wol)
2570 struct jme_adapter *jme = netdev_priv(netdev);
2572 wol->supported = WAKE_MAGIC | WAKE_PHY;
2574 wol->wolopts = 0;
2576 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2577 wol->wolopts |= WAKE_PHY;
2579 if (jme->reg_pmcs & PMCS_MFEN)
2580 wol->wolopts |= WAKE_MAGIC;
2584 static int
2585 jme_set_wol(struct net_device *netdev,
2586 struct ethtool_wolinfo *wol)
2588 struct jme_adapter *jme = netdev_priv(netdev);
2590 if (wol->wolopts & (WAKE_MAGICSECURE |
2591 WAKE_UCAST |
2592 WAKE_MCAST |
2593 WAKE_BCAST |
2594 WAKE_ARP))
2595 return -EOPNOTSUPP;
2597 jme->reg_pmcs = 0;
2599 if (wol->wolopts & WAKE_PHY)
2600 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2602 if (wol->wolopts & WAKE_MAGIC)
2603 jme->reg_pmcs |= PMCS_MFEN;
2605 return 0;
2608 static int
2609 jme_get_link_ksettings(struct net_device *netdev,
2610 struct ethtool_link_ksettings *cmd)
2612 struct jme_adapter *jme = netdev_priv(netdev);
2614 spin_lock_bh(&jme->phy_lock);
2615 mii_ethtool_get_link_ksettings(&jme->mii_if, cmd);
2616 spin_unlock_bh(&jme->phy_lock);
2617 return 0;
2620 static int
2621 jme_set_link_ksettings(struct net_device *netdev,
2622 const struct ethtool_link_ksettings *cmd)
2624 struct jme_adapter *jme = netdev_priv(netdev);
2625 int rc, fdc = 0;
2627 if (cmd->base.speed == SPEED_1000 &&
2628 cmd->base.autoneg != AUTONEG_ENABLE)
2629 return -EINVAL;
2632 * Check If user changed duplex only while force_media.
2633 * Hardware would not generate link change interrupt.
2635 if (jme->mii_if.force_media &&
2636 cmd->base.autoneg != AUTONEG_ENABLE &&
2637 (jme->mii_if.full_duplex != cmd->base.duplex))
2638 fdc = 1;
2640 spin_lock_bh(&jme->phy_lock);
2641 rc = mii_ethtool_set_link_ksettings(&jme->mii_if, cmd);
2642 spin_unlock_bh(&jme->phy_lock);
2644 if (!rc) {
2645 if (fdc)
2646 jme_reset_link(jme);
2647 jme->old_cmd = *cmd;
2648 set_bit(JME_FLAG_SSET, &jme->flags);
2651 return rc;
2654 static int
2655 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2657 int rc;
2658 struct jme_adapter *jme = netdev_priv(netdev);
2659 struct mii_ioctl_data *mii_data = if_mii(rq);
2660 unsigned int duplex_chg;
2662 if (cmd == SIOCSMIIREG) {
2663 u16 val = mii_data->val_in;
2664 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2665 (val & BMCR_SPEED1000))
2666 return -EINVAL;
2669 spin_lock_bh(&jme->phy_lock);
2670 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2671 spin_unlock_bh(&jme->phy_lock);
2673 if (!rc && (cmd == SIOCSMIIREG)) {
2674 if (duplex_chg)
2675 jme_reset_link(jme);
2676 jme_get_link_ksettings(netdev, &jme->old_cmd);
2677 set_bit(JME_FLAG_SSET, &jme->flags);
2680 return rc;
2683 static u32
2684 jme_get_link(struct net_device *netdev)
2686 struct jme_adapter *jme = netdev_priv(netdev);
2687 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2690 static u32
2691 jme_get_msglevel(struct net_device *netdev)
2693 struct jme_adapter *jme = netdev_priv(netdev);
2694 return jme->msg_enable;
2697 static void
2698 jme_set_msglevel(struct net_device *netdev, u32 value)
2700 struct jme_adapter *jme = netdev_priv(netdev);
2701 jme->msg_enable = value;
2704 static netdev_features_t
2705 jme_fix_features(struct net_device *netdev, netdev_features_t features)
2707 if (netdev->mtu > 1900)
2708 features &= ~(NETIF_F_ALL_TSO | NETIF_F_CSUM_MASK);
2709 return features;
2712 static int
2713 jme_set_features(struct net_device *netdev, netdev_features_t features)
2715 struct jme_adapter *jme = netdev_priv(netdev);
2717 spin_lock_bh(&jme->rxmcs_lock);
2718 if (features & NETIF_F_RXCSUM)
2719 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2720 else
2721 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2722 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2723 spin_unlock_bh(&jme->rxmcs_lock);
2725 return 0;
2728 #ifdef CONFIG_NET_POLL_CONTROLLER
2729 static void jme_netpoll(struct net_device *dev)
2731 unsigned long flags;
2733 local_irq_save(flags);
2734 jme_intr(dev->irq, dev);
2735 local_irq_restore(flags);
2737 #endif
2739 static int
2740 jme_nway_reset(struct net_device *netdev)
2742 struct jme_adapter *jme = netdev_priv(netdev);
2743 jme_restart_an(jme);
2744 return 0;
2747 static u8
2748 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2750 u32 val;
2751 int to;
2753 val = jread32(jme, JME_SMBCSR);
2754 to = JME_SMB_BUSY_TIMEOUT;
2755 while ((val & SMBCSR_BUSY) && --to) {
2756 msleep(1);
2757 val = jread32(jme, JME_SMBCSR);
2759 if (!to) {
2760 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2761 return 0xFF;
2764 jwrite32(jme, JME_SMBINTF,
2765 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2766 SMBINTF_HWRWN_READ |
2767 SMBINTF_HWCMD);
2769 val = jread32(jme, JME_SMBINTF);
2770 to = JME_SMB_BUSY_TIMEOUT;
2771 while ((val & SMBINTF_HWCMD) && --to) {
2772 msleep(1);
2773 val = jread32(jme, JME_SMBINTF);
2775 if (!to) {
2776 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2777 return 0xFF;
2780 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2783 static void
2784 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2786 u32 val;
2787 int to;
2789 val = jread32(jme, JME_SMBCSR);
2790 to = JME_SMB_BUSY_TIMEOUT;
2791 while ((val & SMBCSR_BUSY) && --to) {
2792 msleep(1);
2793 val = jread32(jme, JME_SMBCSR);
2795 if (!to) {
2796 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2797 return;
2800 jwrite32(jme, JME_SMBINTF,
2801 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2802 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2803 SMBINTF_HWRWN_WRITE |
2804 SMBINTF_HWCMD);
2806 val = jread32(jme, JME_SMBINTF);
2807 to = JME_SMB_BUSY_TIMEOUT;
2808 while ((val & SMBINTF_HWCMD) && --to) {
2809 msleep(1);
2810 val = jread32(jme, JME_SMBINTF);
2812 if (!to) {
2813 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2814 return;
2817 mdelay(2);
2820 static int
2821 jme_get_eeprom_len(struct net_device *netdev)
2823 struct jme_adapter *jme = netdev_priv(netdev);
2824 u32 val;
2825 val = jread32(jme, JME_SMBCSR);
2826 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2829 static int
2830 jme_get_eeprom(struct net_device *netdev,
2831 struct ethtool_eeprom *eeprom, u8 *data)
2833 struct jme_adapter *jme = netdev_priv(netdev);
2834 int i, offset = eeprom->offset, len = eeprom->len;
2837 * ethtool will check the boundary for us
2839 eeprom->magic = JME_EEPROM_MAGIC;
2840 for (i = 0 ; i < len ; ++i)
2841 data[i] = jme_smb_read(jme, i + offset);
2843 return 0;
2846 static int
2847 jme_set_eeprom(struct net_device *netdev,
2848 struct ethtool_eeprom *eeprom, u8 *data)
2850 struct jme_adapter *jme = netdev_priv(netdev);
2851 int i, offset = eeprom->offset, len = eeprom->len;
2853 if (eeprom->magic != JME_EEPROM_MAGIC)
2854 return -EINVAL;
2857 * ethtool will check the boundary for us
2859 for (i = 0 ; i < len ; ++i)
2860 jme_smb_write(jme, i + offset, data[i]);
2862 return 0;
2865 static const struct ethtool_ops jme_ethtool_ops = {
2866 .get_drvinfo = jme_get_drvinfo,
2867 .get_regs_len = jme_get_regs_len,
2868 .get_regs = jme_get_regs,
2869 .get_coalesce = jme_get_coalesce,
2870 .set_coalesce = jme_set_coalesce,
2871 .get_pauseparam = jme_get_pauseparam,
2872 .set_pauseparam = jme_set_pauseparam,
2873 .get_wol = jme_get_wol,
2874 .set_wol = jme_set_wol,
2875 .get_link = jme_get_link,
2876 .get_msglevel = jme_get_msglevel,
2877 .set_msglevel = jme_set_msglevel,
2878 .nway_reset = jme_nway_reset,
2879 .get_eeprom_len = jme_get_eeprom_len,
2880 .get_eeprom = jme_get_eeprom,
2881 .set_eeprom = jme_set_eeprom,
2882 .get_link_ksettings = jme_get_link_ksettings,
2883 .set_link_ksettings = jme_set_link_ksettings,
2886 static int
2887 jme_pci_dma64(struct pci_dev *pdev)
2889 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2890 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2891 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2892 return 1;
2894 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2895 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2896 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2897 return 1;
2899 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2900 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2901 return 0;
2903 return -1;
2906 static inline void
2907 jme_phy_init(struct jme_adapter *jme)
2909 u16 reg26;
2911 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2912 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2915 static inline void
2916 jme_check_hw_ver(struct jme_adapter *jme)
2918 u32 chipmode;
2920 chipmode = jread32(jme, JME_CHIPMODE);
2922 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2923 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2924 jme->chip_main_rev = jme->chiprev & 0xF;
2925 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2928 static const struct net_device_ops jme_netdev_ops = {
2929 .ndo_open = jme_open,
2930 .ndo_stop = jme_close,
2931 .ndo_validate_addr = eth_validate_addr,
2932 .ndo_do_ioctl = jme_ioctl,
2933 .ndo_start_xmit = jme_start_xmit,
2934 .ndo_set_mac_address = jme_set_macaddr,
2935 .ndo_set_rx_mode = jme_set_multi,
2936 .ndo_change_mtu = jme_change_mtu,
2937 .ndo_tx_timeout = jme_tx_timeout,
2938 .ndo_fix_features = jme_fix_features,
2939 .ndo_set_features = jme_set_features,
2940 #ifdef CONFIG_NET_POLL_CONTROLLER
2941 .ndo_poll_controller = jme_netpoll,
2942 #endif
2945 static int
2946 jme_init_one(struct pci_dev *pdev,
2947 const struct pci_device_id *ent)
2949 int rc = 0, using_dac, i;
2950 struct net_device *netdev;
2951 struct jme_adapter *jme;
2952 u16 bmcr, bmsr;
2953 u32 apmc;
2956 * set up PCI device basics
2958 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2959 PCIE_LINK_STATE_CLKPM);
2961 rc = pci_enable_device(pdev);
2962 if (rc) {
2963 pr_err("Cannot enable PCI device\n");
2964 goto err_out;
2967 using_dac = jme_pci_dma64(pdev);
2968 if (using_dac < 0) {
2969 pr_err("Cannot set PCI DMA Mask\n");
2970 rc = -EIO;
2971 goto err_out_disable_pdev;
2974 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2975 pr_err("No PCI resource region found\n");
2976 rc = -ENOMEM;
2977 goto err_out_disable_pdev;
2980 rc = pci_request_regions(pdev, DRV_NAME);
2981 if (rc) {
2982 pr_err("Cannot obtain PCI resource region\n");
2983 goto err_out_disable_pdev;
2986 pci_set_master(pdev);
2989 * alloc and init net device
2991 netdev = alloc_etherdev(sizeof(*jme));
2992 if (!netdev) {
2993 rc = -ENOMEM;
2994 goto err_out_release_regions;
2996 netdev->netdev_ops = &jme_netdev_ops;
2997 netdev->ethtool_ops = &jme_ethtool_ops;
2998 netdev->watchdog_timeo = TX_TIMEOUT;
2999 netdev->hw_features = NETIF_F_IP_CSUM |
3000 NETIF_F_IPV6_CSUM |
3001 NETIF_F_SG |
3002 NETIF_F_TSO |
3003 NETIF_F_TSO6 |
3004 NETIF_F_RXCSUM;
3005 netdev->features = NETIF_F_IP_CSUM |
3006 NETIF_F_IPV6_CSUM |
3007 NETIF_F_SG |
3008 NETIF_F_TSO |
3009 NETIF_F_TSO6 |
3010 NETIF_F_HW_VLAN_CTAG_TX |
3011 NETIF_F_HW_VLAN_CTAG_RX;
3012 if (using_dac)
3013 netdev->features |= NETIF_F_HIGHDMA;
3015 /* MTU range: 1280 - 9202*/
3016 netdev->min_mtu = IPV6_MIN_MTU;
3017 netdev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE - ETH_HLEN;
3019 SET_NETDEV_DEV(netdev, &pdev->dev);
3020 pci_set_drvdata(pdev, netdev);
3023 * init adapter info
3025 jme = netdev_priv(netdev);
3026 jme->pdev = pdev;
3027 jme->dev = netdev;
3028 jme->jme_rx = netif_rx;
3029 jme->old_mtu = netdev->mtu = 1500;
3030 jme->phylink = 0;
3031 jme->tx_ring_size = 1 << 10;
3032 jme->tx_ring_mask = jme->tx_ring_size - 1;
3033 jme->tx_wake_threshold = 1 << 9;
3034 jme->rx_ring_size = 1 << 9;
3035 jme->rx_ring_mask = jme->rx_ring_size - 1;
3036 jme->msg_enable = JME_DEF_MSG_ENABLE;
3037 jme->regs = ioremap(pci_resource_start(pdev, 0),
3038 pci_resource_len(pdev, 0));
3039 if (!(jme->regs)) {
3040 pr_err("Mapping PCI resource region error\n");
3041 rc = -ENOMEM;
3042 goto err_out_free_netdev;
3045 if (no_pseudohp) {
3046 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3047 jwrite32(jme, JME_APMC, apmc);
3048 } else if (force_pseudohp) {
3049 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3050 jwrite32(jme, JME_APMC, apmc);
3053 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, NAPI_POLL_WEIGHT)
3055 spin_lock_init(&jme->phy_lock);
3056 spin_lock_init(&jme->macaddr_lock);
3057 spin_lock_init(&jme->rxmcs_lock);
3059 atomic_set(&jme->link_changing, 1);
3060 atomic_set(&jme->rx_cleaning, 1);
3061 atomic_set(&jme->tx_cleaning, 1);
3062 atomic_set(&jme->rx_empty, 1);
3064 tasklet_init(&jme->pcc_task,
3065 jme_pcc_tasklet,
3066 (unsigned long) jme);
3067 jme->dpi.cur = PCC_P1;
3069 jme->reg_ghc = 0;
3070 jme->reg_rxcs = RXCS_DEFAULT;
3071 jme->reg_rxmcs = RXMCS_DEFAULT;
3072 jme->reg_txpfc = 0;
3073 jme->reg_pmcs = PMCS_MFEN;
3074 jme->reg_gpreg1 = GPREG1_DEFAULT;
3076 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3077 netdev->features |= NETIF_F_RXCSUM;
3080 * Get Max Read Req Size from PCI Config Space
3082 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3083 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3084 switch (jme->mrrs) {
3085 case MRRS_128B:
3086 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3087 break;
3088 case MRRS_256B:
3089 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3090 break;
3091 default:
3092 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3093 break;
3097 * Must check before reset_mac_processor
3099 jme_check_hw_ver(jme);
3100 jme->mii_if.dev = netdev;
3101 if (jme->fpgaver) {
3102 jme->mii_if.phy_id = 0;
3103 for (i = 1 ; i < 32 ; ++i) {
3104 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3105 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3106 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3107 jme->mii_if.phy_id = i;
3108 break;
3112 if (!jme->mii_if.phy_id) {
3113 rc = -EIO;
3114 pr_err("Can not find phy_id\n");
3115 goto err_out_unmap;
3118 jme->reg_ghc |= GHC_LINK_POLL;
3119 } else {
3120 jme->mii_if.phy_id = 1;
3122 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3123 jme->mii_if.supports_gmii = true;
3124 else
3125 jme->mii_if.supports_gmii = false;
3126 jme->mii_if.phy_id_mask = 0x1F;
3127 jme->mii_if.reg_num_mask = 0x1F;
3128 jme->mii_if.mdio_read = jme_mdio_read;
3129 jme->mii_if.mdio_write = jme_mdio_write;
3131 jme_clear_pm_disable_wol(jme);
3132 device_init_wakeup(&pdev->dev, true);
3134 jme_set_phyfifo_5level(jme);
3135 jme->pcirev = pdev->revision;
3136 if (!jme->fpgaver)
3137 jme_phy_init(jme);
3138 jme_phy_off(jme);
3141 * Reset MAC processor and reload EEPROM for MAC Address
3143 jme_reset_mac_processor(jme);
3144 rc = jme_reload_eeprom(jme);
3145 if (rc) {
3146 pr_err("Reload eeprom for reading MAC Address error\n");
3147 goto err_out_unmap;
3149 jme_load_macaddr(netdev);
3152 * Tell stack that we are not ready to work until open()
3154 netif_carrier_off(netdev);
3156 rc = register_netdev(netdev);
3157 if (rc) {
3158 pr_err("Cannot register net device\n");
3159 goto err_out_unmap;
3162 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3163 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3164 "JMC250 Gigabit Ethernet" :
3165 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3166 "JMC260 Fast Ethernet" : "Unknown",
3167 (jme->fpgaver != 0) ? " (FPGA)" : "",
3168 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3169 jme->pcirev, netdev->dev_addr);
3171 return 0;
3173 err_out_unmap:
3174 iounmap(jme->regs);
3175 err_out_free_netdev:
3176 free_netdev(netdev);
3177 err_out_release_regions:
3178 pci_release_regions(pdev);
3179 err_out_disable_pdev:
3180 pci_disable_device(pdev);
3181 err_out:
3182 return rc;
3185 static void
3186 jme_remove_one(struct pci_dev *pdev)
3188 struct net_device *netdev = pci_get_drvdata(pdev);
3189 struct jme_adapter *jme = netdev_priv(netdev);
3191 unregister_netdev(netdev);
3192 iounmap(jme->regs);
3193 free_netdev(netdev);
3194 pci_release_regions(pdev);
3195 pci_disable_device(pdev);
3199 static void
3200 jme_shutdown(struct pci_dev *pdev)
3202 struct net_device *netdev = pci_get_drvdata(pdev);
3203 struct jme_adapter *jme = netdev_priv(netdev);
3205 jme_powersave_phy(jme);
3206 pci_pme_active(pdev, true);
3209 #ifdef CONFIG_PM_SLEEP
3210 static int
3211 jme_suspend(struct device *dev)
3213 struct pci_dev *pdev = to_pci_dev(dev);
3214 struct net_device *netdev = pci_get_drvdata(pdev);
3215 struct jme_adapter *jme = netdev_priv(netdev);
3217 if (!netif_running(netdev))
3218 return 0;
3220 atomic_dec(&jme->link_changing);
3222 netif_device_detach(netdev);
3223 netif_stop_queue(netdev);
3224 jme_stop_irq(jme);
3226 tasklet_disable(&jme->txclean_task);
3227 tasklet_disable(&jme->rxclean_task);
3228 tasklet_disable(&jme->rxempty_task);
3230 if (netif_carrier_ok(netdev)) {
3231 if (test_bit(JME_FLAG_POLL, &jme->flags))
3232 jme_polling_mode(jme);
3234 jme_stop_pcc_timer(jme);
3235 jme_disable_rx_engine(jme);
3236 jme_disable_tx_engine(jme);
3237 jme_reset_mac_processor(jme);
3238 jme_free_rx_resources(jme);
3239 jme_free_tx_resources(jme);
3240 netif_carrier_off(netdev);
3241 jme->phylink = 0;
3244 tasklet_enable(&jme->txclean_task);
3245 tasklet_enable(&jme->rxclean_task);
3246 tasklet_enable(&jme->rxempty_task);
3248 jme_powersave_phy(jme);
3250 return 0;
3253 static int
3254 jme_resume(struct device *dev)
3256 struct pci_dev *pdev = to_pci_dev(dev);
3257 struct net_device *netdev = pci_get_drvdata(pdev);
3258 struct jme_adapter *jme = netdev_priv(netdev);
3260 if (!netif_running(netdev))
3261 return 0;
3263 jme_clear_pm_disable_wol(jme);
3264 jme_phy_on(jme);
3265 if (test_bit(JME_FLAG_SSET, &jme->flags))
3266 jme_set_link_ksettings(netdev, &jme->old_cmd);
3267 else
3268 jme_reset_phy_processor(jme);
3269 jme_phy_calibration(jme);
3270 jme_phy_setEA(jme);
3271 netif_device_attach(netdev);
3273 atomic_inc(&jme->link_changing);
3275 jme_reset_link(jme);
3277 jme_start_irq(jme);
3279 return 0;
3282 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3283 #define JME_PM_OPS (&jme_pm_ops)
3285 #else
3287 #define JME_PM_OPS NULL
3288 #endif
3290 static const struct pci_device_id jme_pci_tbl[] = {
3291 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3292 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3296 static struct pci_driver jme_driver = {
3297 .name = DRV_NAME,
3298 .id_table = jme_pci_tbl,
3299 .probe = jme_init_one,
3300 .remove = jme_remove_one,
3301 .shutdown = jme_shutdown,
3302 .driver.pm = JME_PM_OPS,
3305 static int __init
3306 jme_init_module(void)
3308 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3309 return pci_register_driver(&jme_driver);
3312 static void __exit
3313 jme_cleanup_module(void)
3315 pci_unregister_driver(&jme_driver);
3318 module_init(jme_init_module);
3319 module_exit(jme_cleanup_module);
3321 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3322 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3323 MODULE_LICENSE("GPL");
3324 MODULE_VERSION(DRV_VERSION);
3325 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);