drivers/net/ethernet/netronome/nfp/nfp_asm.h

   1 /*
   2  * Copyright (C) 2016-2017 Netronome Systems, Inc.
   3  *
   4  * This software is dual licensed under the GNU General License Version 2,
   5  * June 1991 as shown in the file COPYING in the top-level directory of this
   6  * source tree or the BSD 2-Clause License provided below.  You have the
   7  * option to license this software under the complete terms of either license.
   8  *
   9  * The BSD 2-Clause License:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      1. Redistributions of source code must retain the above
  16  *         copyright notice, this list of conditions and the following
  17  *         disclaimer.
  18  *
  19  *      2. Redistributions in binary form must reproduce the above
  20  *         copyright notice, this list of conditions and the following
  21  *         disclaimer in the documentation and/or other materials
  22  *         provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #ifndef __NFP_ASM_H__
  35 #define __NFP_ASM_H__ 1
  36
  37 #include <linux/bitfield.h>
  38 #include <linux/bug.h>
  39 #include <linux/types.h>
  40
  41 #define REG_NONE        0
  42
  43 #define RE_REG_NO_DST   0x020
  44 #define RE_REG_IMM      0x020
  45 #define RE_REG_IMM_encode(x)                                    \
  46         (RE_REG_IMM | ((x) & 0x1f) | (((x) & 0x60) << 1))
  47 #define RE_REG_IMM_MAX   0x07fULL
  48 #define RE_REG_LM       0x050
  49 #define RE_REG_LM_IDX   0x008
  50 #define RE_REG_LM_IDX_MAX       0x7
  51 #define RE_REG_XFR      0x080
  52
  53 #define UR_REG_XFR      0x180
  54 #define UR_REG_LM       0x200
  55 #define UR_REG_LM_IDX   0x020
  56 #define UR_REG_LM_POST_MOD      0x010
  57 #define UR_REG_LM_POST_MOD_DEC  0x001
  58 #define UR_REG_LM_IDX_MAX       0xf
  59 #define UR_REG_NN       0x280
  60 #define UR_REG_NO_DST   0x300
  61 #define UR_REG_IMM      UR_REG_NO_DST
  62 #define UR_REG_IMM_encode(x) (UR_REG_IMM | (x))
  63 #define UR_REG_IMM_MAX   0x0ffULL
  64
  65 #define OP_BR_BASE              0x0d800000020ULL
  66 #define OP_BR_BASE_MASK         0x0f8000c3ce0ULL
  67 #define OP_BR_MASK              0x0000000001fULL
  68 #define OP_BR_EV_PIP            0x00000000300ULL
  69 #define OP_BR_CSS               0x0000003c000ULL
  70 #define OP_BR_DEFBR             0x00000300000ULL
  71 #define OP_BR_ADDR_LO           0x007ffc00000ULL
  72 #define OP_BR_ADDR_HI           0x10000000000ULL
  73
  74 #define nfp_is_br(_insn)                                \
  75         (((_insn) & OP_BR_BASE_MASK) == OP_BR_BASE)
  76
  77 enum br_mask {
  78         BR_BEQ = 0x00,
  79         BR_BNE = 0x01,
  80         BR_BMI = 0x02,
  81         BR_BHS = 0x04,
  82         BR_BLO = 0x05,
  83         BR_BGE = 0x08,
  84         BR_BLT = 0x09,
  85         BR_UNC = 0x18,
  86 };
  87
  88 enum br_ev_pip {
  89         BR_EV_PIP_UNCOND = 0,
  90         BR_EV_PIP_COND = 1,
  91 };
  92
  93 enum br_ctx_signal_state {
  94         BR_CSS_NONE = 2,
  95 };
  96
  97 u16 br_get_offset(u64 instr);
  98 void br_set_offset(u64 *instr, u16 offset);
  99 void br_add_offset(u64 *instr, u16 offset);
 100
 101 #define OP_BBYTE_BASE           0x0c800000000ULL
 102 #define OP_BB_A_SRC             0x000000000ffULL
 103 #define OP_BB_BYTE              0x00000000300ULL
 104 #define OP_BB_B_SRC             0x0000003fc00ULL
 105 #define OP_BB_I8                0x00000040000ULL
 106 #define OP_BB_EQ                0x00000080000ULL
 107 #define OP_BB_DEFBR             0x00000300000ULL
 108 #define OP_BB_ADDR_LO           0x007ffc00000ULL
 109 #define OP_BB_ADDR_HI           0x10000000000ULL
 110 #define OP_BB_SRC_LMEXTN        0x40000000000ULL
 111
 112 #define OP_BALU_BASE            0x0e800000000ULL
 113 #define OP_BA_A_SRC             0x000000003ffULL
 114 #define OP_BA_B_SRC             0x000000ffc00ULL
 115 #define OP_BA_DEFBR             0x00000300000ULL
 116 #define OP_BA_ADDR_HI           0x0007fc00000ULL
 117
 118 #define OP_IMMED_A_SRC          0x000000003ffULL
 119 #define OP_IMMED_B_SRC          0x000000ffc00ULL
 120 #define OP_IMMED_IMM            0x0000ff00000ULL
 121 #define OP_IMMED_WIDTH          0x00060000000ULL
 122 #define OP_IMMED_INV            0x00080000000ULL
 123 #define OP_IMMED_SHIFT          0x00600000000ULL
 124 #define OP_IMMED_BASE           0x0f000000000ULL
 125 #define OP_IMMED_WR_AB          0x20000000000ULL
 126 #define OP_IMMED_SRC_LMEXTN     0x40000000000ULL
 127 #define OP_IMMED_DST_LMEXTN     0x80000000000ULL
 128
 129 enum immed_width {
 130         IMMED_WIDTH_ALL = 0,
 131         IMMED_WIDTH_BYTE = 1,
 132         IMMED_WIDTH_WORD = 2,
 133 };
 134
 135 enum immed_shift {
 136         IMMED_SHIFT_0B = 0,
 137         IMMED_SHIFT_1B = 1,
 138         IMMED_SHIFT_2B = 2,
 139 };
 140
 141 u16 immed_get_value(u64 instr);
 142 void immed_set_value(u64 *instr, u16 immed);
 143 void immed_add_value(u64 *instr, u16 offset);
 144
 145 #define OP_SHF_BASE             0x08000000000ULL
 146 #define OP_SHF_A_SRC            0x000000000ffULL
 147 #define OP_SHF_SC               0x00000000300ULL
 148 #define OP_SHF_B_SRC            0x0000003fc00ULL
 149 #define OP_SHF_I8               0x00000040000ULL
 150 #define OP_SHF_SW               0x00000080000ULL
 151 #define OP_SHF_DST              0x0000ff00000ULL
 152 #define OP_SHF_SHIFT            0x001f0000000ULL
 153 #define OP_SHF_OP               0x00e00000000ULL
 154 #define OP_SHF_DST_AB           0x01000000000ULL
 155 #define OP_SHF_WR_AB            0x20000000000ULL
 156 #define OP_SHF_SRC_LMEXTN       0x40000000000ULL
 157 #define OP_SHF_DST_LMEXTN       0x80000000000ULL
 158
 159 enum shf_op {
 160         SHF_OP_NONE = 0,
 161         SHF_OP_AND = 2,
 162         SHF_OP_OR = 5,
 163 };
 164
 165 enum shf_sc {
 166         SHF_SC_R_ROT = 0,
 167         SHF_SC_NONE = SHF_SC_R_ROT,
 168         SHF_SC_R_SHF = 1,
 169         SHF_SC_L_SHF = 2,
 170         SHF_SC_R_DSHF = 3,
 171 };
 172
 173 #define OP_ALU_A_SRC            0x000000003ffULL
 174 #define OP_ALU_B_SRC            0x000000ffc00ULL
 175 #define OP_ALU_DST              0x0003ff00000ULL
 176 #define OP_ALU_SW               0x00040000000ULL
 177 #define OP_ALU_OP               0x00f80000000ULL
 178 #define OP_ALU_DST_AB           0x01000000000ULL
 179 #define OP_ALU_BASE             0x0a000000000ULL
 180 #define OP_ALU_WR_AB            0x20000000000ULL
 181 #define OP_ALU_SRC_LMEXTN       0x40000000000ULL
 182 #define OP_ALU_DST_LMEXTN       0x80000000000ULL
 183
 184 enum alu_op {
 185         ALU_OP_NONE     = 0x00,
 186         ALU_OP_ADD      = 0x01,
 187         ALU_OP_NOT      = 0x04,
 188         ALU_OP_ADD_2B   = 0x05,
 189         ALU_OP_AND      = 0x08,
 190         ALU_OP_SUB_C    = 0x0d,
 191         ALU_OP_ADD_C    = 0x11,
 192         ALU_OP_OR       = 0x14,
 193         ALU_OP_SUB      = 0x15,
 194         ALU_OP_XOR      = 0x18,
 195 };
 196
 197 enum alu_dst_ab {
 198         ALU_DST_A = 0,
 199         ALU_DST_B = 1,
 200 };
 201
 202 #define OP_LDF_BASE             0x0c000000000ULL
 203 #define OP_LDF_A_SRC            0x000000000ffULL
 204 #define OP_LDF_SC               0x00000000300ULL
 205 #define OP_LDF_B_SRC            0x0000003fc00ULL
 206 #define OP_LDF_I8               0x00000040000ULL
 207 #define OP_LDF_SW               0x00000080000ULL
 208 #define OP_LDF_ZF               0x00000100000ULL
 209 #define OP_LDF_BMASK            0x0000f000000ULL
 210 #define OP_LDF_SHF              0x001f0000000ULL
 211 #define OP_LDF_WR_AB            0x20000000000ULL
 212 #define OP_LDF_SRC_LMEXTN       0x40000000000ULL
 213 #define OP_LDF_DST_LMEXTN       0x80000000000ULL
 214
 215 #define OP_CMD_A_SRC            0x000000000ffULL
 216 #define OP_CMD_CTX              0x00000000300ULL
 217 #define OP_CMD_B_SRC            0x0000003fc00ULL
 218 #define OP_CMD_TOKEN            0x000000c0000ULL
 219 #define OP_CMD_XFER             0x00001f00000ULL
 220 #define OP_CMD_CNT              0x0000e000000ULL
 221 #define OP_CMD_SIG              0x000f0000000ULL
 222 #define OP_CMD_TGT_CMD          0x07f00000000ULL
 223 #define OP_CMD_INDIR            0x20000000000ULL
 224 #define OP_CMD_MODE            0x1c0000000000ULL
 225
 226 struct cmd_tgt_act {
 227         u8 token;
 228         u8 tgt_cmd;
 229 };
 230
 231 enum cmd_tgt_map {
 232         CMD_TGT_READ8,
 233         CMD_TGT_WRITE8_SWAP,
 234         CMD_TGT_WRITE32_SWAP,
 235         CMD_TGT_READ32,
 236         CMD_TGT_READ32_LE,
 237         CMD_TGT_READ32_SWAP,
 238         CMD_TGT_READ_LE,
 239         CMD_TGT_READ_SWAP_LE,
 240         __CMD_TGT_MAP_SIZE,
 241 };
 242
 243 extern const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE];
 244
 245 enum cmd_mode {
 246         CMD_MODE_40b_AB = 0,
 247         CMD_MODE_40b_BA = 1,
 248         CMD_MODE_32b    = 4,
 249 };
 250
 251 enum cmd_ctx_swap {
 252         CMD_CTX_SWAP = 0,
 253         CMD_CTX_NO_SWAP = 3,
 254 };
 255
 256 #define CMD_OVE_LEN     BIT(7)
 257 #define CMD_OV_LEN      GENMASK(12, 8)
 258
 259 #define OP_LCSR_BASE            0x0fc00000000ULL
 260 #define OP_LCSR_A_SRC           0x000000003ffULL
 261 #define OP_LCSR_B_SRC           0x000000ffc00ULL
 262 #define OP_LCSR_WRITE           0x00000200000ULL
 263 #define OP_LCSR_ADDR            0x001ffc00000ULL
 264 #define OP_LCSR_SRC_LMEXTN      0x40000000000ULL
 265 #define OP_LCSR_DST_LMEXTN      0x80000000000ULL
 266
 267 enum lcsr_wr_src {
 268         LCSR_WR_AREG,
 269         LCSR_WR_BREG,
 270         LCSR_WR_IMM,
 271 };
 272
 273 #define OP_CARB_BASE            0x0e000000000ULL
 274 #define OP_CARB_OR              0x00000010000ULL
 275
 276 #define NFP_CSR_CTX_PTR         0x20
 277 #define NFP_CSR_ACT_LM_ADDR0    0x64
 278 #define NFP_CSR_ACT_LM_ADDR1    0x6c
 279 #define NFP_CSR_ACT_LM_ADDR2    0x94
 280 #define NFP_CSR_ACT_LM_ADDR3    0x9c
 281
 282 /* Software register representation, independent of operand type */
 283 #define NN_REG_TYPE     GENMASK(31, 24)
 284 #define NN_REG_LM_IDX   GENMASK(23, 22)
 285 #define NN_REG_LM_IDX_HI        BIT(23)
 286 #define NN_REG_LM_IDX_LO        BIT(22)
 287 #define NN_REG_LM_MOD   GENMASK(21, 20)
 288 #define NN_REG_VAL      GENMASK(7, 0)
 289
 290 enum nfp_bpf_reg_type {
 291         NN_REG_GPR_A =  BIT(0),
 292         NN_REG_GPR_B =  BIT(1),
 293         NN_REG_GPR_BOTH = NN_REG_GPR_A | NN_REG_GPR_B,
 294         NN_REG_NNR =    BIT(2),
 295         NN_REG_XFER =   BIT(3),
 296         NN_REG_IMM =    BIT(4),
 297         NN_REG_NONE =   BIT(5),
 298         NN_REG_LMEM =   BIT(6),
 299 };
 300
 301 enum nfp_bpf_lm_mode {
 302         NN_LM_MOD_NONE = 0,
 303         NN_LM_MOD_INC,
 304         NN_LM_MOD_DEC,
 305 };
 306
 307 #define reg_both(x)     __enc_swreg((x), NN_REG_GPR_BOTH)
 308 #define reg_a(x)        __enc_swreg((x), NN_REG_GPR_A)
 309 #define reg_b(x)        __enc_swreg((x), NN_REG_GPR_B)
 310 #define reg_nnr(x)      __enc_swreg((x), NN_REG_NNR)
 311 #define reg_xfer(x)     __enc_swreg((x), NN_REG_XFER)
 312 #define reg_imm(x)      __enc_swreg((x), NN_REG_IMM)
 313 #define reg_none()      __enc_swreg(0, NN_REG_NONE)
 314 #define reg_lm(x, off)  __enc_swreg_lm((x), NN_LM_MOD_NONE, (off))
 315 #define reg_lm_inc(x)   __enc_swreg_lm((x), NN_LM_MOD_INC, 0)
 316 #define reg_lm_dec(x)   __enc_swreg_lm((x), NN_LM_MOD_DEC, 0)
 317 #define __reg_lm(x, mod, off)   __enc_swreg_lm((x), (mod), (off))
 318
 319 typedef __u32 __bitwise swreg;
 320
 321 static inline swreg __enc_swreg(u16 id, u8 type)
 322 {
 323         return (__force swreg)(id | FIELD_PREP(NN_REG_TYPE, type));
 324 }
 325
 326 static inline swreg __enc_swreg_lm(u8 id, enum nfp_bpf_lm_mode mode, u8 off)
 327 {
 328         WARN_ON(id > 3 || (off && mode != NN_LM_MOD_NONE));
 329
 330         return (__force swreg)(FIELD_PREP(NN_REG_TYPE, NN_REG_LMEM) |
 331                                FIELD_PREP(NN_REG_LM_IDX, id) |
 332                                FIELD_PREP(NN_REG_LM_MOD, mode) |
 333                                off);
 334 }
 335
 336 static inline u32 swreg_raw(swreg reg)
 337 {
 338         return (__force u32)reg;
 339 }
 340
 341 static inline enum nfp_bpf_reg_type swreg_type(swreg reg)
 342 {
 343         return FIELD_GET(NN_REG_TYPE, swreg_raw(reg));
 344 }
 345
 346 static inline u16 swreg_value(swreg reg)
 347 {
 348         return FIELD_GET(NN_REG_VAL, swreg_raw(reg));
 349 }
 350
 351 static inline bool swreg_lm_idx(swreg reg)
 352 {
 353         return FIELD_GET(NN_REG_LM_IDX_LO, swreg_raw(reg));
 354 }
 355
 356 static inline bool swreg_lmextn(swreg reg)
 357 {
 358         return FIELD_GET(NN_REG_LM_IDX_HI, swreg_raw(reg));
 359 }
 360
 361 static inline enum nfp_bpf_lm_mode swreg_lm_mode(swreg reg)
 362 {
 363         return FIELD_GET(NN_REG_LM_MOD, swreg_raw(reg));
 364 }
 365
 366 struct nfp_insn_ur_regs {
 367         enum alu_dst_ab dst_ab;
 368         u16 dst;
 369         u16 areg, breg;
 370         bool swap;
 371         bool wr_both;
 372         bool dst_lmextn;
 373         bool src_lmextn;
 374 };
 375
 376 struct nfp_insn_re_regs {
 377         enum alu_dst_ab dst_ab;
 378         u8 dst;
 379         u8 areg, breg;
 380         bool swap;
 381         bool wr_both;
 382         bool i8;
 383         bool dst_lmextn;
 384         bool src_lmextn;
 385 };
 386
 387 int swreg_to_unrestricted(swreg dst, swreg lreg, swreg rreg,
 388                           struct nfp_insn_ur_regs *reg);
 389 int swreg_to_restricted(swreg dst, swreg lreg, swreg rreg,
 390                         struct nfp_insn_re_regs *reg, bool has_imm8);
 391
 392 #define NFP_USTORE_PREFETCH_WINDOW      8
 393
 394 int nfp_ustore_check_valid_no_ecc(u64 insn);
 395 u64 nfp_ustore_calc_ecc_insn(u64 insn);
 396
 397 #define NFP_IND_ME_REFL_WR_SIG_INIT     3
 398 #define NFP_IND_ME_CTX_PTR_BASE_MASK    GENMASK(9, 0)
 399 #define NFP_IND_NUM_CONTEXTS            8
 400
 401 static inline u32 nfp_get_ind_csr_ctx_ptr_offs(u32 read_offset)
 402 {
 403         return (read_offset & ~NFP_IND_ME_CTX_PTR_BASE_MASK) | NFP_CSR_CTX_PTR;
 404 }
 405
 406 #endif