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Linux 4.16.11
[linux/fpc-iii.git] / drivers / net / ethernet / pasemi / pasemi_mac.c
blob07a2eb3781b12a307b71849e38d8cbcb6edf1a1e
1 /*
2 * Copyright (C) 2006-2007 PA Semi, Inc
3 *
4 * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/slab.h>
22 #include <linux/interrupt.h>
23 #include <linux/dmaengine.h>
24 #include <linux/delay.h>
25 #include <linux/netdevice.h>
26 #include <linux/of_mdio.h>
27 #include <linux/etherdevice.h>
28 #include <asm/dma-mapping.h>
29 #include <linux/in.h>
30 #include <linux/skbuff.h>
31
32 #include <linux/ip.h>
33 #include <net/checksum.h>
34 #include <linux/prefetch.h>
35
36 #include <asm/irq.h>
37 #include <asm/firmware.h>
38 #include <asm/pasemi_dma.h>
39
40 #include "pasemi_mac.h"
41
42 /* We have our own align, since ppc64 in general has it at 0 because
43 * of design flaws in some of the server bridge chips. However, for
44 * PWRficient doing the unaligned copies is more expensive than doing
45 * unaligned DMA, so make sure the data is aligned instead.
46 */
47 #define LOCAL_SKB_ALIGN 2
48
49 /* TODO list
50 *
51 * - Multicast support
52 * - Large MTU support
53 * - Multiqueue RX/TX
54 */
55
56 #define PE_MIN_MTU (ETH_ZLEN + ETH_HLEN)
57 #define PE_MAX_MTU 9000
58 #define PE_DEF_MTU ETH_DATA_LEN
59
60 #define DEFAULT_MSG_ENABLE \
61 (NETIF_MSG_DRV | \
62 NETIF_MSG_PROBE | \
63 NETIF_MSG_LINK | \
64 NETIF_MSG_TIMER | \
65 NETIF_MSG_IFDOWN | \
66 NETIF_MSG_IFUP | \
67 NETIF_MSG_RX_ERR | \
68 NETIF_MSG_TX_ERR)
69
70 MODULE_LICENSE("GPL");
71 MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
72 MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
73
74 static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
75 module_param(debug, int, 0);
76 MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
77
78 extern const struct ethtool_ops pasemi_mac_ethtool_ops;
79
80 static int translation_enabled(void)
81 {
82 #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
83 return 1;
84 #else
85 return firmware_has_feature(FW_FEATURE_LPAR);
86 #endif
87 }
88
89 static void write_iob_reg(unsigned int reg, unsigned int val)
90 {
91 pasemi_write_iob_reg(reg, val);
92 }
93
94 static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg)
95 {
96 return pasemi_read_mac_reg(mac->dma_if, reg);
97 }
98
99 static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg,
100 unsigned int val)
101 {
102 pasemi_write_mac_reg(mac->dma_if, reg, val);
103 }
104
105 static unsigned int read_dma_reg(unsigned int reg)
106 {
107 return pasemi_read_dma_reg(reg);
108 }
109
110 static void write_dma_reg(unsigned int reg, unsigned int val)
111 {
112 pasemi_write_dma_reg(reg, val);
113 }
114
115 static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac)
116 {
117 return mac->rx;
118 }
119
120 static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac)
121 {
122 return mac->tx;
123 }
124
125 static inline void prefetch_skb(const struct sk_buff *skb)
126 {
127 const void *d = skb;
128
129 prefetch(d);
130 prefetch(d+64);
131 prefetch(d+128);
132 prefetch(d+192);
133 }
134
135 static int mac_to_intf(struct pasemi_mac *mac)
136 {
137 struct pci_dev *pdev = mac->pdev;
138 u32 tmp;
139 int nintf, off, i, j;
140 int devfn = pdev->devfn;
141
142 tmp = read_dma_reg(PAS_DMA_CAP_IFI);
143 nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S;
144 off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S;
145
146 /* IOFF contains the offset to the registers containing the
147 * DMA interface-to-MAC-pci-id mappings, and NIN contains number
148 * of total interfaces. Each register contains 4 devfns.
149 * Just do a linear search until we find the devfn of the MAC
150 * we're trying to look up.
151 */
152
153 for (i = 0; i < (nintf+3)/4; i++) {
154 tmp = read_dma_reg(off+4*i);
155 for (j = 0; j < 4; j++) {
156 if (((tmp >> (8*j)) & 0xff) == devfn)
157 return i*4 + j;
158 }
159 }
160 return -1;
161 }
162
163 static void pasemi_mac_intf_disable(struct pasemi_mac *mac)
164 {
165 unsigned int flags;
166
167 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
168 flags &= ~PAS_MAC_CFG_PCFG_PE;
169 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
170 }
171
172 static void pasemi_mac_intf_enable(struct pasemi_mac *mac)
173 {
174 unsigned int flags;
175
176 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
177 flags |= PAS_MAC_CFG_PCFG_PE;
178 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
179 }
180
181 static int pasemi_get_mac_addr(struct pasemi_mac *mac)
182 {
183 struct pci_dev *pdev = mac->pdev;
184 struct device_node *dn = pci_device_to_OF_node(pdev);
185 int len;
186 const u8 *maddr;
187 u8 addr[ETH_ALEN];
188
189 if (!dn) {
190 dev_dbg(&pdev->dev,
191 "No device node for mac, not configuring\n");
192 return -ENOENT;
193 }
194
195 maddr = of_get_property(dn, "local-mac-address", &len);
196
197 if (maddr && len == ETH_ALEN) {
198 memcpy(mac->mac_addr, maddr, ETH_ALEN);
199 return 0;
200 }
201
202 /* Some old versions of firmware mistakenly uses mac-address
203 * (and as a string) instead of a byte array in local-mac-address.
204 */
205
206 if (maddr == NULL)
207 maddr = of_get_property(dn, "mac-address", NULL);
208
209 if (maddr == NULL) {
210 dev_warn(&pdev->dev,
211 "no mac address in device tree, not configuring\n");
212 return -ENOENT;
213 }
214
215 if (!mac_pton(maddr, addr)) {
216 dev_warn(&pdev->dev,
217 "can't parse mac address, not configuring\n");
218 return -EINVAL;
219 }
220
221 memcpy(mac->mac_addr, addr, ETH_ALEN);
222
223 return 0;
224 }
225
226 static int pasemi_mac_set_mac_addr(struct net_device *dev, void *p)
227 {
228 struct pasemi_mac *mac = netdev_priv(dev);
229 struct sockaddr *addr = p;
230 unsigned int adr0, adr1;
231
232 if (!is_valid_ether_addr(addr->sa_data))
233 return -EADDRNOTAVAIL;
234
235 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
236
237 adr0 = dev->dev_addr[2] << 24 |
238 dev->dev_addr[3] << 16 |
239 dev->dev_addr[4] << 8 |
240 dev->dev_addr[5];
241 adr1 = read_mac_reg(mac, PAS_MAC_CFG_ADR1);
242 adr1 &= ~0xffff;
243 adr1 |= dev->dev_addr[0] << 8 | dev->dev_addr[1];
244
245 pasemi_mac_intf_disable(mac);
246 write_mac_reg(mac, PAS_MAC_CFG_ADR0, adr0);
247 write_mac_reg(mac, PAS_MAC_CFG_ADR1, adr1);
248 pasemi_mac_intf_enable(mac);
249
250 return 0;
251 }
252
253 static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
254 const int nfrags,
255 struct sk_buff *skb,
256 const dma_addr_t *dmas)
257 {
258 int f;
259 struct pci_dev *pdev = mac->dma_pdev;
260
261 pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE);
262
263 for (f = 0; f < nfrags; f++) {
264 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
265
266 pci_unmap_page(pdev, dmas[f+1], skb_frag_size(frag), PCI_DMA_TODEVICE);
267 }
268 dev_kfree_skb_irq(skb);
269
270 /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs,
271 * aligned up to a power of 2
272 */
273 return (nfrags + 3) & ~1;
274 }
275
276 static struct pasemi_mac_csring *pasemi_mac_setup_csring(struct pasemi_mac *mac)
277 {
278 struct pasemi_mac_csring *ring;
279 u32 val;
280 unsigned int cfg;
281 int chno;
282
283 ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_csring),
284 offsetof(struct pasemi_mac_csring, chan));
285
286 if (!ring) {
287 dev_err(&mac->pdev->dev, "Can't allocate checksum channel\n");
288 goto out_chan;
289 }
290
291 chno = ring->chan.chno;
292
293 ring->size = CS_RING_SIZE;
294 ring->next_to_fill = 0;
295
296 /* Allocate descriptors */
297 if (pasemi_dma_alloc_ring(&ring->chan, CS_RING_SIZE))
298 goto out_ring_desc;
299
300 write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
301 PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
302 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
303 val |= PAS_DMA_TXCHAN_BASEU_SIZ(CS_RING_SIZE >> 3);
304
305 write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
306
307 ring->events[0] = pasemi_dma_alloc_flag();
308 ring->events[1] = pasemi_dma_alloc_flag();
309 if (ring->events[0] < 0 || ring->events[1] < 0)
310 goto out_flags;
311
312 pasemi_dma_clear_flag(ring->events[0]);
313 pasemi_dma_clear_flag(ring->events[1]);
314
315 ring->fun = pasemi_dma_alloc_fun();
316 if (ring->fun < 0)
317 goto out_fun;
318
319 cfg = PAS_DMA_TXCHAN_CFG_TY_FUNC | PAS_DMA_TXCHAN_CFG_UP |
320 PAS_DMA_TXCHAN_CFG_TATTR(ring->fun) |
321 PAS_DMA_TXCHAN_CFG_LPSQ | PAS_DMA_TXCHAN_CFG_LPDQ;
322
323 if (translation_enabled())
324 cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
325
326 write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
327
328 /* enable channel */
329 pasemi_dma_start_chan(&ring->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
330 PAS_DMA_TXCHAN_TCMDSTA_DB |
331 PAS_DMA_TXCHAN_TCMDSTA_DE |
332 PAS_DMA_TXCHAN_TCMDSTA_DA);
333
334 return ring;
335
336 out_fun:
337 out_flags:
338 if (ring->events[0] >= 0)
339 pasemi_dma_free_flag(ring->events[0]);
340 if (ring->events[1] >= 0)
341 pasemi_dma_free_flag(ring->events[1]);
342 pasemi_dma_free_ring(&ring->chan);
343 out_ring_desc:
344 pasemi_dma_free_chan(&ring->chan);
345 out_chan:
346
347 return NULL;
348 }
349
350 static void pasemi_mac_setup_csrings(struct pasemi_mac *mac)
351 {
352 int i;
353 mac->cs[0] = pasemi_mac_setup_csring(mac);
354 if (mac->type == MAC_TYPE_XAUI)
355 mac->cs[1] = pasemi_mac_setup_csring(mac);
356 else
357 mac->cs[1] = 0;
358
359 for (i = 0; i < MAX_CS; i++)
360 if (mac->cs[i])
361 mac->num_cs++;
362 }
363
364 static void pasemi_mac_free_csring(struct pasemi_mac_csring *csring)
365 {
366 pasemi_dma_stop_chan(&csring->chan);
367 pasemi_dma_free_flag(csring->events[0]);
368 pasemi_dma_free_flag(csring->events[1]);
369 pasemi_dma_free_ring(&csring->chan);
370 pasemi_dma_free_chan(&csring->chan);
371 pasemi_dma_free_fun(csring->fun);
372 }
373
374 static int pasemi_mac_setup_rx_resources(const struct net_device *dev)
375 {
376 struct pasemi_mac_rxring *ring;
377 struct pasemi_mac *mac = netdev_priv(dev);
378 int chno;
379 unsigned int cfg;
380
381 ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring),
382 offsetof(struct pasemi_mac_rxring, chan));
383
384 if (!ring) {
385 dev_err(&mac->pdev->dev, "Can't allocate RX channel\n");
386 goto out_chan;
387 }
388 chno = ring->chan.chno;
389
390 spin_lock_init(&ring->lock);
391
392 ring->size = RX_RING_SIZE;
393 ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
394 RX_RING_SIZE, GFP_KERNEL);
395
396 if (!ring->ring_info)
397 goto out_ring_info;
398
399 /* Allocate descriptors */
400 if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE))
401 goto out_ring_desc;
402
403 ring->buffers = dma_zalloc_coherent(&mac->dma_pdev->dev,
404 RX_RING_SIZE * sizeof(u64),
405 &ring->buf_dma, GFP_KERNEL);
406 if (!ring->buffers)
407 goto out_ring_desc;
408
409 write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno),
410 PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma));
411
412 write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno),
413 PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) |
414 PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3));
415
416 cfg = PAS_DMA_RXCHAN_CFG_HBU(2);
417
418 if (translation_enabled())
419 cfg |= PAS_DMA_RXCHAN_CFG_CTR;
420
421 write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg);
422
423 write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if),
424 PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma));
425
426 write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if),
427 PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) |
428 PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
429
430 cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 |
431 PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP |
432 PAS_DMA_RXINT_CFG_HEN;
433
434 if (translation_enabled())
435 cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR;
436
437 write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg);
438
439 ring->next_to_fill = 0;
440 ring->next_to_clean = 0;
441 ring->mac = mac;
442 mac->rx = ring;
443
444 return 0;
445
446 out_ring_desc:
447 kfree(ring->ring_info);
448 out_ring_info:
449 pasemi_dma_free_chan(&ring->chan);
450 out_chan:
451 return -ENOMEM;
452 }
453
454 static struct pasemi_mac_txring *
455 pasemi_mac_setup_tx_resources(const struct net_device *dev)
456 {
457 struct pasemi_mac *mac = netdev_priv(dev);
458 u32 val;
459 struct pasemi_mac_txring *ring;
460 unsigned int cfg;
461 int chno;
462
463 ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring),
464 offsetof(struct pasemi_mac_txring, chan));
465
466 if (!ring) {
467 dev_err(&mac->pdev->dev, "Can't allocate TX channel\n");
468 goto out_chan;
469 }
470
471 chno = ring->chan.chno;
472
473 spin_lock_init(&ring->lock);
474
475 ring->size = TX_RING_SIZE;
476 ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
477 TX_RING_SIZE, GFP_KERNEL);
478 if (!ring->ring_info)
479 goto out_ring_info;
480
481 /* Allocate descriptors */
482 if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE))
483 goto out_ring_desc;
484
485 write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
486 PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
487 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
488 val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3);
489
490 write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
491
492 cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE |
493 PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
494 PAS_DMA_TXCHAN_CFG_UP |
495 PAS_DMA_TXCHAN_CFG_WT(4);
496
497 if (translation_enabled())
498 cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
499
500 write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
501
502 ring->next_to_fill = 0;
503 ring->next_to_clean = 0;
504 ring->mac = mac;
505
506 return ring;
507
508 out_ring_desc:
509 kfree(ring->ring_info);
510 out_ring_info:
511 pasemi_dma_free_chan(&ring->chan);
512 out_chan:
513 return NULL;
514 }
515
516 static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac)
517 {
518 struct pasemi_mac_txring *txring = tx_ring(mac);
519 unsigned int i, j;
520 struct pasemi_mac_buffer *info;
521 dma_addr_t dmas[MAX_SKB_FRAGS+1];
522 int freed, nfrags;
523 int start, limit;
524
525 start = txring->next_to_clean;
526 limit = txring->next_to_fill;
527
528 /* Compensate for when fill has wrapped and clean has not */
529 if (start > limit)
530 limit += TX_RING_SIZE;
531
532 for (i = start; i < limit; i += freed) {
533 info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)];
534 if (info->dma && info->skb) {
535 nfrags = skb_shinfo(info->skb)->nr_frags;
536 for (j = 0; j <= nfrags; j++)
537 dmas[j] = txring->ring_info[(i+1+j) &
538 (TX_RING_SIZE-1)].dma;
539 freed = pasemi_mac_unmap_tx_skb(mac, nfrags,
540 info->skb, dmas);
541 } else {
542 freed = 2;
543 }
544 }
545
546 kfree(txring->ring_info);
547 pasemi_dma_free_chan(&txring->chan);
548
549 }
550
551 static void pasemi_mac_free_rx_buffers(struct pasemi_mac *mac)
552 {
553 struct pasemi_mac_rxring *rx = rx_ring(mac);
554 unsigned int i;
555 struct pasemi_mac_buffer *info;
556
557 for (i = 0; i < RX_RING_SIZE; i++) {
558 info = &RX_DESC_INFO(rx, i);
559 if (info->skb && info->dma) {
560 pci_unmap_single(mac->dma_pdev,
561 info->dma,
562 info->skb->len,
563 PCI_DMA_FROMDEVICE);
564 dev_kfree_skb_any(info->skb);
565 }
566 info->dma = 0;
567 info->skb = NULL;
568 }
569
570 for (i = 0; i < RX_RING_SIZE; i++)
571 RX_BUFF(rx, i) = 0;
572 }
573
574 static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac)
575 {
576 pasemi_mac_free_rx_buffers(mac);
577
578 dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
579 rx_ring(mac)->buffers, rx_ring(mac)->buf_dma);
580
581 kfree(rx_ring(mac)->ring_info);
582 pasemi_dma_free_chan(&rx_ring(mac)->chan);
583 mac->rx = NULL;
584 }
585
586 static void pasemi_mac_replenish_rx_ring(struct net_device *dev,
587 const int limit)
588 {
589 const struct pasemi_mac *mac = netdev_priv(dev);
590 struct pasemi_mac_rxring *rx = rx_ring(mac);
591 int fill, count;
592
593 if (limit <= 0)
594 return;
595
596 fill = rx_ring(mac)->next_to_fill;
597 for (count = 0; count < limit; count++) {
598 struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill);
599 u64 *buff = &RX_BUFF(rx, fill);
600 struct sk_buff *skb;
601 dma_addr_t dma;
602
603 /* Entry in use? */
604 WARN_ON(*buff);
605
606 skb = netdev_alloc_skb(dev, mac->bufsz);
607 skb_reserve(skb, LOCAL_SKB_ALIGN);
608
609 if (unlikely(!skb))
610 break;
611
612 dma = pci_map_single(mac->dma_pdev, skb->data,
613 mac->bufsz - LOCAL_SKB_ALIGN,
614 PCI_DMA_FROMDEVICE);
615
616 if (unlikely(pci_dma_mapping_error(mac->dma_pdev, dma))) {
617 dev_kfree_skb_irq(info->skb);
618 break;
619 }
620
621 info->skb = skb;
622 info->dma = dma;
623 *buff = XCT_RXB_LEN(mac->bufsz) | XCT_RXB_ADDR(dma);
624 fill++;
625 }
626
627 wmb();
628
629 write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count);
630
631 rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) &
632 (RX_RING_SIZE - 1);
633 }
634
635 static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac)
636 {
637 struct pasemi_mac_rxring *rx = rx_ring(mac);
638 unsigned int reg, pcnt;
639 /* Re-enable packet count interrupts: finally
640 * ack the packet count interrupt we got in rx_intr.
641 */
642
643 pcnt = *rx->chan.status & PAS_STATUS_PCNT_M;
644
645 reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
646
647 if (*rx->chan.status & PAS_STATUS_TIMER)
648 reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
649
650 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg);
651 }
652
653 static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac)
654 {
655 unsigned int reg, pcnt;
656
657 /* Re-enable packet count interrupts */
658 pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M;
659
660 reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
661
662 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg);
663 }
664
665
666 static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac,
667 const u64 macrx)
668 {
669 unsigned int rcmdsta, ccmdsta;
670 struct pasemi_dmachan *chan = &rx_ring(mac)->chan;
671
672 if (!netif_msg_rx_err(mac))
673 return;
674
675 rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
676 ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno));
677
678 printk(KERN_ERR "pasemi_mac: rx error. macrx %016llx, rx status %llx\n",
679 macrx, *chan->status);
680
681 printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n",
682 rcmdsta, ccmdsta);
683 }
684
685 static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac,
686 const u64 mactx)
687 {
688 unsigned int cmdsta;
689 struct pasemi_dmachan *chan = &tx_ring(mac)->chan;
690
691 if (!netif_msg_tx_err(mac))
692 return;
693
694 cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno));
695
696 printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016llx, "\
697 "tx status 0x%016llx\n", mactx, *chan->status);
698
699 printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta);
700 }
701
702 static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx,
703 const int limit)
704 {
705 const struct pasemi_dmachan *chan = &rx->chan;
706 struct pasemi_mac *mac = rx->mac;
707 struct pci_dev *pdev = mac->dma_pdev;
708 unsigned int n;
709 int count, buf_index, tot_bytes, packets;
710 struct pasemi_mac_buffer *info;
711 struct sk_buff *skb;
712 unsigned int len;
713 u64 macrx, eval;
714 dma_addr_t dma;
715
716 tot_bytes = 0;
717 packets = 0;
718
719 spin_lock(&rx->lock);
720
721 n = rx->next_to_clean;
722
723 prefetch(&RX_DESC(rx, n));
724
725 for (count = 0; count < limit; count++) {
726 macrx = RX_DESC(rx, n);
727 prefetch(&RX_DESC(rx, n+4));
728
729 if ((macrx & XCT_MACRX_E) ||
730 (*chan->status & PAS_STATUS_ERROR))
731 pasemi_mac_rx_error(mac, macrx);
732
733 if (!(macrx & XCT_MACRX_O))
734 break;
735
736 info = NULL;
737
738 BUG_ON(!(macrx & XCT_MACRX_RR_8BRES));
739
740 eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >>
741 XCT_RXRES_8B_EVAL_S;
742 buf_index = eval-1;
743
744 dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M);
745 info = &RX_DESC_INFO(rx, buf_index);
746
747 skb = info->skb;
748
749 prefetch_skb(skb);
750
751 len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
752
753 pci_unmap_single(pdev, dma, mac->bufsz - LOCAL_SKB_ALIGN,
754 PCI_DMA_FROMDEVICE);
755
756 if (macrx & XCT_MACRX_CRC) {
757 /* CRC error flagged */
758 mac->netdev->stats.rx_errors++;
759 mac->netdev->stats.rx_crc_errors++;
760 /* No need to free skb, it'll be reused */
761 goto next;
762 }
763
764 info->skb = NULL;
765 info->dma = 0;
766
767 if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) {
768 skb->ip_summed = CHECKSUM_UNNECESSARY;
769 skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
770 XCT_MACRX_CSUM_S;
771 } else {
772 skb_checksum_none_assert(skb);
773 }
774
775 packets++;
776 tot_bytes += len;
777
778 /* Don't include CRC */
779 skb_put(skb, len-4);
780
781 skb->protocol = eth_type_trans(skb, mac->netdev);
782 napi_gro_receive(&mac->napi, skb);
783
784 next:
785 RX_DESC(rx, n) = 0;
786 RX_DESC(rx, n+1) = 0;
787
788 /* Need to zero it out since hardware doesn't, since the
789 * replenish loop uses it to tell when it's done.
790 */
791 RX_BUFF(rx, buf_index) = 0;
792
793 n += 4;
794 }
795
796 if (n > RX_RING_SIZE) {
797 /* Errata 5971 workaround: L2 target of headers */
798 write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0);
799 n &= (RX_RING_SIZE-1);
800 }
801
802 rx_ring(mac)->next_to_clean = n;
803
804 /* Increase is in number of 16-byte entries, and since each descriptor
805 * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with
806 * count*2.
807 */
808 write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1);
809
810 pasemi_mac_replenish_rx_ring(mac->netdev, count);
811
812 mac->netdev->stats.rx_bytes += tot_bytes;
813 mac->netdev->stats.rx_packets += packets;
814
815 spin_unlock(&rx_ring(mac)->lock);
816
817 return count;
818 }
819
820 /* Can't make this too large or we blow the kernel stack limits */
821 #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS)
822
823 static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring)
824 {
825 struct pasemi_dmachan *chan = &txring->chan;
826 struct pasemi_mac *mac = txring->mac;
827 int i, j;
828 unsigned int start, descr_count, buf_count, batch_limit;
829 unsigned int ring_limit;
830 unsigned int total_count;
831 unsigned long flags;
832 struct sk_buff *skbs[TX_CLEAN_BATCHSIZE];
833 dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1];
834 int nf[TX_CLEAN_BATCHSIZE];
835 int nr_frags;
836
837 total_count = 0;
838 batch_limit = TX_CLEAN_BATCHSIZE;
839 restart:
840 spin_lock_irqsave(&txring->lock, flags);
841
842 start = txring->next_to_clean;
843 ring_limit = txring->next_to_fill;
844
845 prefetch(&TX_DESC_INFO(txring, start+1).skb);
846
847 /* Compensate for when fill has wrapped but clean has not */
848 if (start > ring_limit)
849 ring_limit += TX_RING_SIZE;
850
851 buf_count = 0;
852 descr_count = 0;
853
854 for (i = start;
855 descr_count < batch_limit && i < ring_limit;
856 i += buf_count) {
857 u64 mactx = TX_DESC(txring, i);
858 struct sk_buff *skb;
859
860 if ((mactx & XCT_MACTX_E) ||
861 (*chan->status & PAS_STATUS_ERROR))
862 pasemi_mac_tx_error(mac, mactx);
863
864 /* Skip over control descriptors */
865 if (!(mactx & XCT_MACTX_LLEN_M)) {
866 TX_DESC(txring, i) = 0;
867 TX_DESC(txring, i+1) = 0;
868 buf_count = 2;
869 continue;
870 }
871
872 skb = TX_DESC_INFO(txring, i+1).skb;
873 nr_frags = TX_DESC_INFO(txring, i).dma;
874
875 if (unlikely(mactx & XCT_MACTX_O))
876 /* Not yet transmitted */
877 break;
878
879 buf_count = 2 + nr_frags;
880 /* Since we always fill with an even number of entries, make
881 * sure we skip any unused one at the end as well.
882 */
883 if (buf_count & 1)
884 buf_count++;
885
886 for (j = 0; j <= nr_frags; j++)
887 dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma;
888
889 skbs[descr_count] = skb;
890 nf[descr_count] = nr_frags;
891
892 TX_DESC(txring, i) = 0;
893 TX_DESC(txring, i+1) = 0;
894
895 descr_count++;
896 }
897 txring->next_to_clean = i & (TX_RING_SIZE-1);
898
899 spin_unlock_irqrestore(&txring->lock, flags);
900 netif_wake_queue(mac->netdev);
901
902 for (i = 0; i < descr_count; i++)
903 pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]);
904
905 total_count += descr_count;
906
907 /* If the batch was full, try to clean more */
908 if (descr_count == batch_limit)
909 goto restart;
910
911 return total_count;
912 }
913
914
915 static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
916 {
917 const struct pasemi_mac_rxring *rxring = data;
918 struct pasemi_mac *mac = rxring->mac;
919 const struct pasemi_dmachan *chan = &rxring->chan;
920 unsigned int reg;
921
922 if (!(*chan->status & PAS_STATUS_CAUSE_M))
923 return IRQ_NONE;
924
925 /* Don't reset packet count so it won't fire again but clear
926 * all others.
927 */
928
929 reg = 0;
930 if (*chan->status & PAS_STATUS_SOFT)
931 reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
932 if (*chan->status & PAS_STATUS_ERROR)
933 reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
934
935 napi_schedule(&mac->napi);
936
937 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg);
938
939 return IRQ_HANDLED;
940 }
941
942 #define TX_CLEAN_INTERVAL HZ
943
944 static void pasemi_mac_tx_timer(struct timer_list *t)
945 {
946 struct pasemi_mac_txring *txring = from_timer(txring, t, clean_timer);
947 struct pasemi_mac *mac = txring->mac;
948
949 pasemi_mac_clean_tx(txring);
950
951 mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL);
952
953 pasemi_mac_restart_tx_intr(mac);
954 }
955
956 static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
957 {
958 struct pasemi_mac_txring *txring = data;
959 const struct pasemi_dmachan *chan = &txring->chan;
960 struct pasemi_mac *mac = txring->mac;
961 unsigned int reg;
962
963 if (!(*chan->status & PAS_STATUS_CAUSE_M))
964 return IRQ_NONE;
965
966 reg = 0;
967
968 if (*chan->status & PAS_STATUS_SOFT)
969 reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
970 if (*chan->status & PAS_STATUS_ERROR)
971 reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
972
973 mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2);
974
975 napi_schedule(&mac->napi);
976
977 if (reg)
978 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg);
979
980 return IRQ_HANDLED;
981 }
982
983 static void pasemi_adjust_link(struct net_device *dev)
984 {
985 struct pasemi_mac *mac = netdev_priv(dev);
986 int msg;
987 unsigned int flags;
988 unsigned int new_flags;
989
990 if (!dev->phydev->link) {
991 /* If no link, MAC speed settings don't matter. Just report
992 * link down and return.
993 */
994 if (mac->link && netif_msg_link(mac))
995 printk(KERN_INFO "%s: Link is down.\n", dev->name);
996
997 netif_carrier_off(dev);
998 pasemi_mac_intf_disable(mac);
999 mac->link = 0;
1000
1001 return;
1002 } else {
1003 pasemi_mac_intf_enable(mac);
1004 netif_carrier_on(dev);
1005 }
1006
1007 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
1008 new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
1009 PAS_MAC_CFG_PCFG_TSR_M);
1010
1011 if (!dev->phydev->duplex)
1012 new_flags |= PAS_MAC_CFG_PCFG_HD;
1013
1014 switch (dev->phydev->speed) {
1015 case 1000:
1016 new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
1017 PAS_MAC_CFG_PCFG_TSR_1G;
1018 break;
1019 case 100:
1020 new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
1021 PAS_MAC_CFG_PCFG_TSR_100M;
1022 break;
1023 case 10:
1024 new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
1025 PAS_MAC_CFG_PCFG_TSR_10M;
1026 break;
1027 default:
1028 printk("Unsupported speed %d\n", dev->phydev->speed);
1029 }
1030
1031 /* Print on link or speed/duplex change */
1032 msg = mac->link != dev->phydev->link || flags != new_flags;
1033
1034 mac->duplex = dev->phydev->duplex;
1035 mac->speed = dev->phydev->speed;
1036 mac->link = dev->phydev->link;
1037
1038 if (new_flags != flags)
1039 write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags);
1040
1041 if (msg && netif_msg_link(mac))
1042 printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
1043 dev->name, mac->speed, mac->duplex ? "full" : "half");
1044 }
1045
1046 static int pasemi_mac_phy_init(struct net_device *dev)
1047 {
1048 struct pasemi_mac *mac = netdev_priv(dev);
1049 struct device_node *dn, *phy_dn;
1050 struct phy_device *phydev;
1051
1052 dn = pci_device_to_OF_node(mac->pdev);
1053 phy_dn = of_parse_phandle(dn, "phy-handle", 0);
1054 of_node_put(phy_dn);
1055
1056 mac->link = 0;
1057 mac->speed = 0;
1058 mac->duplex = -1;
1059
1060 phydev = of_phy_connect(dev, phy_dn, &pasemi_adjust_link, 0,
1061 PHY_INTERFACE_MODE_SGMII);
1062
1063 if (!phydev) {
1064 printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
1065 return -ENODEV;
1066 }
1067
1068 return 0;
1069 }
1070
1071
1072 static int pasemi_mac_open(struct net_device *dev)
1073 {
1074 struct pasemi_mac *mac = netdev_priv(dev);
1075 unsigned int flags;
1076 int i, ret;
1077
1078 flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
1079 PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
1080 PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
1081
1082 write_mac_reg(mac, PAS_MAC_CFG_TXP, flags);
1083
1084 ret = pasemi_mac_setup_rx_resources(dev);
1085 if (ret)
1086 goto out_rx_resources;
1087
1088 mac->tx = pasemi_mac_setup_tx_resources(dev);
1089
1090 if (!mac->tx)
1091 goto out_tx_ring;
1092
1093 /* We might already have allocated rings in case mtu was changed
1094 * before interface was brought up.
1095 */
1096 if (dev->mtu > 1500 && !mac->num_cs) {
1097 pasemi_mac_setup_csrings(mac);
1098 if (!mac->num_cs)
1099 goto out_tx_ring;
1100 }
1101
1102 /* Zero out rmon counters */
1103 for (i = 0; i < 32; i++)
1104 write_mac_reg(mac, PAS_MAC_RMON(i), 0);
1105
1106 /* 0x3ff with 33MHz clock is about 31us */
1107 write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG,
1108 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff));
1109
1110 write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno),
1111 PAS_IOB_DMA_RXCH_CFG_CNTTH(256));
1112
1113 write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno),
1114 PAS_IOB_DMA_TXCH_CFG_CNTTH(32));
1115
1116 write_mac_reg(mac, PAS_MAC_IPC_CHNL,
1117 PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) |
1118 PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno));
1119
1120 /* enable rx if */
1121 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1122 PAS_DMA_RXINT_RCMDSTA_EN |
1123 PAS_DMA_RXINT_RCMDSTA_DROPS_M |
1124 PAS_DMA_RXINT_RCMDSTA_BP |
1125 PAS_DMA_RXINT_RCMDSTA_OO |
1126 PAS_DMA_RXINT_RCMDSTA_BT);
1127
1128 /* enable rx channel */
1129 pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU |
1130 PAS_DMA_RXCHAN_CCMDSTA_OD |
1131 PAS_DMA_RXCHAN_CCMDSTA_FD |
1132 PAS_DMA_RXCHAN_CCMDSTA_DT);
1133
1134 /* enable tx channel */
1135 pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
1136 PAS_DMA_TXCHAN_TCMDSTA_DB |
1137 PAS_DMA_TXCHAN_TCMDSTA_DE |
1138 PAS_DMA_TXCHAN_TCMDSTA_DA);
1139
1140 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE);
1141
1142 write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno),
1143 RX_RING_SIZE>>1);
1144
1145 /* Clear out any residual packet count state from firmware */
1146 pasemi_mac_restart_rx_intr(mac);
1147 pasemi_mac_restart_tx_intr(mac);
1148
1149 flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
1150
1151 if (mac->type == MAC_TYPE_GMAC)
1152 flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
1153 else
1154 flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G;
1155
1156 /* Enable interface in MAC */
1157 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
1158
1159 ret = pasemi_mac_phy_init(dev);
1160 if (ret) {
1161 /* Since we won't get link notification, just enable RX */
1162 pasemi_mac_intf_enable(mac);
1163 if (mac->type == MAC_TYPE_GMAC) {
1164 /* Warn for missing PHY on SGMII (1Gig) ports */
1165 dev_warn(&mac->pdev->dev,
1166 "PHY init failed: %d.\n", ret);
1167 dev_warn(&mac->pdev->dev,
1168 "Defaulting to 1Gbit full duplex\n");
1169 }
1170 }
1171
1172 netif_start_queue(dev);
1173 napi_enable(&mac->napi);
1174
1175 snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx",
1176 dev->name);
1177
1178 ret = request_irq(mac->tx->chan.irq, pasemi_mac_tx_intr, 0,
1179 mac->tx_irq_name, mac->tx);
1180 if (ret) {
1181 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
1182 mac->tx->chan.irq, ret);
1183 goto out_tx_int;
1184 }
1185
1186 snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx",
1187 dev->name);
1188
1189 ret = request_irq(mac->rx->chan.irq, pasemi_mac_rx_intr, 0,
1190 mac->rx_irq_name, mac->rx);
1191 if (ret) {
1192 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
1193 mac->rx->chan.irq, ret);
1194 goto out_rx_int;
1195 }
1196
1197 if (dev->phydev)
1198 phy_start(dev->phydev);
1199
1200 timer_setup(&mac->tx->clean_timer, pasemi_mac_tx_timer, 0);
1201 mod_timer(&mac->tx->clean_timer, jiffies + HZ);
1202
1203 return 0;
1204
1205 out_rx_int:
1206 free_irq(mac->tx->chan.irq, mac->tx);
1207 out_tx_int:
1208 napi_disable(&mac->napi);
1209 netif_stop_queue(dev);
1210 out_tx_ring:
1211 if (mac->tx)
1212 pasemi_mac_free_tx_resources(mac);
1213 pasemi_mac_free_rx_resources(mac);
1214 out_rx_resources:
1215
1216 return ret;
1217 }
1218
1219 #define MAX_RETRIES 5000
1220
1221 static void pasemi_mac_pause_txchan(struct pasemi_mac *mac)
1222 {
1223 unsigned int sta, retries;
1224 int txch = tx_ring(mac)->chan.chno;
1225
1226 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch),
1227 PAS_DMA_TXCHAN_TCMDSTA_ST);
1228
1229 for (retries = 0; retries < MAX_RETRIES; retries++) {
1230 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
1231 if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT))
1232 break;
1233 cond_resched();
1234 }
1235
1236 if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)
1237 dev_err(&mac->dma_pdev->dev,
1238 "Failed to stop tx channel, tcmdsta %08x\n", sta);
1239
1240 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0);
1241 }
1242
1243 static void pasemi_mac_pause_rxchan(struct pasemi_mac *mac)
1244 {
1245 unsigned int sta, retries;
1246 int rxch = rx_ring(mac)->chan.chno;
1247
1248 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch),
1249 PAS_DMA_RXCHAN_CCMDSTA_ST);
1250 for (retries = 0; retries < MAX_RETRIES; retries++) {
1251 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
1252 if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT))
1253 break;
1254 cond_resched();
1255 }
1256
1257 if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)
1258 dev_err(&mac->dma_pdev->dev,
1259 "Failed to stop rx channel, ccmdsta 08%x\n", sta);
1260 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0);
1261 }
1262
1263 static void pasemi_mac_pause_rxint(struct pasemi_mac *mac)
1264 {
1265 unsigned int sta, retries;
1266
1267 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1268 PAS_DMA_RXINT_RCMDSTA_ST);
1269 for (retries = 0; retries < MAX_RETRIES; retries++) {
1270 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1271 if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT))
1272 break;
1273 cond_resched();
1274 }
1275
1276 if (sta & PAS_DMA_RXINT_RCMDSTA_ACT)
1277 dev_err(&mac->dma_pdev->dev,
1278 "Failed to stop rx interface, rcmdsta %08x\n", sta);
1279 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
1280 }
1281
1282 static int pasemi_mac_close(struct net_device *dev)
1283 {
1284 struct pasemi_mac *mac = netdev_priv(dev);
1285 unsigned int sta;
1286 int rxch, txch, i;
1287
1288 rxch = rx_ring(mac)->chan.chno;
1289 txch = tx_ring(mac)->chan.chno;
1290
1291 if (dev->phydev) {
1292 phy_stop(dev->phydev);
1293 phy_disconnect(dev->phydev);
1294 }
1295
1296 del_timer_sync(&mac->tx->clean_timer);
1297
1298 netif_stop_queue(dev);
1299 napi_disable(&mac->napi);
1300
1301 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1302 if (sta & (PAS_DMA_RXINT_RCMDSTA_BP |
1303 PAS_DMA_RXINT_RCMDSTA_OO |
1304 PAS_DMA_RXINT_RCMDSTA_BT))
1305 printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta);
1306
1307 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
1308 if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU |
1309 PAS_DMA_RXCHAN_CCMDSTA_OD |
1310 PAS_DMA_RXCHAN_CCMDSTA_FD |
1311 PAS_DMA_RXCHAN_CCMDSTA_DT))
1312 printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta);
1313
1314 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
1315 if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB |
1316 PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA))
1317 printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta);
1318
1319 /* Clean out any pending buffers */
1320 pasemi_mac_clean_tx(tx_ring(mac));
1321 pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
1322
1323 pasemi_mac_pause_txchan(mac);
1324 pasemi_mac_pause_rxint(mac);
1325 pasemi_mac_pause_rxchan(mac);
1326 pasemi_mac_intf_disable(mac);
1327
1328 free_irq(mac->tx->chan.irq, mac->tx);
1329 free_irq(mac->rx->chan.irq, mac->rx);
1330
1331 for (i = 0; i < mac->num_cs; i++) {
1332 pasemi_mac_free_csring(mac->cs[i]);
1333 mac->cs[i] = NULL;
1334 }
1335
1336 mac->num_cs = 0;
1337
1338 /* Free resources */
1339 pasemi_mac_free_rx_resources(mac);
1340 pasemi_mac_free_tx_resources(mac);
1341
1342 return 0;
1343 }
1344
1345 static void pasemi_mac_queue_csdesc(const struct sk_buff *skb,
1346 const dma_addr_t *map,
1347 const unsigned int *map_size,
1348 struct pasemi_mac_txring *txring,
1349 struct pasemi_mac_csring *csring)
1350 {
1351 u64 fund;
1352 dma_addr_t cs_dest;
1353 const int nh_off = skb_network_offset(skb);
1354 const int nh_len = skb_network_header_len(skb);
1355 const int nfrags = skb_shinfo(skb)->nr_frags;
1356 int cs_size, i, fill, hdr, cpyhdr, evt;
1357 dma_addr_t csdma;
1358
1359 fund = XCT_FUN_ST | XCT_FUN_RR_8BRES |
1360 XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
1361 XCT_FUN_CRM_SIG | XCT_FUN_LLEN(skb->len - nh_off) |
1362 XCT_FUN_SHL(nh_len >> 2) | XCT_FUN_SE;
1363
1364 switch (ip_hdr(skb)->protocol) {
1365 case IPPROTO_TCP:
1366 fund |= XCT_FUN_SIG_TCP4;
1367 /* TCP checksum is 16 bytes into the header */
1368 cs_dest = map[0] + skb_transport_offset(skb) + 16;
1369 break;
1370 case IPPROTO_UDP:
1371 fund |= XCT_FUN_SIG_UDP4;
1372 /* UDP checksum is 6 bytes into the header */
1373 cs_dest = map[0] + skb_transport_offset(skb) + 6;
1374 break;
1375 default:
1376 BUG();
1377 }
1378
1379 /* Do the checksum offloaded */
1380 fill = csring->next_to_fill;
1381 hdr = fill;
1382
1383 CS_DESC(csring, fill++) = fund;
1384 /* Room for 8BRES. Checksum result is really 2 bytes into it */
1385 csdma = csring->chan.ring_dma + (fill & (CS_RING_SIZE-1)) * 8 + 2;
1386 CS_DESC(csring, fill++) = 0;
1387
1388 CS_DESC(csring, fill) = XCT_PTR_LEN(map_size[0]-nh_off) | XCT_PTR_ADDR(map[0]+nh_off);
1389 for (i = 1; i <= nfrags; i++)
1390 CS_DESC(csring, fill+i) = XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
1391
1392 fill += i;
1393 if (fill & 1)
1394 fill++;
1395
1396 /* Copy the result into the TCP packet */
1397 cpyhdr = fill;
1398 CS_DESC(csring, fill++) = XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
1399 XCT_FUN_LLEN(2) | XCT_FUN_SE;
1400 CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(cs_dest) | XCT_PTR_T;
1401 CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(csdma);
1402 fill++;
1403
1404 evt = !csring->last_event;
1405 csring->last_event = evt;
1406
1407 /* Event handshaking with MAC TX */
1408 CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1409 CTRL_CMD_ETYPE_SET | CTRL_CMD_REG(csring->events[evt]);
1410 CS_DESC(csring, fill++) = 0;
1411 CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1412 CTRL_CMD_ETYPE_WCLR | CTRL_CMD_REG(csring->events[!evt]);
1413 CS_DESC(csring, fill++) = 0;
1414 csring->next_to_fill = fill & (CS_RING_SIZE-1);
1415
1416 cs_size = fill - hdr;
1417 write_dma_reg(PAS_DMA_TXCHAN_INCR(csring->chan.chno), (cs_size) >> 1);
1418
1419 /* TX-side event handshaking */
1420 fill = txring->next_to_fill;
1421 TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1422 CTRL_CMD_ETYPE_WSET | CTRL_CMD_REG(csring->events[evt]);
1423 TX_DESC(txring, fill++) = 0;
1424 TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1425 CTRL_CMD_ETYPE_CLR | CTRL_CMD_REG(csring->events[!evt]);
1426 TX_DESC(txring, fill++) = 0;
1427 txring->next_to_fill = fill;
1428
1429 write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2);
1430 }
1431
1432 static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
1433 {
1434 struct pasemi_mac * const mac = netdev_priv(dev);
1435 struct pasemi_mac_txring * const txring = tx_ring(mac);
1436 struct pasemi_mac_csring *csring;
1437 u64 dflags = 0;
1438 u64 mactx;
1439 dma_addr_t map[MAX_SKB_FRAGS+1];
1440 unsigned int map_size[MAX_SKB_FRAGS+1];
1441 unsigned long flags;
1442 int i, nfrags;
1443 int fill;
1444 const int nh_off = skb_network_offset(skb);
1445 const int nh_len = skb_network_header_len(skb);
1446
1447 prefetch(&txring->ring_info);
1448
1449 dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD;
1450
1451 nfrags = skb_shinfo(skb)->nr_frags;
1452
1453 map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb),
1454 PCI_DMA_TODEVICE);
1455 map_size[0] = skb_headlen(skb);
1456 if (pci_dma_mapping_error(mac->dma_pdev, map[0]))
1457 goto out_err_nolock;
1458
1459 for (i = 0; i < nfrags; i++) {
1460 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1461
1462 map[i + 1] = skb_frag_dma_map(&mac->dma_pdev->dev, frag, 0,
1463 skb_frag_size(frag), DMA_TO_DEVICE);
1464 map_size[i+1] = skb_frag_size(frag);
1465 if (dma_mapping_error(&mac->dma_pdev->dev, map[i + 1])) {
1466 nfrags = i;
1467 goto out_err_nolock;
1468 }
1469 }
1470
1471 if (skb->ip_summed == CHECKSUM_PARTIAL && skb->len <= 1540) {
1472 switch (ip_hdr(skb)->protocol) {
1473 case IPPROTO_TCP:
1474 dflags |= XCT_MACTX_CSUM_TCP;
1475 dflags |= XCT_MACTX_IPH(nh_len >> 2);
1476 dflags |= XCT_MACTX_IPO(nh_off);
1477 break;
1478 case IPPROTO_UDP:
1479 dflags |= XCT_MACTX_CSUM_UDP;
1480 dflags |= XCT_MACTX_IPH(nh_len >> 2);
1481 dflags |= XCT_MACTX_IPO(nh_off);
1482 break;
1483 default:
1484 WARN_ON(1);
1485 }
1486 }
1487
1488 mactx = dflags | XCT_MACTX_LLEN(skb->len);
1489
1490 spin_lock_irqsave(&txring->lock, flags);
1491
1492 /* Avoid stepping on the same cache line that the DMA controller
1493 * is currently about to send, so leave at least 8 words available.
1494 * Total free space needed is mactx + fragments + 8
1495 */
1496 if (RING_AVAIL(txring) < nfrags + 14) {
1497 /* no room -- stop the queue and wait for tx intr */
1498 netif_stop_queue(dev);
1499 goto out_err;
1500 }
1501
1502 /* Queue up checksum + event descriptors, if needed */
1503 if (mac->num_cs && skb->ip_summed == CHECKSUM_PARTIAL && skb->len > 1540) {
1504 csring = mac->cs[mac->last_cs];
1505 mac->last_cs = (mac->last_cs + 1) % mac->num_cs;
1506
1507 pasemi_mac_queue_csdesc(skb, map, map_size, txring, csring);
1508 }
1509
1510 fill = txring->next_to_fill;
1511 TX_DESC(txring, fill) = mactx;
1512 TX_DESC_INFO(txring, fill).dma = nfrags;
1513 fill++;
1514 TX_DESC_INFO(txring, fill).skb = skb;
1515 for (i = 0; i <= nfrags; i++) {
1516 TX_DESC(txring, fill+i) =
1517 XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
1518 TX_DESC_INFO(txring, fill+i).dma = map[i];
1519 }
1520
1521 /* We have to add an even number of 8-byte entries to the ring
1522 * even if the last one is unused. That means always an odd number
1523 * of pointers + one mactx descriptor.
1524 */
1525 if (nfrags & 1)
1526 nfrags++;
1527
1528 txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1);
1529
1530 dev->stats.tx_packets++;
1531 dev->stats.tx_bytes += skb->len;
1532
1533 spin_unlock_irqrestore(&txring->lock, flags);
1534
1535 write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1);
1536
1537 return NETDEV_TX_OK;
1538
1539 out_err:
1540 spin_unlock_irqrestore(&txring->lock, flags);
1541 out_err_nolock:
1542 while (nfrags--)
1543 pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags],
1544 PCI_DMA_TODEVICE);
1545
1546 return NETDEV_TX_BUSY;
1547 }
1548
1549 static void pasemi_mac_set_rx_mode(struct net_device *dev)
1550 {
1551 const struct pasemi_mac *mac = netdev_priv(dev);
1552 unsigned int flags;
1553
1554 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
1555
1556 /* Set promiscuous */
1557 if (dev->flags & IFF_PROMISC)
1558 flags |= PAS_MAC_CFG_PCFG_PR;
1559 else
1560 flags &= ~PAS_MAC_CFG_PCFG_PR;
1561
1562 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
1563 }
1564
1565
1566 static int pasemi_mac_poll(struct napi_struct *napi, int budget)
1567 {
1568 struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi);
1569 int pkts;
1570
1571 pasemi_mac_clean_tx(tx_ring(mac));
1572 pkts = pasemi_mac_clean_rx(rx_ring(mac), budget);
1573 if (pkts < budget) {
1574 /* all done, no more packets present */
1575 napi_complete_done(napi, pkts);
1576
1577 pasemi_mac_restart_rx_intr(mac);
1578 pasemi_mac_restart_tx_intr(mac);
1579 }
1580 return pkts;
1581 }
1582
1583 #ifdef CONFIG_NET_POLL_CONTROLLER
1584 /*
1585 * Polling 'interrupt' - used by things like netconsole to send skbs
1586 * without having to re-enable interrupts. It's not called while
1587 * the interrupt routine is executing.
1588 */
1589 static void pasemi_mac_netpoll(struct net_device *dev)
1590 {
1591 const struct pasemi_mac *mac = netdev_priv(dev);
1592
1593 disable_irq(mac->tx->chan.irq);
1594 pasemi_mac_tx_intr(mac->tx->chan.irq, mac->tx);
1595 enable_irq(mac->tx->chan.irq);
1596
1597 disable_irq(mac->rx->chan.irq);
1598 pasemi_mac_rx_intr(mac->rx->chan.irq, mac->rx);
1599 enable_irq(mac->rx->chan.irq);
1600 }
1601 #endif
1602
1603 static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu)
1604 {
1605 struct pasemi_mac *mac = netdev_priv(dev);
1606 unsigned int reg;
1607 unsigned int rcmdsta = 0;
1608 int running;
1609 int ret = 0;
1610
1611 running = netif_running(dev);
1612
1613 if (running) {
1614 /* Need to stop the interface, clean out all already
1615 * received buffers, free all unused buffers on the RX
1616 * interface ring, then finally re-fill the rx ring with
1617 * the new-size buffers and restart.
1618 */
1619
1620 napi_disable(&mac->napi);
1621 netif_tx_disable(dev);
1622 pasemi_mac_intf_disable(mac);
1623
1624 rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1625 pasemi_mac_pause_rxint(mac);
1626 pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
1627 pasemi_mac_free_rx_buffers(mac);
1628
1629 }
1630
1631 /* Setup checksum channels if large MTU and none already allocated */
1632 if (new_mtu > PE_DEF_MTU && !mac->num_cs) {
1633 pasemi_mac_setup_csrings(mac);
1634 if (!mac->num_cs) {
1635 ret = -ENOMEM;
1636 goto out;
1637 }
1638 }
1639
1640 /* Change maxf, i.e. what size frames are accepted.
1641 * Need room for ethernet header and CRC word
1642 */
1643 reg = read_mac_reg(mac, PAS_MAC_CFG_MACCFG);
1644 reg &= ~PAS_MAC_CFG_MACCFG_MAXF_M;
1645 reg |= PAS_MAC_CFG_MACCFG_MAXF(new_mtu + ETH_HLEN + 4);
1646 write_mac_reg(mac, PAS_MAC_CFG_MACCFG, reg);
1647
1648 dev->mtu = new_mtu;
1649 /* MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
1650 mac->bufsz = new_mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128;
1651
1652 out:
1653 if (running) {
1654 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1655 rcmdsta | PAS_DMA_RXINT_RCMDSTA_EN);
1656
1657 rx_ring(mac)->next_to_fill = 0;
1658 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE-1);
1659
1660 napi_enable(&mac->napi);
1661 netif_start_queue(dev);
1662 pasemi_mac_intf_enable(mac);
1663 }
1664
1665 return ret;
1666 }
1667
1668 static const struct net_device_ops pasemi_netdev_ops = {
1669 .ndo_open = pasemi_mac_open,
1670 .ndo_stop = pasemi_mac_close,
1671 .ndo_start_xmit = pasemi_mac_start_tx,
1672 .ndo_set_rx_mode = pasemi_mac_set_rx_mode,
1673 .ndo_set_mac_address = pasemi_mac_set_mac_addr,
1674 .ndo_change_mtu = pasemi_mac_change_mtu,
1675 .ndo_validate_addr = eth_validate_addr,
1676 #ifdef CONFIG_NET_POLL_CONTROLLER
1677 .ndo_poll_controller = pasemi_mac_netpoll,
1678 #endif
1679 };
1680
1681 static int
1682 pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1683 {
1684 struct net_device *dev;
1685 struct pasemi_mac *mac;
1686 int err, ret;
1687
1688 err = pci_enable_device(pdev);
1689 if (err)
1690 return err;
1691
1692 dev = alloc_etherdev(sizeof(struct pasemi_mac));
1693 if (dev == NULL) {
1694 err = -ENOMEM;
1695 goto out_disable_device;
1696 }
1697
1698 pci_set_drvdata(pdev, dev);
1699 SET_NETDEV_DEV(dev, &pdev->dev);
1700
1701 mac = netdev_priv(dev);
1702
1703 mac->pdev = pdev;
1704 mac->netdev = dev;
1705
1706 netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64);
1707
1708 dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG |
1709 NETIF_F_HIGHDMA | NETIF_F_GSO;
1710
1711 mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
1712 if (!mac->dma_pdev) {
1713 dev_err(&mac->pdev->dev, "Can't find DMA Controller\n");
1714 err = -ENODEV;
1715 goto out;
1716 }
1717
1718 mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
1719 if (!mac->iob_pdev) {
1720 dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n");
1721 err = -ENODEV;
1722 goto out;
1723 }
1724
1725 /* get mac addr from device tree */
1726 if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
1727 err = -ENODEV;
1728 goto out;
1729 }
1730 memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
1731
1732 ret = mac_to_intf(mac);
1733 if (ret < 0) {
1734 dev_err(&mac->pdev->dev, "Can't map DMA interface\n");
1735 err = -ENODEV;
1736 goto out;
1737 }
1738 mac->dma_if = ret;
1739
1740 switch (pdev->device) {
1741 case 0xa005:
1742 mac->type = MAC_TYPE_GMAC;
1743 break;
1744 case 0xa006:
1745 mac->type = MAC_TYPE_XAUI;
1746 break;
1747 default:
1748 err = -ENODEV;
1749 goto out;
1750 }
1751
1752 dev->netdev_ops = &pasemi_netdev_ops;
1753 dev->mtu = PE_DEF_MTU;
1754
1755 /* MTU range: 64 - 9000 */
1756 dev->min_mtu = PE_MIN_MTU;
1757 dev->max_mtu = PE_MAX_MTU;
1758
1759 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
1760 mac->bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128;
1761
1762 dev->ethtool_ops = &pasemi_mac_ethtool_ops;
1763
1764 if (err)
1765 goto out;
1766
1767 mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1768
1769 /* Enable most messages by default */
1770 mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1771
1772 err = register_netdev(dev);
1773
1774 if (err) {
1775 dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
1776 err);
1777 goto out;
1778 } else if (netif_msg_probe(mac)) {
1779 printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %pM\n",
1780 dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
1781 mac->dma_if, dev->dev_addr);
1782 }
1783
1784 return err;
1785
1786 out:
1787 pci_dev_put(mac->iob_pdev);
1788 pci_dev_put(mac->dma_pdev);
1789
1790 free_netdev(dev);
1791 out_disable_device:
1792 pci_disable_device(pdev);
1793 return err;
1794
1795 }
1796
1797 static void pasemi_mac_remove(struct pci_dev *pdev)
1798 {
1799 struct net_device *netdev = pci_get_drvdata(pdev);
1800 struct pasemi_mac *mac;
1801
1802 if (!netdev)
1803 return;
1804
1805 mac = netdev_priv(netdev);
1806
1807 unregister_netdev(netdev);
1808
1809 pci_disable_device(pdev);
1810 pci_dev_put(mac->dma_pdev);
1811 pci_dev_put(mac->iob_pdev);
1812
1813 pasemi_dma_free_chan(&mac->tx->chan);
1814 pasemi_dma_free_chan(&mac->rx->chan);
1815
1816 free_netdev(netdev);
1817 }
1818
1819 static const struct pci_device_id pasemi_mac_pci_tbl[] = {
1820 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
1821 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
1822 { },
1823 };
1824
1825 MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
1826
1827 static struct pci_driver pasemi_mac_driver = {
1828 .name = "pasemi_mac",
1829 .id_table = pasemi_mac_pci_tbl,
1830 .probe = pasemi_mac_probe,
1831 .remove = pasemi_mac_remove,
1832 };
1833
1834 static void __exit pasemi_mac_cleanup_module(void)
1835 {
1836 pci_unregister_driver(&pasemi_mac_driver);
1837 }
1838
1839 int pasemi_mac_init_module(void)
1840 {
1841 int err;
1842
1843 err = pasemi_dma_init();
1844 if (err)
1845 return err;
1846
1847 return pci_register_driver(&pasemi_mac_driver);
1848 }
1849
1850 module_init(pasemi_mac_init_module);
1851 module_exit(pasemi_mac_cleanup_module);
Linux with added FPC-III support