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Linux 4.16.11
[linux/fpc-iii.git] / drivers / net / ethernet / sfc / farch.c
blob266b9bee1f3a75264a4f03d833864fab0ca472fa
1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/seq_file.h>
17 #include <linux/crc32.h>
18 #include "net_driver.h"
19 #include "bitfield.h"
20 #include "efx.h"
21 #include "nic.h"
22 #include "farch_regs.h"
23 #include "sriov.h"
24 #include "siena_sriov.h"
25 #include "io.h"
26 #include "workarounds.h"
27
28 /* Falcon-architecture (SFC9000-family) support */
29
30 /**************************************************************************
31 *
32 * Configurable values
33 *
34 **************************************************************************
35 */
36
37 /* This is set to 16 for a good reason. In summary, if larger than
38 * 16, the descriptor cache holds more than a default socket
39 * buffer's worth of packets (for UDP we can only have at most one
40 * socket buffer's worth outstanding). This combined with the fact
41 * that we only get 1 TX event per descriptor cache means the NIC
42 * goes idle.
43 */
44 #define TX_DC_ENTRIES 16
45 #define TX_DC_ENTRIES_ORDER 1
46
47 #define RX_DC_ENTRIES 64
48 #define RX_DC_ENTRIES_ORDER 3
49
50 /* If EFX_MAX_INT_ERRORS internal errors occur within
51 * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
52 * disable it.
53 */
54 #define EFX_INT_ERROR_EXPIRE 3600
55 #define EFX_MAX_INT_ERRORS 5
56
57 /* Depth of RX flush request fifo */
58 #define EFX_RX_FLUSH_COUNT 4
59
60 /* Driver generated events */
61 #define _EFX_CHANNEL_MAGIC_TEST 0x000101
62 #define _EFX_CHANNEL_MAGIC_FILL 0x000102
63 #define _EFX_CHANNEL_MAGIC_RX_DRAIN 0x000103
64 #define _EFX_CHANNEL_MAGIC_TX_DRAIN 0x000104
65
66 #define _EFX_CHANNEL_MAGIC(_code, _data) ((_code) << 8 | (_data))
67 #define _EFX_CHANNEL_MAGIC_CODE(_magic) ((_magic) >> 8)
68
69 #define EFX_CHANNEL_MAGIC_TEST(_channel) \
70 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TEST, (_channel)->channel)
71 #define EFX_CHANNEL_MAGIC_FILL(_rx_queue) \
72 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_FILL, \
73 efx_rx_queue_index(_rx_queue))
74 #define EFX_CHANNEL_MAGIC_RX_DRAIN(_rx_queue) \
75 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_RX_DRAIN, \
76 efx_rx_queue_index(_rx_queue))
77 #define EFX_CHANNEL_MAGIC_TX_DRAIN(_tx_queue) \
78 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TX_DRAIN, \
79 (_tx_queue)->queue)
80
81 static void efx_farch_magic_event(struct efx_channel *channel, u32 magic);
82
83 /**************************************************************************
84 *
85 * Hardware access
86 *
87 **************************************************************************/
88
89 static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
90 unsigned int index)
91 {
92 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
93 value, index);
94 }
95
96 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
97 const efx_oword_t *mask)
98 {
99 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
100 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
101 }
102
103 int efx_farch_test_registers(struct efx_nic *efx,
104 const struct efx_farch_register_test *regs,
105 size_t n_regs)
106 {
107 unsigned address = 0;
108 int i, j;
109 efx_oword_t mask, imask, original, reg, buf;
110
111 for (i = 0; i < n_regs; ++i) {
112 address = regs[i].address;
113 mask = imask = regs[i].mask;
114 EFX_INVERT_OWORD(imask);
115
116 efx_reado(efx, &original, address);
117
118 /* bit sweep on and off */
119 for (j = 0; j < 128; j++) {
120 if (!EFX_EXTRACT_OWORD32(mask, j, j))
121 continue;
122
123 /* Test this testable bit can be set in isolation */
124 EFX_AND_OWORD(reg, original, mask);
125 EFX_SET_OWORD32(reg, j, j, 1);
126
127 efx_writeo(efx, &reg, address);
128 efx_reado(efx, &buf, address);
129
130 if (efx_masked_compare_oword(&reg, &buf, &mask))
131 goto fail;
132
133 /* Test this testable bit can be cleared in isolation */
134 EFX_OR_OWORD(reg, original, mask);
135 EFX_SET_OWORD32(reg, j, j, 0);
136
137 efx_writeo(efx, &reg, address);
138 efx_reado(efx, &buf, address);
139
140 if (efx_masked_compare_oword(&reg, &buf, &mask))
141 goto fail;
142 }
143
144 efx_writeo(efx, &original, address);
145 }
146
147 return 0;
148
149 fail:
150 netif_err(efx, hw, efx->net_dev,
151 "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
152 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
153 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
154 return -EIO;
155 }
156
157 /**************************************************************************
158 *
159 * Special buffer handling
160 * Special buffers are used for event queues and the TX and RX
161 * descriptor rings.
162 *
163 *************************************************************************/
164
165 /*
166 * Initialise a special buffer
167 *
168 * This will define a buffer (previously allocated via
169 * efx_alloc_special_buffer()) in the buffer table, allowing
170 * it to be used for event queues, descriptor rings etc.
171 */
172 static void
173 efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
174 {
175 efx_qword_t buf_desc;
176 unsigned int index;
177 dma_addr_t dma_addr;
178 int i;
179
180 EFX_WARN_ON_PARANOID(!buffer->buf.addr);
181
182 /* Write buffer descriptors to NIC */
183 for (i = 0; i < buffer->entries; i++) {
184 index = buffer->index + i;
185 dma_addr = buffer->buf.dma_addr + (i * EFX_BUF_SIZE);
186 netif_dbg(efx, probe, efx->net_dev,
187 "mapping special buffer %d at %llx\n",
188 index, (unsigned long long)dma_addr);
189 EFX_POPULATE_QWORD_3(buf_desc,
190 FRF_AZ_BUF_ADR_REGION, 0,
191 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
192 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
193 efx_write_buf_tbl(efx, &buf_desc, index);
194 }
195 }
196
197 /* Unmaps a buffer and clears the buffer table entries */
198 static void
199 efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
200 {
201 efx_oword_t buf_tbl_upd;
202 unsigned int start = buffer->index;
203 unsigned int end = (buffer->index + buffer->entries - 1);
204
205 if (!buffer->entries)
206 return;
207
208 netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n",
209 buffer->index, buffer->index + buffer->entries - 1);
210
211 EFX_POPULATE_OWORD_4(buf_tbl_upd,
212 FRF_AZ_BUF_UPD_CMD, 0,
213 FRF_AZ_BUF_CLR_CMD, 1,
214 FRF_AZ_BUF_CLR_END_ID, end,
215 FRF_AZ_BUF_CLR_START_ID, start);
216 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
217 }
218
219 /*
220 * Allocate a new special buffer
221 *
222 * This allocates memory for a new buffer, clears it and allocates a
223 * new buffer ID range. It does not write into the buffer table.
224 *
225 * This call will allocate 4KB buffers, since 8KB buffers can't be
226 * used for event queues and descriptor rings.
227 */
228 static int efx_alloc_special_buffer(struct efx_nic *efx,
229 struct efx_special_buffer *buffer,
230 unsigned int len)
231 {
232 #ifdef CONFIG_SFC_SRIOV
233 struct siena_nic_data *nic_data = efx->nic_data;
234 #endif
235 len = ALIGN(len, EFX_BUF_SIZE);
236
237 if (efx_nic_alloc_buffer(efx, &buffer->buf, len, GFP_KERNEL))
238 return -ENOMEM;
239 buffer->entries = len / EFX_BUF_SIZE;
240 BUG_ON(buffer->buf.dma_addr & (EFX_BUF_SIZE - 1));
241
242 /* Select new buffer ID */
243 buffer->index = efx->next_buffer_table;
244 efx->next_buffer_table += buffer->entries;
245 #ifdef CONFIG_SFC_SRIOV
246 BUG_ON(efx_siena_sriov_enabled(efx) &&
247 nic_data->vf_buftbl_base < efx->next_buffer_table);
248 #endif
249
250 netif_dbg(efx, probe, efx->net_dev,
251 "allocating special buffers %d-%d at %llx+%x "
252 "(virt %p phys %llx)\n", buffer->index,
253 buffer->index + buffer->entries - 1,
254 (u64)buffer->buf.dma_addr, len,
255 buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
256
257 return 0;
258 }
259
260 static void
261 efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
262 {
263 if (!buffer->buf.addr)
264 return;
265
266 netif_dbg(efx, hw, efx->net_dev,
267 "deallocating special buffers %d-%d at %llx+%x "
268 "(virt %p phys %llx)\n", buffer->index,
269 buffer->index + buffer->entries - 1,
270 (u64)buffer->buf.dma_addr, buffer->buf.len,
271 buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
272
273 efx_nic_free_buffer(efx, &buffer->buf);
274 buffer->entries = 0;
275 }
276
277 /**************************************************************************
278 *
279 * TX path
280 *
281 **************************************************************************/
282
283 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
284 static inline void efx_farch_notify_tx_desc(struct efx_tx_queue *tx_queue)
285 {
286 unsigned write_ptr;
287 efx_dword_t reg;
288
289 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
290 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
291 efx_writed_page(tx_queue->efx, &reg,
292 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
293 }
294
295 /* Write pointer and first descriptor for TX descriptor ring */
296 static inline void efx_farch_push_tx_desc(struct efx_tx_queue *tx_queue,
297 const efx_qword_t *txd)
298 {
299 unsigned write_ptr;
300 efx_oword_t reg;
301
302 BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0);
303 BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0);
304
305 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
306 EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true,
307 FRF_AZ_TX_DESC_WPTR, write_ptr);
308 reg.qword[0] = *txd;
309 efx_writeo_page(tx_queue->efx, &reg,
310 FR_BZ_TX_DESC_UPD_P0, tx_queue->queue);
311 }
312
313
314 /* For each entry inserted into the software descriptor ring, create a
315 * descriptor in the hardware TX descriptor ring (in host memory), and
316 * write a doorbell.
317 */
318 void efx_farch_tx_write(struct efx_tx_queue *tx_queue)
319 {
320 struct efx_tx_buffer *buffer;
321 efx_qword_t *txd;
322 unsigned write_ptr;
323 unsigned old_write_count = tx_queue->write_count;
324
325 tx_queue->xmit_more_available = false;
326 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
327 return;
328
329 do {
330 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
331 buffer = &tx_queue->buffer[write_ptr];
332 txd = efx_tx_desc(tx_queue, write_ptr);
333 ++tx_queue->write_count;
334
335 EFX_WARN_ON_ONCE_PARANOID(buffer->flags & EFX_TX_BUF_OPTION);
336
337 /* Create TX descriptor ring entry */
338 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
339 EFX_POPULATE_QWORD_4(*txd,
340 FSF_AZ_TX_KER_CONT,
341 buffer->flags & EFX_TX_BUF_CONT,
342 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
343 FSF_AZ_TX_KER_BUF_REGION, 0,
344 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
345 } while (tx_queue->write_count != tx_queue->insert_count);
346
347 wmb(); /* Ensure descriptors are written before they are fetched */
348
349 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
350 txd = efx_tx_desc(tx_queue,
351 old_write_count & tx_queue->ptr_mask);
352 efx_farch_push_tx_desc(tx_queue, txd);
353 ++tx_queue->pushes;
354 } else {
355 efx_farch_notify_tx_desc(tx_queue);
356 }
357 }
358
359 unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,
360 dma_addr_t dma_addr, unsigned int len)
361 {
362 /* Don't cross 4K boundaries with descriptors. */
363 unsigned int limit = (~dma_addr & (EFX_PAGE_SIZE - 1)) + 1;
364
365 len = min(limit, len);
366
367 return len;
368 }
369
370
371 /* Allocate hardware resources for a TX queue */
372 int efx_farch_tx_probe(struct efx_tx_queue *tx_queue)
373 {
374 struct efx_nic *efx = tx_queue->efx;
375 unsigned entries;
376
377 entries = tx_queue->ptr_mask + 1;
378 return efx_alloc_special_buffer(efx, &tx_queue->txd,
379 entries * sizeof(efx_qword_t));
380 }
381
382 void efx_farch_tx_init(struct efx_tx_queue *tx_queue)
383 {
384 int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
385 struct efx_nic *efx = tx_queue->efx;
386 efx_oword_t reg;
387
388 /* Pin TX descriptor ring */
389 efx_init_special_buffer(efx, &tx_queue->txd);
390
391 /* Push TX descriptor ring to card */
392 EFX_POPULATE_OWORD_10(reg,
393 FRF_AZ_TX_DESCQ_EN, 1,
394 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
395 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
396 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
397 FRF_AZ_TX_DESCQ_EVQ_ID,
398 tx_queue->channel->channel,
399 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
400 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
401 FRF_AZ_TX_DESCQ_SIZE,
402 __ffs(tx_queue->txd.entries),
403 FRF_AZ_TX_DESCQ_TYPE, 0,
404 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
405
406 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
407 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS, !csum);
408
409 efx_writeo_table(efx, &reg, efx->type->txd_ptr_tbl_base,
410 tx_queue->queue);
411
412 EFX_POPULATE_OWORD_1(reg,
413 FRF_BZ_TX_PACE,
414 (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
415 FFE_BZ_TX_PACE_OFF :
416 FFE_BZ_TX_PACE_RESERVED);
417 efx_writeo_table(efx, &reg, FR_BZ_TX_PACE_TBL, tx_queue->queue);
418 }
419
420 static void efx_farch_flush_tx_queue(struct efx_tx_queue *tx_queue)
421 {
422 struct efx_nic *efx = tx_queue->efx;
423 efx_oword_t tx_flush_descq;
424
425 WARN_ON(atomic_read(&tx_queue->flush_outstanding));
426 atomic_set(&tx_queue->flush_outstanding, 1);
427
428 EFX_POPULATE_OWORD_2(tx_flush_descq,
429 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
430 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
431 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
432 }
433
434 void efx_farch_tx_fini(struct efx_tx_queue *tx_queue)
435 {
436 struct efx_nic *efx = tx_queue->efx;
437 efx_oword_t tx_desc_ptr;
438
439 /* Remove TX descriptor ring from card */
440 EFX_ZERO_OWORD(tx_desc_ptr);
441 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
442 tx_queue->queue);
443
444 /* Unpin TX descriptor ring */
445 efx_fini_special_buffer(efx, &tx_queue->txd);
446 }
447
448 /* Free buffers backing TX queue */
449 void efx_farch_tx_remove(struct efx_tx_queue *tx_queue)
450 {
451 efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
452 }
453
454 /**************************************************************************
455 *
456 * RX path
457 *
458 **************************************************************************/
459
460 /* This creates an entry in the RX descriptor queue */
461 static inline void
462 efx_farch_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
463 {
464 struct efx_rx_buffer *rx_buf;
465 efx_qword_t *rxd;
466
467 rxd = efx_rx_desc(rx_queue, index);
468 rx_buf = efx_rx_buffer(rx_queue, index);
469 EFX_POPULATE_QWORD_3(*rxd,
470 FSF_AZ_RX_KER_BUF_SIZE,
471 rx_buf->len -
472 rx_queue->efx->type->rx_buffer_padding,
473 FSF_AZ_RX_KER_BUF_REGION, 0,
474 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
475 }
476
477 /* This writes to the RX_DESC_WPTR register for the specified receive
478 * descriptor ring.
479 */
480 void efx_farch_rx_write(struct efx_rx_queue *rx_queue)
481 {
482 struct efx_nic *efx = rx_queue->efx;
483 efx_dword_t reg;
484 unsigned write_ptr;
485
486 while (rx_queue->notified_count != rx_queue->added_count) {
487 efx_farch_build_rx_desc(
488 rx_queue,
489 rx_queue->notified_count & rx_queue->ptr_mask);
490 ++rx_queue->notified_count;
491 }
492
493 wmb();
494 write_ptr = rx_queue->added_count & rx_queue->ptr_mask;
495 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
496 efx_writed_page(efx, &reg, FR_AZ_RX_DESC_UPD_DWORD_P0,
497 efx_rx_queue_index(rx_queue));
498 }
499
500 int efx_farch_rx_probe(struct efx_rx_queue *rx_queue)
501 {
502 struct efx_nic *efx = rx_queue->efx;
503 unsigned entries;
504
505 entries = rx_queue->ptr_mask + 1;
506 return efx_alloc_special_buffer(efx, &rx_queue->rxd,
507 entries * sizeof(efx_qword_t));
508 }
509
510 void efx_farch_rx_init(struct efx_rx_queue *rx_queue)
511 {
512 efx_oword_t rx_desc_ptr;
513 struct efx_nic *efx = rx_queue->efx;
514 bool jumbo_en;
515
516 /* For kernel-mode queues in Siena, the JUMBO flag enables scatter. */
517 jumbo_en = efx->rx_scatter;
518
519 netif_dbg(efx, hw, efx->net_dev,
520 "RX queue %d ring in special buffers %d-%d\n",
521 efx_rx_queue_index(rx_queue), rx_queue->rxd.index,
522 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
523
524 rx_queue->scatter_n = 0;
525
526 /* Pin RX descriptor ring */
527 efx_init_special_buffer(efx, &rx_queue->rxd);
528
529 /* Push RX descriptor ring to card */
530 EFX_POPULATE_OWORD_10(rx_desc_ptr,
531 FRF_AZ_RX_ISCSI_DDIG_EN, true,
532 FRF_AZ_RX_ISCSI_HDIG_EN, true,
533 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
534 FRF_AZ_RX_DESCQ_EVQ_ID,
535 efx_rx_queue_channel(rx_queue)->channel,
536 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
537 FRF_AZ_RX_DESCQ_LABEL,
538 efx_rx_queue_index(rx_queue),
539 FRF_AZ_RX_DESCQ_SIZE,
540 __ffs(rx_queue->rxd.entries),
541 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
542 FRF_AZ_RX_DESCQ_JUMBO, jumbo_en,
543 FRF_AZ_RX_DESCQ_EN, 1);
544 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
545 efx_rx_queue_index(rx_queue));
546 }
547
548 static void efx_farch_flush_rx_queue(struct efx_rx_queue *rx_queue)
549 {
550 struct efx_nic *efx = rx_queue->efx;
551 efx_oword_t rx_flush_descq;
552
553 EFX_POPULATE_OWORD_2(rx_flush_descq,
554 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
555 FRF_AZ_RX_FLUSH_DESCQ,
556 efx_rx_queue_index(rx_queue));
557 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
558 }
559
560 void efx_farch_rx_fini(struct efx_rx_queue *rx_queue)
561 {
562 efx_oword_t rx_desc_ptr;
563 struct efx_nic *efx = rx_queue->efx;
564
565 /* Remove RX descriptor ring from card */
566 EFX_ZERO_OWORD(rx_desc_ptr);
567 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
568 efx_rx_queue_index(rx_queue));
569
570 /* Unpin RX descriptor ring */
571 efx_fini_special_buffer(efx, &rx_queue->rxd);
572 }
573
574 /* Free buffers backing RX queue */
575 void efx_farch_rx_remove(struct efx_rx_queue *rx_queue)
576 {
577 efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
578 }
579
580 /**************************************************************************
581 *
582 * Flush handling
583 *
584 **************************************************************************/
585
586 /* efx_farch_flush_queues() must be woken up when all flushes are completed,
587 * or more RX flushes can be kicked off.
588 */
589 static bool efx_farch_flush_wake(struct efx_nic *efx)
590 {
591 /* Ensure that all updates are visible to efx_farch_flush_queues() */
592 smp_mb();
593
594 return (atomic_read(&efx->active_queues) == 0 ||
595 (atomic_read(&efx->rxq_flush_outstanding) < EFX_RX_FLUSH_COUNT
596 && atomic_read(&efx->rxq_flush_pending) > 0));
597 }
598
599 static bool efx_check_tx_flush_complete(struct efx_nic *efx)
600 {
601 bool i = true;
602 efx_oword_t txd_ptr_tbl;
603 struct efx_channel *channel;
604 struct efx_tx_queue *tx_queue;
605
606 efx_for_each_channel(channel, efx) {
607 efx_for_each_channel_tx_queue(tx_queue, channel) {
608 efx_reado_table(efx, &txd_ptr_tbl,
609 FR_BZ_TX_DESC_PTR_TBL, tx_queue->queue);
610 if (EFX_OWORD_FIELD(txd_ptr_tbl,
611 FRF_AZ_TX_DESCQ_FLUSH) ||
612 EFX_OWORD_FIELD(txd_ptr_tbl,
613 FRF_AZ_TX_DESCQ_EN)) {
614 netif_dbg(efx, hw, efx->net_dev,
615 "flush did not complete on TXQ %d\n",
616 tx_queue->queue);
617 i = false;
618 } else if (atomic_cmpxchg(&tx_queue->flush_outstanding,
619 1, 0)) {
620 /* The flush is complete, but we didn't
621 * receive a flush completion event
622 */
623 netif_dbg(efx, hw, efx->net_dev,
624 "flush complete on TXQ %d, so drain "
625 "the queue\n", tx_queue->queue);
626 /* Don't need to increment active_queues as it
627 * has already been incremented for the queues
628 * which did not drain
629 */
630 efx_farch_magic_event(channel,
631 EFX_CHANNEL_MAGIC_TX_DRAIN(
632 tx_queue));
633 }
634 }
635 }
636
637 return i;
638 }
639
640 /* Flush all the transmit queues, and continue flushing receive queues until
641 * they're all flushed. Wait for the DRAIN events to be received so that there
642 * are no more RX and TX events left on any channel. */
643 static int efx_farch_do_flush(struct efx_nic *efx)
644 {
645 unsigned timeout = msecs_to_jiffies(5000); /* 5s for all flushes and drains */
646 struct efx_channel *channel;
647 struct efx_rx_queue *rx_queue;
648 struct efx_tx_queue *tx_queue;
649 int rc = 0;
650
651 efx_for_each_channel(channel, efx) {
652 efx_for_each_channel_tx_queue(tx_queue, channel) {
653 efx_farch_flush_tx_queue(tx_queue);
654 }
655 efx_for_each_channel_rx_queue(rx_queue, channel) {
656 rx_queue->flush_pending = true;
657 atomic_inc(&efx->rxq_flush_pending);
658 }
659 }
660
661 while (timeout && atomic_read(&efx->active_queues) > 0) {
662 /* If SRIOV is enabled, then offload receive queue flushing to
663 * the firmware (though we will still have to poll for
664 * completion). If that fails, fall back to the old scheme.
665 */
666 if (efx_siena_sriov_enabled(efx)) {
667 rc = efx_mcdi_flush_rxqs(efx);
668 if (!rc)
669 goto wait;
670 }
671
672 /* The hardware supports four concurrent rx flushes, each of
673 * which may need to be retried if there is an outstanding
674 * descriptor fetch
675 */
676 efx_for_each_channel(channel, efx) {
677 efx_for_each_channel_rx_queue(rx_queue, channel) {
678 if (atomic_read(&efx->rxq_flush_outstanding) >=
679 EFX_RX_FLUSH_COUNT)
680 break;
681
682 if (rx_queue->flush_pending) {
683 rx_queue->flush_pending = false;
684 atomic_dec(&efx->rxq_flush_pending);
685 atomic_inc(&efx->rxq_flush_outstanding);
686 efx_farch_flush_rx_queue(rx_queue);
687 }
688 }
689 }
690
691 wait:
692 timeout = wait_event_timeout(efx->flush_wq,
693 efx_farch_flush_wake(efx),
694 timeout);
695 }
696
697 if (atomic_read(&efx->active_queues) &&
698 !efx_check_tx_flush_complete(efx)) {
699 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues "
700 "(rx %d+%d)\n", atomic_read(&efx->active_queues),
701 atomic_read(&efx->rxq_flush_outstanding),
702 atomic_read(&efx->rxq_flush_pending));
703 rc = -ETIMEDOUT;
704
705 atomic_set(&efx->active_queues, 0);
706 atomic_set(&efx->rxq_flush_pending, 0);
707 atomic_set(&efx->rxq_flush_outstanding, 0);
708 }
709
710 return rc;
711 }
712
713 int efx_farch_fini_dmaq(struct efx_nic *efx)
714 {
715 struct efx_channel *channel;
716 struct efx_tx_queue *tx_queue;
717 struct efx_rx_queue *rx_queue;
718 int rc = 0;
719
720 /* Do not attempt to write to the NIC during EEH recovery */
721 if (efx->state != STATE_RECOVERY) {
722 /* Only perform flush if DMA is enabled */
723 if (efx->pci_dev->is_busmaster) {
724 efx->type->prepare_flush(efx);
725 rc = efx_farch_do_flush(efx);
726 efx->type->finish_flush(efx);
727 }
728
729 efx_for_each_channel(channel, efx) {
730 efx_for_each_channel_rx_queue(rx_queue, channel)
731 efx_farch_rx_fini(rx_queue);
732 efx_for_each_channel_tx_queue(tx_queue, channel)
733 efx_farch_tx_fini(tx_queue);
734 }
735 }
736
737 return rc;
738 }
739
740 /* Reset queue and flush accounting after FLR
741 *
742 * One possible cause of FLR recovery is that DMA may be failing (eg. if bus
743 * mastering was disabled), in which case we don't receive (RXQ) flush
744 * completion events. This means that efx->rxq_flush_outstanding remained at 4
745 * after the FLR; also, efx->active_queues was non-zero (as no flush completion
746 * events were received, and we didn't go through efx_check_tx_flush_complete())
747 * If we don't fix this up, on the next call to efx_realloc_channels() we won't
748 * flush any RX queues because efx->rxq_flush_outstanding is at the limit of 4
749 * for batched flush requests; and the efx->active_queues gets messed up because
750 * we keep incrementing for the newly initialised queues, but it never went to
751 * zero previously. Then we get a timeout every time we try to restart the
752 * queues, as it doesn't go back to zero when we should be flushing the queues.
753 */
754 void efx_farch_finish_flr(struct efx_nic *efx)
755 {
756 atomic_set(&efx->rxq_flush_pending, 0);
757 atomic_set(&efx->rxq_flush_outstanding, 0);
758 atomic_set(&efx->active_queues, 0);
759 }
760
761
762 /**************************************************************************
763 *
764 * Event queue processing
765 * Event queues are processed by per-channel tasklets.
766 *
767 **************************************************************************/
768
769 /* Update a channel's event queue's read pointer (RPTR) register
770 *
771 * This writes the EVQ_RPTR_REG register for the specified channel's
772 * event queue.
773 */
774 void efx_farch_ev_read_ack(struct efx_channel *channel)
775 {
776 efx_dword_t reg;
777 struct efx_nic *efx = channel->efx;
778
779 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR,
780 channel->eventq_read_ptr & channel->eventq_mask);
781
782 /* For Falcon A1, EVQ_RPTR_KER is documented as having a step size
783 * of 4 bytes, but it is really 16 bytes just like later revisions.
784 */
785 efx_writed(efx, &reg,
786 efx->type->evq_rptr_tbl_base +
787 FR_BZ_EVQ_RPTR_STEP * channel->channel);
788 }
789
790 /* Use HW to insert a SW defined event */
791 void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
792 efx_qword_t *event)
793 {
794 efx_oword_t drv_ev_reg;
795
796 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
797 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
798 drv_ev_reg.u32[0] = event->u32[0];
799 drv_ev_reg.u32[1] = event->u32[1];
800 drv_ev_reg.u32[2] = 0;
801 drv_ev_reg.u32[3] = 0;
802 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, evq);
803 efx_writeo(efx, &drv_ev_reg, FR_AZ_DRV_EV);
804 }
805
806 static void efx_farch_magic_event(struct efx_channel *channel, u32 magic)
807 {
808 efx_qword_t event;
809
810 EFX_POPULATE_QWORD_2(event, FSF_AZ_EV_CODE,
811 FSE_AZ_EV_CODE_DRV_GEN_EV,
812 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
813 efx_farch_generate_event(channel->efx, channel->channel, &event);
814 }
815
816 /* Handle a transmit completion event
817 *
818 * The NIC batches TX completion events; the message we receive is of
819 * the form "complete all TX events up to this index".
820 */
821 static void
822 efx_farch_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
823 {
824 unsigned int tx_ev_desc_ptr;
825 unsigned int tx_ev_q_label;
826 struct efx_tx_queue *tx_queue;
827 struct efx_nic *efx = channel->efx;
828
829 if (unlikely(READ_ONCE(efx->reset_pending)))
830 return;
831
832 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
833 /* Transmit completion */
834 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
835 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
836 tx_queue = efx_channel_get_tx_queue(
837 channel, tx_ev_q_label % EFX_TXQ_TYPES);
838 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
839 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
840 /* Rewrite the FIFO write pointer */
841 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
842 tx_queue = efx_channel_get_tx_queue(
843 channel, tx_ev_q_label % EFX_TXQ_TYPES);
844
845 netif_tx_lock(efx->net_dev);
846 efx_farch_notify_tx_desc(tx_queue);
847 netif_tx_unlock(efx->net_dev);
848 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR)) {
849 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
850 } else {
851 netif_err(efx, tx_err, efx->net_dev,
852 "channel %d unexpected TX event "
853 EFX_QWORD_FMT"\n", channel->channel,
854 EFX_QWORD_VAL(*event));
855 }
856 }
857
858 /* Detect errors included in the rx_evt_pkt_ok bit. */
859 static u16 efx_farch_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
860 const efx_qword_t *event)
861 {
862 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
863 struct efx_nic *efx = rx_queue->efx;
864 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
865 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
866 bool rx_ev_frm_trunc, rx_ev_tobe_disc;
867 bool rx_ev_other_err, rx_ev_pause_frm;
868 bool rx_ev_hdr_type, rx_ev_mcast_pkt;
869 unsigned rx_ev_pkt_type;
870
871 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
872 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
873 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
874 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
875 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
876 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
877 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
878 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
879 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
880 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
881 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
882 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
883 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
884
885 /* Every error apart from tobe_disc and pause_frm */
886 rx_ev_other_err = (rx_ev_tcp_udp_chksum_err |
887 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
888 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
889
890 /* Count errors that are not in MAC stats. Ignore expected
891 * checksum errors during self-test. */
892 if (rx_ev_frm_trunc)
893 ++channel->n_rx_frm_trunc;
894 else if (rx_ev_tobe_disc)
895 ++channel->n_rx_tobe_disc;
896 else if (!efx->loopback_selftest) {
897 if (rx_ev_ip_hdr_chksum_err)
898 ++channel->n_rx_ip_hdr_chksum_err;
899 else if (rx_ev_tcp_udp_chksum_err)
900 ++channel->n_rx_tcp_udp_chksum_err;
901 }
902
903 /* TOBE_DISC is expected on unicast mismatches; don't print out an
904 * error message. FRM_TRUNC indicates RXDP dropped the packet due
905 * to a FIFO overflow.
906 */
907 #ifdef DEBUG
908 if (rx_ev_other_err && net_ratelimit()) {
909 netif_dbg(efx, rx_err, efx->net_dev,
910 " RX queue %d unexpected RX event "
911 EFX_QWORD_FMT "%s%s%s%s%s%s%s\n",
912 efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event),
913 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
914 rx_ev_ip_hdr_chksum_err ?
915 " [IP_HDR_CHKSUM_ERR]" : "",
916 rx_ev_tcp_udp_chksum_err ?
917 " [TCP_UDP_CHKSUM_ERR]" : "",
918 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
919 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
920 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
921 rx_ev_pause_frm ? " [PAUSE]" : "");
922 }
923 #endif
924
925 if (efx->net_dev->features & NETIF_F_RXALL)
926 /* don't discard frame for CRC error */
927 rx_ev_eth_crc_err = false;
928
929 /* The frame must be discarded if any of these are true. */
930 return (rx_ev_eth_crc_err | rx_ev_frm_trunc |
931 rx_ev_tobe_disc | rx_ev_pause_frm) ?
932 EFX_RX_PKT_DISCARD : 0;
933 }
934
935 /* Handle receive events that are not in-order. Return true if this
936 * can be handled as a partial packet discard, false if it's more
937 * serious.
938 */
939 static bool
940 efx_farch_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
941 {
942 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
943 struct efx_nic *efx = rx_queue->efx;
944 unsigned expected, dropped;
945
946 if (rx_queue->scatter_n &&
947 index == ((rx_queue->removed_count + rx_queue->scatter_n - 1) &
948 rx_queue->ptr_mask)) {
949 ++channel->n_rx_nodesc_trunc;
950 return true;
951 }
952
953 expected = rx_queue->removed_count & rx_queue->ptr_mask;
954 dropped = (index - expected) & rx_queue->ptr_mask;
955 netif_info(efx, rx_err, efx->net_dev,
956 "dropped %d events (index=%d expected=%d)\n",
957 dropped, index, expected);
958
959 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
960 return false;
961 }
962
963 /* Handle a packet received event
964 *
965 * The NIC gives a "discard" flag if it's a unicast packet with the
966 * wrong destination address
967 * Also "is multicast" and "matches multicast filter" flags can be used to
968 * discard non-matching multicast packets.
969 */
970 static void
971 efx_farch_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
972 {
973 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
974 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
975 unsigned expected_ptr;
976 bool rx_ev_pkt_ok, rx_ev_sop, rx_ev_cont;
977 u16 flags;
978 struct efx_rx_queue *rx_queue;
979 struct efx_nic *efx = channel->efx;
980
981 if (unlikely(READ_ONCE(efx->reset_pending)))
982 return;
983
984 rx_ev_cont = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT);
985 rx_ev_sop = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP);
986 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
987 channel->channel);
988
989 rx_queue = efx_channel_get_rx_queue(channel);
990
991 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
992 expected_ptr = ((rx_queue->removed_count + rx_queue->scatter_n) &
993 rx_queue->ptr_mask);
994
995 /* Check for partial drops and other errors */
996 if (unlikely(rx_ev_desc_ptr != expected_ptr) ||
997 unlikely(rx_ev_sop != (rx_queue->scatter_n == 0))) {
998 if (rx_ev_desc_ptr != expected_ptr &&
999 !efx_farch_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr))
1000 return;
1001
1002 /* Discard all pending fragments */
1003 if (rx_queue->scatter_n) {
1004 efx_rx_packet(
1005 rx_queue,
1006 rx_queue->removed_count & rx_queue->ptr_mask,
1007 rx_queue->scatter_n, 0, EFX_RX_PKT_DISCARD);
1008 rx_queue->removed_count += rx_queue->scatter_n;
1009 rx_queue->scatter_n = 0;
1010 }
1011
1012 /* Return if there is no new fragment */
1013 if (rx_ev_desc_ptr != expected_ptr)
1014 return;
1015
1016 /* Discard new fragment if not SOP */
1017 if (!rx_ev_sop) {
1018 efx_rx_packet(
1019 rx_queue,
1020 rx_queue->removed_count & rx_queue->ptr_mask,
1021 1, 0, EFX_RX_PKT_DISCARD);
1022 ++rx_queue->removed_count;
1023 return;
1024 }
1025 }
1026
1027 ++rx_queue->scatter_n;
1028 if (rx_ev_cont)
1029 return;
1030
1031 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
1032 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
1033 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
1034
1035 if (likely(rx_ev_pkt_ok)) {
1036 /* If packet is marked as OK then we can rely on the
1037 * hardware checksum and classification.
1038 */
1039 flags = 0;
1040 switch (rx_ev_hdr_type) {
1041 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
1042 flags |= EFX_RX_PKT_TCP;
1043 /* fall through */
1044 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
1045 flags |= EFX_RX_PKT_CSUMMED;
1046 /* fall through */
1047 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
1048 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
1049 break;
1050 }
1051 } else {
1052 flags = efx_farch_handle_rx_not_ok(rx_queue, event);
1053 }
1054
1055 /* Detect multicast packets that didn't match the filter */
1056 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
1057 if (rx_ev_mcast_pkt) {
1058 unsigned int rx_ev_mcast_hash_match =
1059 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
1060
1061 if (unlikely(!rx_ev_mcast_hash_match)) {
1062 ++channel->n_rx_mcast_mismatch;
1063 flags |= EFX_RX_PKT_DISCARD;
1064 }
1065 }
1066
1067 channel->irq_mod_score += 2;
1068
1069 /* Handle received packet */
1070 efx_rx_packet(rx_queue,
1071 rx_queue->removed_count & rx_queue->ptr_mask,
1072 rx_queue->scatter_n, rx_ev_byte_cnt, flags);
1073 rx_queue->removed_count += rx_queue->scatter_n;
1074 rx_queue->scatter_n = 0;
1075 }
1076
1077 /* If this flush done event corresponds to a &struct efx_tx_queue, then
1078 * send an %EFX_CHANNEL_MAGIC_TX_DRAIN event to drain the event queue
1079 * of all transmit completions.
1080 */
1081 static void
1082 efx_farch_handle_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1083 {
1084 struct efx_tx_queue *tx_queue;
1085 int qid;
1086
1087 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1088 if (qid < EFX_TXQ_TYPES * (efx->n_tx_channels + efx->n_extra_tx_channels)) {
1089 tx_queue = efx_get_tx_queue(efx, qid / EFX_TXQ_TYPES,
1090 qid % EFX_TXQ_TYPES);
1091 if (atomic_cmpxchg(&tx_queue->flush_outstanding, 1, 0)) {
1092 efx_farch_magic_event(tx_queue->channel,
1093 EFX_CHANNEL_MAGIC_TX_DRAIN(tx_queue));
1094 }
1095 }
1096 }
1097
1098 /* If this flush done event corresponds to a &struct efx_rx_queue: If the flush
1099 * was successful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add
1100 * the RX queue back to the mask of RX queues in need of flushing.
1101 */
1102 static void
1103 efx_farch_handle_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1104 {
1105 struct efx_channel *channel;
1106 struct efx_rx_queue *rx_queue;
1107 int qid;
1108 bool failed;
1109
1110 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1111 failed = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1112 if (qid >= efx->n_channels)
1113 return;
1114 channel = efx_get_channel(efx, qid);
1115 if (!efx_channel_has_rx_queue(channel))
1116 return;
1117 rx_queue = efx_channel_get_rx_queue(channel);
1118
1119 if (failed) {
1120 netif_info(efx, hw, efx->net_dev,
1121 "RXQ %d flush retry\n", qid);
1122 rx_queue->flush_pending = true;
1123 atomic_inc(&efx->rxq_flush_pending);
1124 } else {
1125 efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1126 EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue));
1127 }
1128 atomic_dec(&efx->rxq_flush_outstanding);
1129 if (efx_farch_flush_wake(efx))
1130 wake_up(&efx->flush_wq);
1131 }
1132
1133 static void
1134 efx_farch_handle_drain_event(struct efx_channel *channel)
1135 {
1136 struct efx_nic *efx = channel->efx;
1137
1138 WARN_ON(atomic_read(&efx->active_queues) == 0);
1139 atomic_dec(&efx->active_queues);
1140 if (efx_farch_flush_wake(efx))
1141 wake_up(&efx->flush_wq);
1142 }
1143
1144 static void efx_farch_handle_generated_event(struct efx_channel *channel,
1145 efx_qword_t *event)
1146 {
1147 struct efx_nic *efx = channel->efx;
1148 struct efx_rx_queue *rx_queue =
1149 efx_channel_has_rx_queue(channel) ?
1150 efx_channel_get_rx_queue(channel) : NULL;
1151 unsigned magic, code;
1152
1153 magic = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC);
1154 code = _EFX_CHANNEL_MAGIC_CODE(magic);
1155
1156 if (magic == EFX_CHANNEL_MAGIC_TEST(channel)) {
1157 channel->event_test_cpu = raw_smp_processor_id();
1158 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_FILL(rx_queue)) {
1159 /* The queue must be empty, so we won't receive any rx
1160 * events, so efx_process_channel() won't refill the
1161 * queue. Refill it here */
1162 efx_fast_push_rx_descriptors(rx_queue, true);
1163 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)) {
1164 efx_farch_handle_drain_event(channel);
1165 } else if (code == _EFX_CHANNEL_MAGIC_TX_DRAIN) {
1166 efx_farch_handle_drain_event(channel);
1167 } else {
1168 netif_dbg(efx, hw, efx->net_dev, "channel %d received "
1169 "generated event "EFX_QWORD_FMT"\n",
1170 channel->channel, EFX_QWORD_VAL(*event));
1171 }
1172 }
1173
1174 static void
1175 efx_farch_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1176 {
1177 struct efx_nic *efx = channel->efx;
1178 unsigned int ev_sub_code;
1179 unsigned int ev_sub_data;
1180
1181 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
1182 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1183
1184 switch (ev_sub_code) {
1185 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
1186 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n",
1187 channel->channel, ev_sub_data);
1188 efx_farch_handle_tx_flush_done(efx, event);
1189 #ifdef CONFIG_SFC_SRIOV
1190 efx_siena_sriov_tx_flush_done(efx, event);
1191 #endif
1192 break;
1193 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
1194 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n",
1195 channel->channel, ev_sub_data);
1196 efx_farch_handle_rx_flush_done(efx, event);
1197 #ifdef CONFIG_SFC_SRIOV
1198 efx_siena_sriov_rx_flush_done(efx, event);
1199 #endif
1200 break;
1201 case FSE_AZ_EVQ_INIT_DONE_EV:
1202 netif_dbg(efx, hw, efx->net_dev,
1203 "channel %d EVQ %d initialised\n",
1204 channel->channel, ev_sub_data);
1205 break;
1206 case FSE_AZ_SRM_UPD_DONE_EV:
1207 netif_vdbg(efx, hw, efx->net_dev,
1208 "channel %d SRAM update done\n", channel->channel);
1209 break;
1210 case FSE_AZ_WAKE_UP_EV:
1211 netif_vdbg(efx, hw, efx->net_dev,
1212 "channel %d RXQ %d wakeup event\n",
1213 channel->channel, ev_sub_data);
1214 break;
1215 case FSE_AZ_TIMER_EV:
1216 netif_vdbg(efx, hw, efx->net_dev,
1217 "channel %d RX queue %d timer expired\n",
1218 channel->channel, ev_sub_data);
1219 break;
1220 case FSE_AA_RX_RECOVER_EV:
1221 netif_err(efx, rx_err, efx->net_dev,
1222 "channel %d seen DRIVER RX_RESET event. "
1223 "Resetting.\n", channel->channel);
1224 atomic_inc(&efx->rx_reset);
1225 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1226 break;
1227 case FSE_BZ_RX_DSC_ERROR_EV:
1228 if (ev_sub_data < EFX_VI_BASE) {
1229 netif_err(efx, rx_err, efx->net_dev,
1230 "RX DMA Q %d reports descriptor fetch error."
1231 " RX Q %d is disabled.\n", ev_sub_data,
1232 ev_sub_data);
1233 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
1234 }
1235 #ifdef CONFIG_SFC_SRIOV
1236 else
1237 efx_siena_sriov_desc_fetch_err(efx, ev_sub_data);
1238 #endif
1239 break;
1240 case FSE_BZ_TX_DSC_ERROR_EV:
1241 if (ev_sub_data < EFX_VI_BASE) {
1242 netif_err(efx, tx_err, efx->net_dev,
1243 "TX DMA Q %d reports descriptor fetch error."
1244 " TX Q %d is disabled.\n", ev_sub_data,
1245 ev_sub_data);
1246 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
1247 }
1248 #ifdef CONFIG_SFC_SRIOV
1249 else
1250 efx_siena_sriov_desc_fetch_err(efx, ev_sub_data);
1251 #endif
1252 break;
1253 default:
1254 netif_vdbg(efx, hw, efx->net_dev,
1255 "channel %d unknown driver event code %d "
1256 "data %04x\n", channel->channel, ev_sub_code,
1257 ev_sub_data);
1258 break;
1259 }
1260 }
1261
1262 int efx_farch_ev_process(struct efx_channel *channel, int budget)
1263 {
1264 struct efx_nic *efx = channel->efx;
1265 unsigned int read_ptr;
1266 efx_qword_t event, *p_event;
1267 int ev_code;
1268 int spent = 0;
1269
1270 if (budget <= 0)
1271 return spent;
1272
1273 read_ptr = channel->eventq_read_ptr;
1274
1275 for (;;) {
1276 p_event = efx_event(channel, read_ptr);
1277 event = *p_event;
1278
1279 if (!efx_event_present(&event))
1280 /* End of events */
1281 break;
1282
1283 netif_vdbg(channel->efx, intr, channel->efx->net_dev,
1284 "channel %d event is "EFX_QWORD_FMT"\n",
1285 channel->channel, EFX_QWORD_VAL(event));
1286
1287 /* Clear this event by marking it all ones */
1288 EFX_SET_QWORD(*p_event);
1289
1290 ++read_ptr;
1291
1292 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1293
1294 switch (ev_code) {
1295 case FSE_AZ_EV_CODE_RX_EV:
1296 efx_farch_handle_rx_event(channel, &event);
1297 if (++spent == budget)
1298 goto out;
1299 break;
1300 case FSE_AZ_EV_CODE_TX_EV:
1301 efx_farch_handle_tx_event(channel, &event);
1302 break;
1303 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1304 efx_farch_handle_generated_event(channel, &event);
1305 break;
1306 case FSE_AZ_EV_CODE_DRIVER_EV:
1307 efx_farch_handle_driver_event(channel, &event);
1308 break;
1309 #ifdef CONFIG_SFC_SRIOV
1310 case FSE_CZ_EV_CODE_USER_EV:
1311 efx_siena_sriov_event(channel, &event);
1312 break;
1313 #endif
1314 case FSE_CZ_EV_CODE_MCDI_EV:
1315 efx_mcdi_process_event(channel, &event);
1316 break;
1317 case FSE_AZ_EV_CODE_GLOBAL_EV:
1318 if (efx->type->handle_global_event &&
1319 efx->type->handle_global_event(channel, &event))
1320 break;
1321 /* else fall through */
1322 default:
1323 netif_err(channel->efx, hw, channel->efx->net_dev,
1324 "channel %d unknown event type %d (data "
1325 EFX_QWORD_FMT ")\n", channel->channel,
1326 ev_code, EFX_QWORD_VAL(event));
1327 }
1328 }
1329
1330 out:
1331 channel->eventq_read_ptr = read_ptr;
1332 return spent;
1333 }
1334
1335 /* Allocate buffer table entries for event queue */
1336 int efx_farch_ev_probe(struct efx_channel *channel)
1337 {
1338 struct efx_nic *efx = channel->efx;
1339 unsigned entries;
1340
1341 entries = channel->eventq_mask + 1;
1342 return efx_alloc_special_buffer(efx, &channel->eventq,
1343 entries * sizeof(efx_qword_t));
1344 }
1345
1346 int efx_farch_ev_init(struct efx_channel *channel)
1347 {
1348 efx_oword_t reg;
1349 struct efx_nic *efx = channel->efx;
1350
1351 netif_dbg(efx, hw, efx->net_dev,
1352 "channel %d event queue in special buffers %d-%d\n",
1353 channel->channel, channel->eventq.index,
1354 channel->eventq.index + channel->eventq.entries - 1);
1355
1356 EFX_POPULATE_OWORD_3(reg,
1357 FRF_CZ_TIMER_Q_EN, 1,
1358 FRF_CZ_HOST_NOTIFY_MODE, 0,
1359 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1360 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1361
1362 /* Pin event queue buffer */
1363 efx_init_special_buffer(efx, &channel->eventq);
1364
1365 /* Fill event queue with all ones (i.e. empty events) */
1366 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1367
1368 /* Push event queue to card */
1369 EFX_POPULATE_OWORD_3(reg,
1370 FRF_AZ_EVQ_EN, 1,
1371 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1372 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1373 efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1374 channel->channel);
1375
1376 return 0;
1377 }
1378
1379 void efx_farch_ev_fini(struct efx_channel *channel)
1380 {
1381 efx_oword_t reg;
1382 struct efx_nic *efx = channel->efx;
1383
1384 /* Remove event queue from card */
1385 EFX_ZERO_OWORD(reg);
1386 efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1387 channel->channel);
1388 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1389
1390 /* Unpin event queue */
1391 efx_fini_special_buffer(efx, &channel->eventq);
1392 }
1393
1394 /* Free buffers backing event queue */
1395 void efx_farch_ev_remove(struct efx_channel *channel)
1396 {
1397 efx_free_special_buffer(channel->efx, &channel->eventq);
1398 }
1399
1400
1401 void efx_farch_ev_test_generate(struct efx_channel *channel)
1402 {
1403 efx_farch_magic_event(channel, EFX_CHANNEL_MAGIC_TEST(channel));
1404 }
1405
1406 void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue)
1407 {
1408 efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1409 EFX_CHANNEL_MAGIC_FILL(rx_queue));
1410 }
1411
1412 /**************************************************************************
1413 *
1414 * Hardware interrupts
1415 * The hardware interrupt handler does very little work; all the event
1416 * queue processing is carried out by per-channel tasklets.
1417 *
1418 **************************************************************************/
1419
1420 /* Enable/disable/generate interrupts */
1421 static inline void efx_farch_interrupts(struct efx_nic *efx,
1422 bool enabled, bool force)
1423 {
1424 efx_oword_t int_en_reg_ker;
1425
1426 EFX_POPULATE_OWORD_3(int_en_reg_ker,
1427 FRF_AZ_KER_INT_LEVE_SEL, efx->irq_level,
1428 FRF_AZ_KER_INT_KER, force,
1429 FRF_AZ_DRV_INT_EN_KER, enabled);
1430 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1431 }
1432
1433 void efx_farch_irq_enable_master(struct efx_nic *efx)
1434 {
1435 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1436 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1437
1438 efx_farch_interrupts(efx, true, false);
1439 }
1440
1441 void efx_farch_irq_disable_master(struct efx_nic *efx)
1442 {
1443 /* Disable interrupts */
1444 efx_farch_interrupts(efx, false, false);
1445 }
1446
1447 /* Generate a test interrupt
1448 * Interrupt must already have been enabled, otherwise nasty things
1449 * may happen.
1450 */
1451 int efx_farch_irq_test_generate(struct efx_nic *efx)
1452 {
1453 efx_farch_interrupts(efx, true, true);
1454 return 0;
1455 }
1456
1457 /* Process a fatal interrupt
1458 * Disable bus mastering ASAP and schedule a reset
1459 */
1460 irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx)
1461 {
1462 efx_oword_t *int_ker = efx->irq_status.addr;
1463 efx_oword_t fatal_intr;
1464 int error, mem_perr;
1465
1466 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1467 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1468
1469 netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status "
1470 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1471 EFX_OWORD_VAL(fatal_intr),
1472 error ? "disabling bus mastering" : "no recognised error");
1473
1474 /* If this is a memory parity error dump which blocks are offending */
1475 mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) ||
1476 EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER));
1477 if (mem_perr) {
1478 efx_oword_t reg;
1479 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1480 netif_err(efx, hw, efx->net_dev,
1481 "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n",
1482 EFX_OWORD_VAL(reg));
1483 }
1484
1485 /* Disable both devices */
1486 pci_clear_master(efx->pci_dev);
1487 efx_farch_irq_disable_master(efx);
1488
1489 /* Count errors and reset or disable the NIC accordingly */
1490 if (efx->int_error_count == 0 ||
1491 time_after(jiffies, efx->int_error_expire)) {
1492 efx->int_error_count = 0;
1493 efx->int_error_expire =
1494 jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1495 }
1496 if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1497 netif_err(efx, hw, efx->net_dev,
1498 "SYSTEM ERROR - reset scheduled\n");
1499 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1500 } else {
1501 netif_err(efx, hw, efx->net_dev,
1502 "SYSTEM ERROR - max number of errors seen."
1503 "NIC will be disabled\n");
1504 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1505 }
1506
1507 return IRQ_HANDLED;
1508 }
1509
1510 /* Handle a legacy interrupt
1511 * Acknowledges the interrupt and schedule event queue processing.
1512 */
1513 irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id)
1514 {
1515 struct efx_nic *efx = dev_id;
1516 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
1517 efx_oword_t *int_ker = efx->irq_status.addr;
1518 irqreturn_t result = IRQ_NONE;
1519 struct efx_channel *channel;
1520 efx_dword_t reg;
1521 u32 queues;
1522 int syserr;
1523
1524 /* Read the ISR which also ACKs the interrupts */
1525 efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1526 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1527
1528 /* Legacy interrupts are disabled too late by the EEH kernel
1529 * code. Disable them earlier.
1530 * If an EEH error occurred, the read will have returned all ones.
1531 */
1532 if (EFX_DWORD_IS_ALL_ONES(reg) && efx_try_recovery(efx) &&
1533 !efx->eeh_disabled_legacy_irq) {
1534 disable_irq_nosync(efx->legacy_irq);
1535 efx->eeh_disabled_legacy_irq = true;
1536 }
1537
1538 /* Handle non-event-queue sources */
1539 if (queues & (1U << efx->irq_level) && soft_enabled) {
1540 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1541 if (unlikely(syserr))
1542 return efx_farch_fatal_interrupt(efx);
1543 efx->last_irq_cpu = raw_smp_processor_id();
1544 }
1545
1546 if (queues != 0) {
1547 efx->irq_zero_count = 0;
1548
1549 /* Schedule processing of any interrupting queues */
1550 if (likely(soft_enabled)) {
1551 efx_for_each_channel(channel, efx) {
1552 if (queues & 1)
1553 efx_schedule_channel_irq(channel);
1554 queues >>= 1;
1555 }
1556 }
1557 result = IRQ_HANDLED;
1558
1559 } else {
1560 efx_qword_t *event;
1561
1562 /* Legacy ISR read can return zero once (SF bug 15783) */
1563
1564 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1565 * because this might be a shared interrupt. */
1566 if (efx->irq_zero_count++ == 0)
1567 result = IRQ_HANDLED;
1568
1569 /* Ensure we schedule or rearm all event queues */
1570 if (likely(soft_enabled)) {
1571 efx_for_each_channel(channel, efx) {
1572 event = efx_event(channel,
1573 channel->eventq_read_ptr);
1574 if (efx_event_present(event))
1575 efx_schedule_channel_irq(channel);
1576 else
1577 efx_farch_ev_read_ack(channel);
1578 }
1579 }
1580 }
1581
1582 if (result == IRQ_HANDLED)
1583 netif_vdbg(efx, intr, efx->net_dev,
1584 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1585 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1586
1587 return result;
1588 }
1589
1590 /* Handle an MSI interrupt
1591 *
1592 * Handle an MSI hardware interrupt. This routine schedules event
1593 * queue processing. No interrupt acknowledgement cycle is necessary.
1594 * Also, we never need to check that the interrupt is for us, since
1595 * MSI interrupts cannot be shared.
1596 */
1597 irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id)
1598 {
1599 struct efx_msi_context *context = dev_id;
1600 struct efx_nic *efx = context->efx;
1601 efx_oword_t *int_ker = efx->irq_status.addr;
1602 int syserr;
1603
1604 netif_vdbg(efx, intr, efx->net_dev,
1605 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1606 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1607
1608 if (!likely(READ_ONCE(efx->irq_soft_enabled)))
1609 return IRQ_HANDLED;
1610
1611 /* Handle non-event-queue sources */
1612 if (context->index == efx->irq_level) {
1613 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1614 if (unlikely(syserr))
1615 return efx_farch_fatal_interrupt(efx);
1616 efx->last_irq_cpu = raw_smp_processor_id();
1617 }
1618
1619 /* Schedule processing of the channel */
1620 efx_schedule_channel_irq(efx->channel[context->index]);
1621
1622 return IRQ_HANDLED;
1623 }
1624
1625 /* Setup RSS indirection table.
1626 * This maps from the hash value of the packet to RXQ
1627 */
1628 void efx_farch_rx_push_indir_table(struct efx_nic *efx)
1629 {
1630 size_t i = 0;
1631 efx_dword_t dword;
1632
1633 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1634 FR_BZ_RX_INDIRECTION_TBL_ROWS);
1635
1636 for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1637 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1638 efx->rx_indir_table[i]);
1639 efx_writed(efx, &dword,
1640 FR_BZ_RX_INDIRECTION_TBL +
1641 FR_BZ_RX_INDIRECTION_TBL_STEP * i);
1642 }
1643 }
1644
1645 void efx_farch_rx_pull_indir_table(struct efx_nic *efx)
1646 {
1647 size_t i = 0;
1648 efx_dword_t dword;
1649
1650 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1651 FR_BZ_RX_INDIRECTION_TBL_ROWS);
1652
1653 for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1654 efx_readd(efx, &dword,
1655 FR_BZ_RX_INDIRECTION_TBL +
1656 FR_BZ_RX_INDIRECTION_TBL_STEP * i);
1657 efx->rx_indir_table[i] = EFX_DWORD_FIELD(dword, FRF_BZ_IT_QUEUE);
1658 }
1659 }
1660
1661 /* Looks at available SRAM resources and works out how many queues we
1662 * can support, and where things like descriptor caches should live.
1663 *
1664 * SRAM is split up as follows:
1665 * 0 buftbl entries for channels
1666 * efx->vf_buftbl_base buftbl entries for SR-IOV
1667 * efx->rx_dc_base RX descriptor caches
1668 * efx->tx_dc_base TX descriptor caches
1669 */
1670 void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw)
1671 {
1672 unsigned vi_count, buftbl_min, total_tx_channels;
1673
1674 #ifdef CONFIG_SFC_SRIOV
1675 struct siena_nic_data *nic_data = efx->nic_data;
1676 #endif
1677
1678 total_tx_channels = efx->n_tx_channels + efx->n_extra_tx_channels;
1679 /* Account for the buffer table entries backing the datapath channels
1680 * and the descriptor caches for those channels.
1681 */
1682 buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE +
1683 total_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE +
1684 efx->n_channels * EFX_MAX_EVQ_SIZE)
1685 * sizeof(efx_qword_t) / EFX_BUF_SIZE);
1686 vi_count = max(efx->n_channels, total_tx_channels * EFX_TXQ_TYPES);
1687
1688 #ifdef CONFIG_SFC_SRIOV
1689 if (efx->type->sriov_wanted) {
1690 if (efx->type->sriov_wanted(efx)) {
1691 unsigned vi_dc_entries, buftbl_free;
1692 unsigned entries_per_vf, vf_limit;
1693
1694 nic_data->vf_buftbl_base = buftbl_min;
1695
1696 vi_dc_entries = RX_DC_ENTRIES + TX_DC_ENTRIES;
1697 vi_count = max(vi_count, EFX_VI_BASE);
1698 buftbl_free = (sram_lim_qw - buftbl_min -
1699 vi_count * vi_dc_entries);
1700
1701 entries_per_vf = ((vi_dc_entries +
1702 EFX_VF_BUFTBL_PER_VI) *
1703 efx_vf_size(efx));
1704 vf_limit = min(buftbl_free / entries_per_vf,
1705 (1024U - EFX_VI_BASE) >> efx->vi_scale);
1706
1707 if (efx->vf_count > vf_limit) {
1708 netif_err(efx, probe, efx->net_dev,
1709 "Reducing VF count from from %d to %d\n",
1710 efx->vf_count, vf_limit);
1711 efx->vf_count = vf_limit;
1712 }
1713 vi_count += efx->vf_count * efx_vf_size(efx);
1714 }
1715 }
1716 #endif
1717
1718 efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES;
1719 efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES;
1720 }
1721
1722 u32 efx_farch_fpga_ver(struct efx_nic *efx)
1723 {
1724 efx_oword_t altera_build;
1725 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1726 return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1727 }
1728
1729 void efx_farch_init_common(struct efx_nic *efx)
1730 {
1731 efx_oword_t temp;
1732
1733 /* Set positions of descriptor caches in SRAM. */
1734 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base);
1735 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1736 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base);
1737 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1738
1739 /* Set TX descriptor cache size. */
1740 BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1741 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1742 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1743
1744 /* Set RX descriptor cache size. Set low watermark to size-8, as
1745 * this allows most efficient prefetching.
1746 */
1747 BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1748 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1749 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1750 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1751 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1752
1753 /* Program INT_KER address */
1754 EFX_POPULATE_OWORD_2(temp,
1755 FRF_AZ_NORM_INT_VEC_DIS_KER,
1756 EFX_INT_MODE_USE_MSI(efx),
1757 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1758 efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1759
1760 if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1761 /* Use an interrupt level unused by event queues */
1762 efx->irq_level = 0x1f;
1763 else
1764 /* Use a valid MSI-X vector */
1765 efx->irq_level = 0;
1766
1767 /* Enable all the genuinely fatal interrupts. (They are still
1768 * masked by the overall interrupt mask, controlled by
1769 * falcon_interrupts()).
1770 *
1771 * Note: All other fatal interrupts are enabled
1772 */
1773 EFX_POPULATE_OWORD_3(temp,
1774 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1775 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1776 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
1777 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
1778 EFX_INVERT_OWORD(temp);
1779 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1780
1781 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1782 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1783 */
1784 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1785 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1786 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1787 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1788 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1);
1789 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1790 /* Enable SW_EV to inherit in char driver - assume harmless here */
1791 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1792 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1793 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
1794 /* Disable hardware watchdog which can misfire */
1795 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
1796 /* Squash TX of packets of 16 bytes or less */
1797 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1798 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
1799
1800 EFX_POPULATE_OWORD_4(temp,
1801 /* Default values */
1802 FRF_BZ_TX_PACE_SB_NOT_AF, 0x15,
1803 FRF_BZ_TX_PACE_SB_AF, 0xb,
1804 FRF_BZ_TX_PACE_FB_BASE, 0,
1805 /* Allow large pace values in the fast bin. */
1806 FRF_BZ_TX_PACE_BIN_TH,
1807 FFE_BZ_TX_PACE_RESERVED);
1808 efx_writeo(efx, &temp, FR_BZ_TX_PACE);
1809 }
1810
1811 /**************************************************************************
1812 *
1813 * Filter tables
1814 *
1815 **************************************************************************
1816 */
1817
1818 /* "Fudge factors" - difference between programmed value and actual depth.
1819 * Due to pipelined implementation we need to program H/W with a value that
1820 * is larger than the hop limit we want.
1821 */
1822 #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD 3
1823 #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL 1
1824
1825 /* Hard maximum search limit. Hardware will time-out beyond 200-something.
1826 * We also need to avoid infinite loops in efx_farch_filter_search() when the
1827 * table is full.
1828 */
1829 #define EFX_FARCH_FILTER_CTL_SRCH_MAX 200
1830
1831 /* Don't try very hard to find space for performance hints, as this is
1832 * counter-productive. */
1833 #define EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX 5
1834
1835 enum efx_farch_filter_type {
1836 EFX_FARCH_FILTER_TCP_FULL = 0,
1837 EFX_FARCH_FILTER_TCP_WILD,
1838 EFX_FARCH_FILTER_UDP_FULL,
1839 EFX_FARCH_FILTER_UDP_WILD,
1840 EFX_FARCH_FILTER_MAC_FULL = 4,
1841 EFX_FARCH_FILTER_MAC_WILD,
1842 EFX_FARCH_FILTER_UC_DEF = 8,
1843 EFX_FARCH_FILTER_MC_DEF,
1844 EFX_FARCH_FILTER_TYPE_COUNT, /* number of specific types */
1845 };
1846
1847 enum efx_farch_filter_table_id {
1848 EFX_FARCH_FILTER_TABLE_RX_IP = 0,
1849 EFX_FARCH_FILTER_TABLE_RX_MAC,
1850 EFX_FARCH_FILTER_TABLE_RX_DEF,
1851 EFX_FARCH_FILTER_TABLE_TX_MAC,
1852 EFX_FARCH_FILTER_TABLE_COUNT,
1853 };
1854
1855 enum efx_farch_filter_index {
1856 EFX_FARCH_FILTER_INDEX_UC_DEF,
1857 EFX_FARCH_FILTER_INDEX_MC_DEF,
1858 EFX_FARCH_FILTER_SIZE_RX_DEF,
1859 };
1860
1861 struct efx_farch_filter_spec {
1862 u8 type:4;
1863 u8 priority:4;
1864 u8 flags;
1865 u16 dmaq_id;
1866 u32 data[3];
1867 };
1868
1869 struct efx_farch_filter_table {
1870 enum efx_farch_filter_table_id id;
1871 u32 offset; /* address of table relative to BAR */
1872 unsigned size; /* number of entries */
1873 unsigned step; /* step between entries */
1874 unsigned used; /* number currently used */
1875 unsigned long *used_bitmap;
1876 struct efx_farch_filter_spec *spec;
1877 unsigned search_limit[EFX_FARCH_FILTER_TYPE_COUNT];
1878 };
1879
1880 struct efx_farch_filter_state {
1881 struct efx_farch_filter_table table[EFX_FARCH_FILTER_TABLE_COUNT];
1882 };
1883
1884 static void
1885 efx_farch_filter_table_clear_entry(struct efx_nic *efx,
1886 struct efx_farch_filter_table *table,
1887 unsigned int filter_idx);
1888
1889 /* The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
1890 * key derived from the n-tuple. The initial LFSR state is 0xffff. */
1891 static u16 efx_farch_filter_hash(u32 key)
1892 {
1893 u16 tmp;
1894
1895 /* First 16 rounds */
1896 tmp = 0x1fff ^ key >> 16;
1897 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1898 tmp = tmp ^ tmp >> 9;
1899 /* Last 16 rounds */
1900 tmp = tmp ^ tmp << 13 ^ key;
1901 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1902 return tmp ^ tmp >> 9;
1903 }
1904
1905 /* To allow for hash collisions, filter search continues at these
1906 * increments from the first possible entry selected by the hash. */
1907 static u16 efx_farch_filter_increment(u32 key)
1908 {
1909 return key * 2 - 1;
1910 }
1911
1912 static enum efx_farch_filter_table_id
1913 efx_farch_filter_spec_table_id(const struct efx_farch_filter_spec *spec)
1914 {
1915 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1916 (EFX_FARCH_FILTER_TCP_FULL >> 2));
1917 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1918 (EFX_FARCH_FILTER_TCP_WILD >> 2));
1919 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1920 (EFX_FARCH_FILTER_UDP_FULL >> 2));
1921 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1922 (EFX_FARCH_FILTER_UDP_WILD >> 2));
1923 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1924 (EFX_FARCH_FILTER_MAC_FULL >> 2));
1925 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1926 (EFX_FARCH_FILTER_MAC_WILD >> 2));
1927 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_TX_MAC !=
1928 EFX_FARCH_FILTER_TABLE_RX_MAC + 2);
1929 return (spec->type >> 2) + ((spec->flags & EFX_FILTER_FLAG_TX) ? 2 : 0);
1930 }
1931
1932 static void efx_farch_filter_push_rx_config(struct efx_nic *efx)
1933 {
1934 struct efx_farch_filter_state *state = efx->filter_state;
1935 struct efx_farch_filter_table *table;
1936 efx_oword_t filter_ctl;
1937
1938 efx_reado(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
1939
1940 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
1941 EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_FULL_SRCH_LIMIT,
1942 table->search_limit[EFX_FARCH_FILTER_TCP_FULL] +
1943 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1944 EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_WILD_SRCH_LIMIT,
1945 table->search_limit[EFX_FARCH_FILTER_TCP_WILD] +
1946 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1947 EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_FULL_SRCH_LIMIT,
1948 table->search_limit[EFX_FARCH_FILTER_UDP_FULL] +
1949 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1950 EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_WILD_SRCH_LIMIT,
1951 table->search_limit[EFX_FARCH_FILTER_UDP_WILD] +
1952 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1953
1954 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
1955 if (table->size) {
1956 EFX_SET_OWORD_FIELD(
1957 filter_ctl, FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
1958 table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
1959 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1960 EFX_SET_OWORD_FIELD(
1961 filter_ctl, FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
1962 table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
1963 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1964 }
1965
1966 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
1967 if (table->size) {
1968 EFX_SET_OWORD_FIELD(
1969 filter_ctl, FRF_CZ_UNICAST_NOMATCH_Q_ID,
1970 table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].dmaq_id);
1971 EFX_SET_OWORD_FIELD(
1972 filter_ctl, FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED,
1973 !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1974 EFX_FILTER_FLAG_RX_RSS));
1975 EFX_SET_OWORD_FIELD(
1976 filter_ctl, FRF_CZ_MULTICAST_NOMATCH_Q_ID,
1977 table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].dmaq_id);
1978 EFX_SET_OWORD_FIELD(
1979 filter_ctl, FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED,
1980 !!(table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1981 EFX_FILTER_FLAG_RX_RSS));
1982
1983 /* There is a single bit to enable RX scatter for all
1984 * unmatched packets. Only set it if scatter is
1985 * enabled in both filter specs.
1986 */
1987 EFX_SET_OWORD_FIELD(
1988 filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
1989 !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1990 table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1991 EFX_FILTER_FLAG_RX_SCATTER));
1992 } else {
1993 /* We don't expose 'default' filters because unmatched
1994 * packets always go to the queue number found in the
1995 * RSS table. But we still need to set the RX scatter
1996 * bit here.
1997 */
1998 EFX_SET_OWORD_FIELD(
1999 filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
2000 efx->rx_scatter);
2001 }
2002
2003 efx_writeo(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
2004 }
2005
2006 static void efx_farch_filter_push_tx_limits(struct efx_nic *efx)
2007 {
2008 struct efx_farch_filter_state *state = efx->filter_state;
2009 struct efx_farch_filter_table *table;
2010 efx_oword_t tx_cfg;
2011
2012 efx_reado(efx, &tx_cfg, FR_AZ_TX_CFG);
2013
2014 table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
2015 if (table->size) {
2016 EFX_SET_OWORD_FIELD(
2017 tx_cfg, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE,
2018 table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
2019 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
2020 EFX_SET_OWORD_FIELD(
2021 tx_cfg, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE,
2022 table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
2023 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
2024 }
2025
2026 efx_writeo(efx, &tx_cfg, FR_AZ_TX_CFG);
2027 }
2028
2029 static int
2030 efx_farch_filter_from_gen_spec(struct efx_farch_filter_spec *spec,
2031 const struct efx_filter_spec *gen_spec)
2032 {
2033 bool is_full = false;
2034
2035 if ((gen_spec->flags & EFX_FILTER_FLAG_RX_RSS) &&
2036 gen_spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT)
2037 return -EINVAL;
2038
2039 spec->priority = gen_spec->priority;
2040 spec->flags = gen_spec->flags;
2041 spec->dmaq_id = gen_spec->dmaq_id;
2042
2043 switch (gen_spec->match_flags) {
2044 case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2045 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
2046 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT):
2047 is_full = true;
2048 /* fall through */
2049 case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2050 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT): {
2051 __be32 rhost, host1, host2;
2052 __be16 rport, port1, port2;
2053
2054 EFX_WARN_ON_PARANOID(!(gen_spec->flags & EFX_FILTER_FLAG_RX));
2055
2056 if (gen_spec->ether_type != htons(ETH_P_IP))
2057 return -EPROTONOSUPPORT;
2058 if (gen_spec->loc_port == 0 ||
2059 (is_full && gen_spec->rem_port == 0))
2060 return -EADDRNOTAVAIL;
2061 switch (gen_spec->ip_proto) {
2062 case IPPROTO_TCP:
2063 spec->type = (is_full ? EFX_FARCH_FILTER_TCP_FULL :
2064 EFX_FARCH_FILTER_TCP_WILD);
2065 break;
2066 case IPPROTO_UDP:
2067 spec->type = (is_full ? EFX_FARCH_FILTER_UDP_FULL :
2068 EFX_FARCH_FILTER_UDP_WILD);
2069 break;
2070 default:
2071 return -EPROTONOSUPPORT;
2072 }
2073
2074 /* Filter is constructed in terms of source and destination,
2075 * with the odd wrinkle that the ports are swapped in a UDP
2076 * wildcard filter. We need to convert from local and remote
2077 * (= zero for wildcard) addresses.
2078 */
2079 rhost = is_full ? gen_spec->rem_host[0] : 0;
2080 rport = is_full ? gen_spec->rem_port : 0;
2081 host1 = rhost;
2082 host2 = gen_spec->loc_host[0];
2083 if (!is_full && gen_spec->ip_proto == IPPROTO_UDP) {
2084 port1 = gen_spec->loc_port;
2085 port2 = rport;
2086 } else {
2087 port1 = rport;
2088 port2 = gen_spec->loc_port;
2089 }
2090 spec->data[0] = ntohl(host1) << 16 | ntohs(port1);
2091 spec->data[1] = ntohs(port2) << 16 | ntohl(host1) >> 16;
2092 spec->data[2] = ntohl(host2);
2093
2094 break;
2095 }
2096
2097 case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID:
2098 is_full = true;
2099 /* fall through */
2100 case EFX_FILTER_MATCH_LOC_MAC:
2101 spec->type = (is_full ? EFX_FARCH_FILTER_MAC_FULL :
2102 EFX_FARCH_FILTER_MAC_WILD);
2103 spec->data[0] = is_full ? ntohs(gen_spec->outer_vid) : 0;
2104 spec->data[1] = (gen_spec->loc_mac[2] << 24 |
2105 gen_spec->loc_mac[3] << 16 |
2106 gen_spec->loc_mac[4] << 8 |
2107 gen_spec->loc_mac[5]);
2108 spec->data[2] = (gen_spec->loc_mac[0] << 8 |
2109 gen_spec->loc_mac[1]);
2110 break;
2111
2112 case EFX_FILTER_MATCH_LOC_MAC_IG:
2113 spec->type = (is_multicast_ether_addr(gen_spec->loc_mac) ?
2114 EFX_FARCH_FILTER_MC_DEF :
2115 EFX_FARCH_FILTER_UC_DEF);
2116 memset(spec->data, 0, sizeof(spec->data)); /* ensure equality */
2117 break;
2118
2119 default:
2120 return -EPROTONOSUPPORT;
2121 }
2122
2123 return 0;
2124 }
2125
2126 static void
2127 efx_farch_filter_to_gen_spec(struct efx_filter_spec *gen_spec,
2128 const struct efx_farch_filter_spec *spec)
2129 {
2130 bool is_full = false;
2131
2132 /* *gen_spec should be completely initialised, to be consistent
2133 * with efx_filter_init_{rx,tx}() and in case we want to copy
2134 * it back to userland.
2135 */
2136 memset(gen_spec, 0, sizeof(*gen_spec));
2137
2138 gen_spec->priority = spec->priority;
2139 gen_spec->flags = spec->flags;
2140 gen_spec->dmaq_id = spec->dmaq_id;
2141
2142 switch (spec->type) {
2143 case EFX_FARCH_FILTER_TCP_FULL:
2144 case EFX_FARCH_FILTER_UDP_FULL:
2145 is_full = true;
2146 /* fall through */
2147 case EFX_FARCH_FILTER_TCP_WILD:
2148 case EFX_FARCH_FILTER_UDP_WILD: {
2149 __be32 host1, host2;
2150 __be16 port1, port2;
2151
2152 gen_spec->match_flags =
2153 EFX_FILTER_MATCH_ETHER_TYPE |
2154 EFX_FILTER_MATCH_IP_PROTO |
2155 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
2156 if (is_full)
2157 gen_spec->match_flags |= (EFX_FILTER_MATCH_REM_HOST |
2158 EFX_FILTER_MATCH_REM_PORT);
2159 gen_spec->ether_type = htons(ETH_P_IP);
2160 gen_spec->ip_proto =
2161 (spec->type == EFX_FARCH_FILTER_TCP_FULL ||
2162 spec->type == EFX_FARCH_FILTER_TCP_WILD) ?
2163 IPPROTO_TCP : IPPROTO_UDP;
2164
2165 host1 = htonl(spec->data[0] >> 16 | spec->data[1] << 16);
2166 port1 = htons(spec->data[0]);
2167 host2 = htonl(spec->data[2]);
2168 port2 = htons(spec->data[1] >> 16);
2169 if (spec->flags & EFX_FILTER_FLAG_TX) {
2170 gen_spec->loc_host[0] = host1;
2171 gen_spec->rem_host[0] = host2;
2172 } else {
2173 gen_spec->loc_host[0] = host2;
2174 gen_spec->rem_host[0] = host1;
2175 }
2176 if (!!(gen_spec->flags & EFX_FILTER_FLAG_TX) ^
2177 (!is_full && gen_spec->ip_proto == IPPROTO_UDP)) {
2178 gen_spec->loc_port = port1;
2179 gen_spec->rem_port = port2;
2180 } else {
2181 gen_spec->loc_port = port2;
2182 gen_spec->rem_port = port1;
2183 }
2184
2185 break;
2186 }
2187
2188 case EFX_FARCH_FILTER_MAC_FULL:
2189 is_full = true;
2190 /* fall through */
2191 case EFX_FARCH_FILTER_MAC_WILD:
2192 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC;
2193 if (is_full)
2194 gen_spec->match_flags |= EFX_FILTER_MATCH_OUTER_VID;
2195 gen_spec->loc_mac[0] = spec->data[2] >> 8;
2196 gen_spec->loc_mac[1] = spec->data[2];
2197 gen_spec->loc_mac[2] = spec->data[1] >> 24;
2198 gen_spec->loc_mac[3] = spec->data[1] >> 16;
2199 gen_spec->loc_mac[4] = spec->data[1] >> 8;
2200 gen_spec->loc_mac[5] = spec->data[1];
2201 gen_spec->outer_vid = htons(spec->data[0]);
2202 break;
2203
2204 case EFX_FARCH_FILTER_UC_DEF:
2205 case EFX_FARCH_FILTER_MC_DEF:
2206 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC_IG;
2207 gen_spec->loc_mac[0] = spec->type == EFX_FARCH_FILTER_MC_DEF;
2208 break;
2209
2210 default:
2211 WARN_ON(1);
2212 break;
2213 }
2214 }
2215
2216 static void
2217 efx_farch_filter_init_rx_auto(struct efx_nic *efx,
2218 struct efx_farch_filter_spec *spec)
2219 {
2220 /* If there's only one channel then disable RSS for non VF
2221 * traffic, thereby allowing VFs to use RSS when the PF can't.
2222 */
2223 spec->priority = EFX_FILTER_PRI_AUTO;
2224 spec->flags = (EFX_FILTER_FLAG_RX |
2225 (efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0) |
2226 (efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0));
2227 spec->dmaq_id = 0;
2228 }
2229
2230 /* Build a filter entry and return its n-tuple key. */
2231 static u32 efx_farch_filter_build(efx_oword_t *filter,
2232 struct efx_farch_filter_spec *spec)
2233 {
2234 u32 data3;
2235
2236 switch (efx_farch_filter_spec_table_id(spec)) {
2237 case EFX_FARCH_FILTER_TABLE_RX_IP: {
2238 bool is_udp = (spec->type == EFX_FARCH_FILTER_UDP_FULL ||
2239 spec->type == EFX_FARCH_FILTER_UDP_WILD);
2240 EFX_POPULATE_OWORD_7(
2241 *filter,
2242 FRF_BZ_RSS_EN,
2243 !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2244 FRF_BZ_SCATTER_EN,
2245 !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2246 FRF_BZ_TCP_UDP, is_udp,
2247 FRF_BZ_RXQ_ID, spec->dmaq_id,
2248 EFX_DWORD_2, spec->data[2],
2249 EFX_DWORD_1, spec->data[1],
2250 EFX_DWORD_0, spec->data[0]);
2251 data3 = is_udp;
2252 break;
2253 }
2254
2255 case EFX_FARCH_FILTER_TABLE_RX_MAC: {
2256 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2257 EFX_POPULATE_OWORD_7(
2258 *filter,
2259 FRF_CZ_RMFT_RSS_EN,
2260 !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2261 FRF_CZ_RMFT_SCATTER_EN,
2262 !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2263 FRF_CZ_RMFT_RXQ_ID, spec->dmaq_id,
2264 FRF_CZ_RMFT_WILDCARD_MATCH, is_wild,
2265 FRF_CZ_RMFT_DEST_MAC_HI, spec->data[2],
2266 FRF_CZ_RMFT_DEST_MAC_LO, spec->data[1],
2267 FRF_CZ_RMFT_VLAN_ID, spec->data[0]);
2268 data3 = is_wild;
2269 break;
2270 }
2271
2272 case EFX_FARCH_FILTER_TABLE_TX_MAC: {
2273 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2274 EFX_POPULATE_OWORD_5(*filter,
2275 FRF_CZ_TMFT_TXQ_ID, spec->dmaq_id,
2276 FRF_CZ_TMFT_WILDCARD_MATCH, is_wild,
2277 FRF_CZ_TMFT_SRC_MAC_HI, spec->data[2],
2278 FRF_CZ_TMFT_SRC_MAC_LO, spec->data[1],
2279 FRF_CZ_TMFT_VLAN_ID, spec->data[0]);
2280 data3 = is_wild | spec->dmaq_id << 1;
2281 break;
2282 }
2283
2284 default:
2285 BUG();
2286 }
2287
2288 return spec->data[0] ^ spec->data[1] ^ spec->data[2] ^ data3;
2289 }
2290
2291 static bool efx_farch_filter_equal(const struct efx_farch_filter_spec *left,
2292 const struct efx_farch_filter_spec *right)
2293 {
2294 if (left->type != right->type ||
2295 memcmp(left->data, right->data, sizeof(left->data)))
2296 return false;
2297
2298 if (left->flags & EFX_FILTER_FLAG_TX &&
2299 left->dmaq_id != right->dmaq_id)
2300 return false;
2301
2302 return true;
2303 }
2304
2305 /*
2306 * Construct/deconstruct external filter IDs. At least the RX filter
2307 * IDs must be ordered by matching priority, for RX NFC semantics.
2308 *
2309 * Deconstruction needs to be robust against invalid IDs so that
2310 * efx_filter_remove_id_safe() and efx_filter_get_filter_safe() can
2311 * accept user-provided IDs.
2312 */
2313
2314 #define EFX_FARCH_FILTER_MATCH_PRI_COUNT 5
2315
2316 static const u8 efx_farch_filter_type_match_pri[EFX_FARCH_FILTER_TYPE_COUNT] = {
2317 [EFX_FARCH_FILTER_TCP_FULL] = 0,
2318 [EFX_FARCH_FILTER_UDP_FULL] = 0,
2319 [EFX_FARCH_FILTER_TCP_WILD] = 1,
2320 [EFX_FARCH_FILTER_UDP_WILD] = 1,
2321 [EFX_FARCH_FILTER_MAC_FULL] = 2,
2322 [EFX_FARCH_FILTER_MAC_WILD] = 3,
2323 [EFX_FARCH_FILTER_UC_DEF] = 4,
2324 [EFX_FARCH_FILTER_MC_DEF] = 4,
2325 };
2326
2327 static const enum efx_farch_filter_table_id efx_farch_filter_range_table[] = {
2328 EFX_FARCH_FILTER_TABLE_RX_IP, /* RX match pri 0 */
2329 EFX_FARCH_FILTER_TABLE_RX_IP,
2330 EFX_FARCH_FILTER_TABLE_RX_MAC,
2331 EFX_FARCH_FILTER_TABLE_RX_MAC,
2332 EFX_FARCH_FILTER_TABLE_RX_DEF, /* RX match pri 4 */
2333 EFX_FARCH_FILTER_TABLE_TX_MAC, /* TX match pri 0 */
2334 EFX_FARCH_FILTER_TABLE_TX_MAC, /* TX match pri 1 */
2335 };
2336
2337 #define EFX_FARCH_FILTER_INDEX_WIDTH 13
2338 #define EFX_FARCH_FILTER_INDEX_MASK ((1 << EFX_FARCH_FILTER_INDEX_WIDTH) - 1)
2339
2340 static inline u32
2341 efx_farch_filter_make_id(const struct efx_farch_filter_spec *spec,
2342 unsigned int index)
2343 {
2344 unsigned int range;
2345
2346 range = efx_farch_filter_type_match_pri[spec->type];
2347 if (!(spec->flags & EFX_FILTER_FLAG_RX))
2348 range += EFX_FARCH_FILTER_MATCH_PRI_COUNT;
2349
2350 return range << EFX_FARCH_FILTER_INDEX_WIDTH | index;
2351 }
2352
2353 static inline enum efx_farch_filter_table_id
2354 efx_farch_filter_id_table_id(u32 id)
2355 {
2356 unsigned int range = id >> EFX_FARCH_FILTER_INDEX_WIDTH;
2357
2358 if (range < ARRAY_SIZE(efx_farch_filter_range_table))
2359 return efx_farch_filter_range_table[range];
2360 else
2361 return EFX_FARCH_FILTER_TABLE_COUNT; /* invalid */
2362 }
2363
2364 static inline unsigned int efx_farch_filter_id_index(u32 id)
2365 {
2366 return id & EFX_FARCH_FILTER_INDEX_MASK;
2367 }
2368
2369 u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx)
2370 {
2371 struct efx_farch_filter_state *state = efx->filter_state;
2372 unsigned int range = EFX_FARCH_FILTER_MATCH_PRI_COUNT - 1;
2373 enum efx_farch_filter_table_id table_id;
2374
2375 do {
2376 table_id = efx_farch_filter_range_table[range];
2377 if (state->table[table_id].size != 0)
2378 return range << EFX_FARCH_FILTER_INDEX_WIDTH |
2379 state->table[table_id].size;
2380 } while (range--);
2381
2382 return 0;
2383 }
2384
2385 s32 efx_farch_filter_insert(struct efx_nic *efx,
2386 struct efx_filter_spec *gen_spec,
2387 bool replace_equal)
2388 {
2389 struct efx_farch_filter_state *state = efx->filter_state;
2390 struct efx_farch_filter_table *table;
2391 struct efx_farch_filter_spec spec;
2392 efx_oword_t filter;
2393 int rep_index, ins_index;
2394 unsigned int depth = 0;
2395 int rc;
2396
2397 rc = efx_farch_filter_from_gen_spec(&spec, gen_spec);
2398 if (rc)
2399 return rc;
2400
2401 table = &state->table[efx_farch_filter_spec_table_id(&spec)];
2402 if (table->size == 0)
2403 return -EINVAL;
2404
2405 netif_vdbg(efx, hw, efx->net_dev,
2406 "%s: type %d search_limit=%d", __func__, spec.type,
2407 table->search_limit[spec.type]);
2408
2409 if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2410 /* One filter spec per type */
2411 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_UC_DEF != 0);
2412 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_MC_DEF !=
2413 EFX_FARCH_FILTER_MC_DEF - EFX_FARCH_FILTER_UC_DEF);
2414 rep_index = spec.type - EFX_FARCH_FILTER_UC_DEF;
2415 ins_index = rep_index;
2416
2417 spin_lock_bh(&efx->filter_lock);
2418 } else {
2419 /* Search concurrently for
2420 * (1) a filter to be replaced (rep_index): any filter
2421 * with the same match values, up to the current
2422 * search depth for this type, and
2423 * (2) the insertion point (ins_index): (1) or any
2424 * free slot before it or up to the maximum search
2425 * depth for this priority
2426 * We fail if we cannot find (2).
2427 *
2428 * We can stop once either
2429 * (a) we find (1), in which case we have definitely
2430 * found (2) as well; or
2431 * (b) we have searched exhaustively for (1), and have
2432 * either found (2) or searched exhaustively for it
2433 */
2434 u32 key = efx_farch_filter_build(&filter, &spec);
2435 unsigned int hash = efx_farch_filter_hash(key);
2436 unsigned int incr = efx_farch_filter_increment(key);
2437 unsigned int max_rep_depth = table->search_limit[spec.type];
2438 unsigned int max_ins_depth =
2439 spec.priority <= EFX_FILTER_PRI_HINT ?
2440 EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX :
2441 EFX_FARCH_FILTER_CTL_SRCH_MAX;
2442 unsigned int i = hash & (table->size - 1);
2443
2444 ins_index = -1;
2445 depth = 1;
2446
2447 spin_lock_bh(&efx->filter_lock);
2448
2449 for (;;) {
2450 if (!test_bit(i, table->used_bitmap)) {
2451 if (ins_index < 0)
2452 ins_index = i;
2453 } else if (efx_farch_filter_equal(&spec,
2454 &table->spec[i])) {
2455 /* Case (a) */
2456 if (ins_index < 0)
2457 ins_index = i;
2458 rep_index = i;
2459 break;
2460 }
2461
2462 if (depth >= max_rep_depth &&
2463 (ins_index >= 0 || depth >= max_ins_depth)) {
2464 /* Case (b) */
2465 if (ins_index < 0) {
2466 rc = -EBUSY;
2467 goto out;
2468 }
2469 rep_index = -1;
2470 break;
2471 }
2472
2473 i = (i + incr) & (table->size - 1);
2474 ++depth;
2475 }
2476 }
2477
2478 /* If we found a filter to be replaced, check whether we
2479 * should do so
2480 */
2481 if (rep_index >= 0) {
2482 struct efx_farch_filter_spec *saved_spec =
2483 &table->spec[rep_index];
2484
2485 if (spec.priority == saved_spec->priority && !replace_equal) {
2486 rc = -EEXIST;
2487 goto out;
2488 }
2489 if (spec.priority < saved_spec->priority) {
2490 rc = -EPERM;
2491 goto out;
2492 }
2493 if (saved_spec->priority == EFX_FILTER_PRI_AUTO ||
2494 saved_spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO)
2495 spec.flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
2496 }
2497
2498 /* Insert the filter */
2499 if (ins_index != rep_index) {
2500 __set_bit(ins_index, table->used_bitmap);
2501 ++table->used;
2502 }
2503 table->spec[ins_index] = spec;
2504
2505 if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2506 efx_farch_filter_push_rx_config(efx);
2507 } else {
2508 if (table->search_limit[spec.type] < depth) {
2509 table->search_limit[spec.type] = depth;
2510 if (spec.flags & EFX_FILTER_FLAG_TX)
2511 efx_farch_filter_push_tx_limits(efx);
2512 else
2513 efx_farch_filter_push_rx_config(efx);
2514 }
2515
2516 efx_writeo(efx, &filter,
2517 table->offset + table->step * ins_index);
2518
2519 /* If we were able to replace a filter by inserting
2520 * at a lower depth, clear the replaced filter
2521 */
2522 if (ins_index != rep_index && rep_index >= 0)
2523 efx_farch_filter_table_clear_entry(efx, table,
2524 rep_index);
2525 }
2526
2527 netif_vdbg(efx, hw, efx->net_dev,
2528 "%s: filter type %d index %d rxq %u set",
2529 __func__, spec.type, ins_index, spec.dmaq_id);
2530 rc = efx_farch_filter_make_id(&spec, ins_index);
2531
2532 out:
2533 spin_unlock_bh(&efx->filter_lock);
2534 return rc;
2535 }
2536
2537 static void
2538 efx_farch_filter_table_clear_entry(struct efx_nic *efx,
2539 struct efx_farch_filter_table *table,
2540 unsigned int filter_idx)
2541 {
2542 static efx_oword_t filter;
2543
2544 EFX_WARN_ON_PARANOID(!test_bit(filter_idx, table->used_bitmap));
2545 BUG_ON(table->offset == 0); /* can't clear MAC default filters */
2546
2547 __clear_bit(filter_idx, table->used_bitmap);
2548 --table->used;
2549 memset(&table->spec[filter_idx], 0, sizeof(table->spec[0]));
2550
2551 efx_writeo(efx, &filter, table->offset + table->step * filter_idx);
2552
2553 /* If this filter required a greater search depth than
2554 * any other, the search limit for its type can now be
2555 * decreased. However, it is hard to determine that
2556 * unless the table has become completely empty - in
2557 * which case, all its search limits can be set to 0.
2558 */
2559 if (unlikely(table->used == 0)) {
2560 memset(table->search_limit, 0, sizeof(table->search_limit));
2561 if (table->id == EFX_FARCH_FILTER_TABLE_TX_MAC)
2562 efx_farch_filter_push_tx_limits(efx);
2563 else
2564 efx_farch_filter_push_rx_config(efx);
2565 }
2566 }
2567
2568 static int efx_farch_filter_remove(struct efx_nic *efx,
2569 struct efx_farch_filter_table *table,
2570 unsigned int filter_idx,
2571 enum efx_filter_priority priority)
2572 {
2573 struct efx_farch_filter_spec *spec = &table->spec[filter_idx];
2574
2575 if (!test_bit(filter_idx, table->used_bitmap) ||
2576 spec->priority != priority)
2577 return -ENOENT;
2578
2579 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
2580 efx_farch_filter_init_rx_auto(efx, spec);
2581 efx_farch_filter_push_rx_config(efx);
2582 } else {
2583 efx_farch_filter_table_clear_entry(efx, table, filter_idx);
2584 }
2585
2586 return 0;
2587 }
2588
2589 int efx_farch_filter_remove_safe(struct efx_nic *efx,
2590 enum efx_filter_priority priority,
2591 u32 filter_id)
2592 {
2593 struct efx_farch_filter_state *state = efx->filter_state;
2594 enum efx_farch_filter_table_id table_id;
2595 struct efx_farch_filter_table *table;
2596 unsigned int filter_idx;
2597 struct efx_farch_filter_spec *spec;
2598 int rc;
2599
2600 table_id = efx_farch_filter_id_table_id(filter_id);
2601 if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2602 return -ENOENT;
2603 table = &state->table[table_id];
2604
2605 filter_idx = efx_farch_filter_id_index(filter_id);
2606 if (filter_idx >= table->size)
2607 return -ENOENT;
2608 spec = &table->spec[filter_idx];
2609
2610 spin_lock_bh(&efx->filter_lock);
2611 rc = efx_farch_filter_remove(efx, table, filter_idx, priority);
2612 spin_unlock_bh(&efx->filter_lock);
2613
2614 return rc;
2615 }
2616
2617 int efx_farch_filter_get_safe(struct efx_nic *efx,
2618 enum efx_filter_priority priority,
2619 u32 filter_id, struct efx_filter_spec *spec_buf)
2620 {
2621 struct efx_farch_filter_state *state = efx->filter_state;
2622 enum efx_farch_filter_table_id table_id;
2623 struct efx_farch_filter_table *table;
2624 struct efx_farch_filter_spec *spec;
2625 unsigned int filter_idx;
2626 int rc;
2627
2628 table_id = efx_farch_filter_id_table_id(filter_id);
2629 if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2630 return -ENOENT;
2631 table = &state->table[table_id];
2632
2633 filter_idx = efx_farch_filter_id_index(filter_id);
2634 if (filter_idx >= table->size)
2635 return -ENOENT;
2636 spec = &table->spec[filter_idx];
2637
2638 spin_lock_bh(&efx->filter_lock);
2639
2640 if (test_bit(filter_idx, table->used_bitmap) &&
2641 spec->priority == priority) {
2642 efx_farch_filter_to_gen_spec(spec_buf, spec);
2643 rc = 0;
2644 } else {
2645 rc = -ENOENT;
2646 }
2647
2648 spin_unlock_bh(&efx->filter_lock);
2649
2650 return rc;
2651 }
2652
2653 static void
2654 efx_farch_filter_table_clear(struct efx_nic *efx,
2655 enum efx_farch_filter_table_id table_id,
2656 enum efx_filter_priority priority)
2657 {
2658 struct efx_farch_filter_state *state = efx->filter_state;
2659 struct efx_farch_filter_table *table = &state->table[table_id];
2660 unsigned int filter_idx;
2661
2662 spin_lock_bh(&efx->filter_lock);
2663 for (filter_idx = 0; filter_idx < table->size; ++filter_idx) {
2664 if (table->spec[filter_idx].priority != EFX_FILTER_PRI_AUTO)
2665 efx_farch_filter_remove(efx, table,
2666 filter_idx, priority);
2667 }
2668 spin_unlock_bh(&efx->filter_lock);
2669 }
2670
2671 int efx_farch_filter_clear_rx(struct efx_nic *efx,
2672 enum efx_filter_priority priority)
2673 {
2674 efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_IP,
2675 priority);
2676 efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_MAC,
2677 priority);
2678 efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_DEF,
2679 priority);
2680 return 0;
2681 }
2682
2683 u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
2684 enum efx_filter_priority priority)
2685 {
2686 struct efx_farch_filter_state *state = efx->filter_state;
2687 enum efx_farch_filter_table_id table_id;
2688 struct efx_farch_filter_table *table;
2689 unsigned int filter_idx;
2690 u32 count = 0;
2691
2692 spin_lock_bh(&efx->filter_lock);
2693
2694 for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2695 table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2696 table_id++) {
2697 table = &state->table[table_id];
2698 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2699 if (test_bit(filter_idx, table->used_bitmap) &&
2700 table->spec[filter_idx].priority == priority)
2701 ++count;
2702 }
2703 }
2704
2705 spin_unlock_bh(&efx->filter_lock);
2706
2707 return count;
2708 }
2709
2710 s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
2711 enum efx_filter_priority priority,
2712 u32 *buf, u32 size)
2713 {
2714 struct efx_farch_filter_state *state = efx->filter_state;
2715 enum efx_farch_filter_table_id table_id;
2716 struct efx_farch_filter_table *table;
2717 unsigned int filter_idx;
2718 s32 count = 0;
2719
2720 spin_lock_bh(&efx->filter_lock);
2721
2722 for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2723 table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2724 table_id++) {
2725 table = &state->table[table_id];
2726 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2727 if (test_bit(filter_idx, table->used_bitmap) &&
2728 table->spec[filter_idx].priority == priority) {
2729 if (count == size) {
2730 count = -EMSGSIZE;
2731 goto out;
2732 }
2733 buf[count++] = efx_farch_filter_make_id(
2734 &table->spec[filter_idx], filter_idx);
2735 }
2736 }
2737 }
2738 out:
2739 spin_unlock_bh(&efx->filter_lock);
2740
2741 return count;
2742 }
2743
2744 /* Restore filter stater after reset */
2745 void efx_farch_filter_table_restore(struct efx_nic *efx)
2746 {
2747 struct efx_farch_filter_state *state = efx->filter_state;
2748 enum efx_farch_filter_table_id table_id;
2749 struct efx_farch_filter_table *table;
2750 efx_oword_t filter;
2751 unsigned int filter_idx;
2752
2753 spin_lock_bh(&efx->filter_lock);
2754
2755 for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2756 table = &state->table[table_id];
2757
2758 /* Check whether this is a regular register table */
2759 if (table->step == 0)
2760 continue;
2761
2762 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2763 if (!test_bit(filter_idx, table->used_bitmap))
2764 continue;
2765 efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2766 efx_writeo(efx, &filter,
2767 table->offset + table->step * filter_idx);
2768 }
2769 }
2770
2771 efx_farch_filter_push_rx_config(efx);
2772 efx_farch_filter_push_tx_limits(efx);
2773
2774 spin_unlock_bh(&efx->filter_lock);
2775 }
2776
2777 void efx_farch_filter_table_remove(struct efx_nic *efx)
2778 {
2779 struct efx_farch_filter_state *state = efx->filter_state;
2780 enum efx_farch_filter_table_id table_id;
2781
2782 for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2783 kfree(state->table[table_id].used_bitmap);
2784 vfree(state->table[table_id].spec);
2785 }
2786 kfree(state);
2787 }
2788
2789 int efx_farch_filter_table_probe(struct efx_nic *efx)
2790 {
2791 struct efx_farch_filter_state *state;
2792 struct efx_farch_filter_table *table;
2793 unsigned table_id;
2794
2795 state = kzalloc(sizeof(struct efx_farch_filter_state), GFP_KERNEL);
2796 if (!state)
2797 return -ENOMEM;
2798 efx->filter_state = state;
2799
2800 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2801 table->id = EFX_FARCH_FILTER_TABLE_RX_IP;
2802 table->offset = FR_BZ_RX_FILTER_TBL0;
2803 table->size = FR_BZ_RX_FILTER_TBL0_ROWS;
2804 table->step = FR_BZ_RX_FILTER_TBL0_STEP;
2805
2806 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
2807 table->id = EFX_FARCH_FILTER_TABLE_RX_MAC;
2808 table->offset = FR_CZ_RX_MAC_FILTER_TBL0;
2809 table->size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
2810 table->step = FR_CZ_RX_MAC_FILTER_TBL0_STEP;
2811
2812 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2813 table->id = EFX_FARCH_FILTER_TABLE_RX_DEF;
2814 table->size = EFX_FARCH_FILTER_SIZE_RX_DEF;
2815
2816 table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
2817 table->id = EFX_FARCH_FILTER_TABLE_TX_MAC;
2818 table->offset = FR_CZ_TX_MAC_FILTER_TBL0;
2819 table->size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS;
2820 table->step = FR_CZ_TX_MAC_FILTER_TBL0_STEP;
2821
2822 for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2823 table = &state->table[table_id];
2824 if (table->size == 0)
2825 continue;
2826 table->used_bitmap = kcalloc(BITS_TO_LONGS(table->size),
2827 sizeof(unsigned long),
2828 GFP_KERNEL);
2829 if (!table->used_bitmap)
2830 goto fail;
2831 table->spec = vzalloc(table->size * sizeof(*table->spec));
2832 if (!table->spec)
2833 goto fail;
2834 }
2835
2836 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2837 if (table->size) {
2838 /* RX default filters must always exist */
2839 struct efx_farch_filter_spec *spec;
2840 unsigned i;
2841
2842 for (i = 0; i < EFX_FARCH_FILTER_SIZE_RX_DEF; i++) {
2843 spec = &table->spec[i];
2844 spec->type = EFX_FARCH_FILTER_UC_DEF + i;
2845 efx_farch_filter_init_rx_auto(efx, spec);
2846 __set_bit(i, table->used_bitmap);
2847 }
2848 }
2849
2850 efx_farch_filter_push_rx_config(efx);
2851
2852 return 0;
2853
2854 fail:
2855 efx_farch_filter_table_remove(efx);
2856 return -ENOMEM;
2857 }
2858
2859 /* Update scatter enable flags for filters pointing to our own RX queues */
2860 void efx_farch_filter_update_rx_scatter(struct efx_nic *efx)
2861 {
2862 struct efx_farch_filter_state *state = efx->filter_state;
2863 enum efx_farch_filter_table_id table_id;
2864 struct efx_farch_filter_table *table;
2865 efx_oword_t filter;
2866 unsigned int filter_idx;
2867
2868 spin_lock_bh(&efx->filter_lock);
2869
2870 for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2871 table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2872 table_id++) {
2873 table = &state->table[table_id];
2874
2875 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2876 if (!test_bit(filter_idx, table->used_bitmap) ||
2877 table->spec[filter_idx].dmaq_id >=
2878 efx->n_rx_channels)
2879 continue;
2880
2881 if (efx->rx_scatter)
2882 table->spec[filter_idx].flags |=
2883 EFX_FILTER_FLAG_RX_SCATTER;
2884 else
2885 table->spec[filter_idx].flags &=
2886 ~EFX_FILTER_FLAG_RX_SCATTER;
2887
2888 if (table_id == EFX_FARCH_FILTER_TABLE_RX_DEF)
2889 /* Pushed by efx_farch_filter_push_rx_config() */
2890 continue;
2891
2892 efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2893 efx_writeo(efx, &filter,
2894 table->offset + table->step * filter_idx);
2895 }
2896 }
2897
2898 efx_farch_filter_push_rx_config(efx);
2899
2900 spin_unlock_bh(&efx->filter_lock);
2901 }
2902
2903 #ifdef CONFIG_RFS_ACCEL
2904
2905 s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
2906 struct efx_filter_spec *gen_spec)
2907 {
2908 return efx_farch_filter_insert(efx, gen_spec, true);
2909 }
2910
2911 bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2912 unsigned int index)
2913 {
2914 struct efx_farch_filter_state *state = efx->filter_state;
2915 struct efx_farch_filter_table *table =
2916 &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2917
2918 if (test_bit(index, table->used_bitmap) &&
2919 table->spec[index].priority == EFX_FILTER_PRI_HINT &&
2920 rps_may_expire_flow(efx->net_dev, table->spec[index].dmaq_id,
2921 flow_id, index)) {
2922 efx_farch_filter_table_clear_entry(efx, table, index);
2923 return true;
2924 }
2925
2926 return false;
2927 }
2928
2929 #endif /* CONFIG_RFS_ACCEL */
2930
2931 void efx_farch_filter_sync_rx_mode(struct efx_nic *efx)
2932 {
2933 struct net_device *net_dev = efx->net_dev;
2934 struct netdev_hw_addr *ha;
2935 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2936 u32 crc;
2937 int bit;
2938
2939 if (!efx_dev_registered(efx))
2940 return;
2941
2942 netif_addr_lock_bh(net_dev);
2943
2944 efx->unicast_filter = !(net_dev->flags & IFF_PROMISC);
2945
2946 /* Build multicast hash table */
2947 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2948 memset(mc_hash, 0xff, sizeof(*mc_hash));
2949 } else {
2950 memset(mc_hash, 0x00, sizeof(*mc_hash));
2951 netdev_for_each_mc_addr(ha, net_dev) {
2952 crc = ether_crc_le(ETH_ALEN, ha->addr);
2953 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
2954 __set_bit_le(bit, mc_hash);
2955 }
2956
2957 /* Broadcast packets go through the multicast hash filter.
2958 * ether_crc_le() of the broadcast address is 0xbe2612ff
2959 * so we always add bit 0xff to the mask.
2960 */
2961 __set_bit_le(0xff, mc_hash);
2962 }
2963
2964 netif_addr_unlock_bh(net_dev);
2965 }
Linux with added FPC-III support