drivers/net/ethernet/sfc/nic.h

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2013 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #ifndef EFX_NIC_H
  12 #define EFX_NIC_H
  13
  14 #include <linux/net_tstamp.h>
  15 #include <linux/i2c-algo-bit.h>
  16 #include "net_driver.h"
  17 #include "efx.h"
  18 #include "mcdi.h"
  19
  20 enum {
  21         /* Revisions 0-2 were Falcon A0, A1 and B0 respectively.
  22          * They are not supported by this driver but these revision numbers
  23          * form part of the ethtool API for register dumping.
  24          */
  25         EFX_REV_SIENA_A0 = 3,
  26         EFX_REV_HUNT_A0 = 4,
  27 };
  28
  29 static inline int efx_nic_rev(struct efx_nic *efx)
  30 {
  31         return efx->type->revision;
  32 }
  33
  34 u32 efx_farch_fpga_ver(struct efx_nic *efx);
  35
  36 /* Read the current event from the event queue */
  37 static inline efx_qword_t *efx_event(struct efx_channel *channel,
  38                                      unsigned int index)
  39 {
  40         return ((efx_qword_t *) (channel->eventq.buf.addr)) +
  41                 (index & channel->eventq_mask);
  42 }
  43
  44 /* See if an event is present
  45  *
  46  * We check both the high and low dword of the event for all ones.  We
  47  * wrote all ones when we cleared the event, and no valid event can
  48  * have all ones in either its high or low dwords.  This approach is
  49  * robust against reordering.
  50  *
  51  * Note that using a single 64-bit comparison is incorrect; even
  52  * though the CPU read will be atomic, the DMA write may not be.
  53  */
  54 static inline int efx_event_present(efx_qword_t *event)
  55 {
  56         return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
  57                   EFX_DWORD_IS_ALL_ONES(event->dword[1]));
  58 }
  59
  60 /* Returns a pointer to the specified transmit descriptor in the TX
  61  * descriptor queue belonging to the specified channel.
  62  */
  63 static inline efx_qword_t *
  64 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
  65 {
  66         return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
  67 }
  68
  69 /* Get partner of a TX queue, seen as part of the same net core queue */
  70 static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue)
  71 {
  72         if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
  73                 return tx_queue - EFX_TXQ_TYPE_OFFLOAD;
  74         else
  75                 return tx_queue + EFX_TXQ_TYPE_OFFLOAD;
  76 }
  77
  78 /* Report whether this TX queue would be empty for the given write_count.
  79  * May return false negative.
  80  */
  81 static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue,
  82                                          unsigned int write_count)
  83 {
  84         unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count);
  85
  86         if (empty_read_count == 0)
  87                 return false;
  88
  89         return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
  90 }
  91
  92 /* Report whether the NIC considers this TX queue empty, using
  93  * packet_write_count (the write count recorded for the last completable
  94  * doorbell push).  May return false negative.  EF10 only, which is OK
  95  * because only EF10 supports PIO.
  96  */
  97 static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue)
  98 {
  99         EFX_WARN_ON_ONCE_PARANOID(!tx_queue->efx->type->option_descriptors);
 100         return __efx_nic_tx_is_empty(tx_queue, tx_queue->packet_write_count);
 101 }
 102
 103 /* Decide whether we can use TX PIO, ie. write packet data directly into
 104  * a buffer on the device.  This can reduce latency at the expense of
 105  * throughput, so we only do this if both hardware and software TX rings
 106  * are empty.  This also ensures that only one packet at a time can be
 107  * using the PIO buffer.
 108  */
 109 static inline bool efx_nic_may_tx_pio(struct efx_tx_queue *tx_queue)
 110 {
 111         struct efx_tx_queue *partner = efx_tx_queue_partner(tx_queue);
 112
 113         return tx_queue->piobuf && efx_nic_tx_is_empty(tx_queue) &&
 114                efx_nic_tx_is_empty(partner);
 115 }
 116
 117 /* Decide whether to push a TX descriptor to the NIC vs merely writing
 118  * the doorbell.  This can reduce latency when we are adding a single
 119  * descriptor to an empty queue, but is otherwise pointless.  Further,
 120  * Falcon and Siena have hardware bugs (SF bug 33851) that may be
 121  * triggered if we don't check this.
 122  * We use the write_count used for the last doorbell push, to get the
 123  * NIC's view of the tx queue.
 124  */
 125 static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
 126                                             unsigned int write_count)
 127 {
 128         bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count);
 129
 130         tx_queue->empty_read_count = 0;
 131         return was_empty && tx_queue->write_count - write_count == 1;
 132 }
 133
 134 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
 135 static inline efx_qword_t *
 136 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
 137 {
 138         return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
 139 }
 140
 141 enum {
 142         PHY_TYPE_NONE = 0,
 143         PHY_TYPE_TXC43128 = 1,
 144         PHY_TYPE_88E1111 = 2,
 145         PHY_TYPE_SFX7101 = 3,
 146         PHY_TYPE_QT2022C2 = 4,
 147         PHY_TYPE_PM8358 = 6,
 148         PHY_TYPE_SFT9001A = 8,
 149         PHY_TYPE_QT2025C = 9,
 150         PHY_TYPE_SFT9001B = 10,
 151 };
 152
 153 /* Alignment of PCIe DMA boundaries (4KB) */
 154 #define EFX_PAGE_SIZE   4096
 155 /* Size and alignment of buffer table entries (same) */
 156 #define EFX_BUF_SIZE    EFX_PAGE_SIZE
 157
 158 /* NIC-generic software stats */
 159 enum {
 160         GENERIC_STAT_rx_noskb_drops,
 161         GENERIC_STAT_rx_nodesc_trunc,
 162         GENERIC_STAT_COUNT
 163 };
 164
 165 enum {
 166         SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT,
 167         SIENA_STAT_tx_good_bytes,
 168         SIENA_STAT_tx_bad_bytes,
 169         SIENA_STAT_tx_packets,
 170         SIENA_STAT_tx_bad,
 171         SIENA_STAT_tx_pause,
 172         SIENA_STAT_tx_control,
 173         SIENA_STAT_tx_unicast,
 174         SIENA_STAT_tx_multicast,
 175         SIENA_STAT_tx_broadcast,
 176         SIENA_STAT_tx_lt64,
 177         SIENA_STAT_tx_64,
 178         SIENA_STAT_tx_65_to_127,
 179         SIENA_STAT_tx_128_to_255,
 180         SIENA_STAT_tx_256_to_511,
 181         SIENA_STAT_tx_512_to_1023,
 182         SIENA_STAT_tx_1024_to_15xx,
 183         SIENA_STAT_tx_15xx_to_jumbo,
 184         SIENA_STAT_tx_gtjumbo,
 185         SIENA_STAT_tx_collision,
 186         SIENA_STAT_tx_single_collision,
 187         SIENA_STAT_tx_multiple_collision,
 188         SIENA_STAT_tx_excessive_collision,
 189         SIENA_STAT_tx_deferred,
 190         SIENA_STAT_tx_late_collision,
 191         SIENA_STAT_tx_excessive_deferred,
 192         SIENA_STAT_tx_non_tcpudp,
 193         SIENA_STAT_tx_mac_src_error,
 194         SIENA_STAT_tx_ip_src_error,
 195         SIENA_STAT_rx_bytes,
 196         SIENA_STAT_rx_good_bytes,
 197         SIENA_STAT_rx_bad_bytes,
 198         SIENA_STAT_rx_packets,
 199         SIENA_STAT_rx_good,
 200         SIENA_STAT_rx_bad,
 201         SIENA_STAT_rx_pause,
 202         SIENA_STAT_rx_control,
 203         SIENA_STAT_rx_unicast,
 204         SIENA_STAT_rx_multicast,
 205         SIENA_STAT_rx_broadcast,
 206         SIENA_STAT_rx_lt64,
 207         SIENA_STAT_rx_64,
 208         SIENA_STAT_rx_65_to_127,
 209         SIENA_STAT_rx_128_to_255,
 210         SIENA_STAT_rx_256_to_511,
 211         SIENA_STAT_rx_512_to_1023,
 212         SIENA_STAT_rx_1024_to_15xx,
 213         SIENA_STAT_rx_15xx_to_jumbo,
 214         SIENA_STAT_rx_gtjumbo,
 215         SIENA_STAT_rx_bad_gtjumbo,
 216         SIENA_STAT_rx_overflow,
 217         SIENA_STAT_rx_false_carrier,
 218         SIENA_STAT_rx_symbol_error,
 219         SIENA_STAT_rx_align_error,
 220         SIENA_STAT_rx_length_error,
 221         SIENA_STAT_rx_internal_error,
 222         SIENA_STAT_rx_nodesc_drop_cnt,
 223         SIENA_STAT_COUNT
 224 };
 225
 226 /**
 227  * struct siena_nic_data - Siena NIC state
 228  * @efx: Pointer back to main interface structure
 229  * @wol_filter_id: Wake-on-LAN packet filter id
 230  * @stats: Hardware statistics
 231  * @vf: Array of &struct siena_vf objects
 232  * @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
 233  * @vfdi_status: Common VFDI status page to be dmad to VF address space.
 234  * @local_addr_list: List of local addresses. Protected by %local_lock.
 235  * @local_page_list: List of DMA addressable pages used to broadcast
 236  *      %local_addr_list. Protected by %local_lock.
 237  * @local_lock: Mutex protecting %local_addr_list and %local_page_list.
 238  * @peer_work: Work item to broadcast peer addresses to VMs.
 239  */
 240 struct siena_nic_data {
 241         struct efx_nic *efx;
 242         int wol_filter_id;
 243         u64 stats[SIENA_STAT_COUNT];
 244 #ifdef CONFIG_SFC_SRIOV
 245         struct siena_vf *vf;
 246         struct efx_channel *vfdi_channel;
 247         unsigned vf_buftbl_base;
 248         struct efx_buffer vfdi_status;
 249         struct list_head local_addr_list;
 250         struct list_head local_page_list;
 251         struct mutex local_lock;
 252         struct work_struct peer_work;
 253 #endif
 254 };
 255
 256 enum {
 257         EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT,
 258         EF10_STAT_port_tx_packets,
 259         EF10_STAT_port_tx_pause,
 260         EF10_STAT_port_tx_control,
 261         EF10_STAT_port_tx_unicast,
 262         EF10_STAT_port_tx_multicast,
 263         EF10_STAT_port_tx_broadcast,
 264         EF10_STAT_port_tx_lt64,
 265         EF10_STAT_port_tx_64,
 266         EF10_STAT_port_tx_65_to_127,
 267         EF10_STAT_port_tx_128_to_255,
 268         EF10_STAT_port_tx_256_to_511,
 269         EF10_STAT_port_tx_512_to_1023,
 270         EF10_STAT_port_tx_1024_to_15xx,
 271         EF10_STAT_port_tx_15xx_to_jumbo,
 272         EF10_STAT_port_rx_bytes,
 273         EF10_STAT_port_rx_bytes_minus_good_bytes,
 274         EF10_STAT_port_rx_good_bytes,
 275         EF10_STAT_port_rx_bad_bytes,
 276         EF10_STAT_port_rx_packets,
 277         EF10_STAT_port_rx_good,
 278         EF10_STAT_port_rx_bad,
 279         EF10_STAT_port_rx_pause,
 280         EF10_STAT_port_rx_control,
 281         EF10_STAT_port_rx_unicast,
 282         EF10_STAT_port_rx_multicast,
 283         EF10_STAT_port_rx_broadcast,
 284         EF10_STAT_port_rx_lt64,
 285         EF10_STAT_port_rx_64,
 286         EF10_STAT_port_rx_65_to_127,
 287         EF10_STAT_port_rx_128_to_255,
 288         EF10_STAT_port_rx_256_to_511,
 289         EF10_STAT_port_rx_512_to_1023,
 290         EF10_STAT_port_rx_1024_to_15xx,
 291         EF10_STAT_port_rx_15xx_to_jumbo,
 292         EF10_STAT_port_rx_gtjumbo,
 293         EF10_STAT_port_rx_bad_gtjumbo,
 294         EF10_STAT_port_rx_overflow,
 295         EF10_STAT_port_rx_align_error,
 296         EF10_STAT_port_rx_length_error,
 297         EF10_STAT_port_rx_nodesc_drops,
 298         EF10_STAT_port_rx_pm_trunc_bb_overflow,
 299         EF10_STAT_port_rx_pm_discard_bb_overflow,
 300         EF10_STAT_port_rx_pm_trunc_vfifo_full,
 301         EF10_STAT_port_rx_pm_discard_vfifo_full,
 302         EF10_STAT_port_rx_pm_trunc_qbb,
 303         EF10_STAT_port_rx_pm_discard_qbb,
 304         EF10_STAT_port_rx_pm_discard_mapping,
 305         EF10_STAT_port_rx_dp_q_disabled_packets,
 306         EF10_STAT_port_rx_dp_di_dropped_packets,
 307         EF10_STAT_port_rx_dp_streaming_packets,
 308         EF10_STAT_port_rx_dp_hlb_fetch,
 309         EF10_STAT_port_rx_dp_hlb_wait,
 310         EF10_STAT_rx_unicast,
 311         EF10_STAT_rx_unicast_bytes,
 312         EF10_STAT_rx_multicast,
 313         EF10_STAT_rx_multicast_bytes,
 314         EF10_STAT_rx_broadcast,
 315         EF10_STAT_rx_broadcast_bytes,
 316         EF10_STAT_rx_bad,
 317         EF10_STAT_rx_bad_bytes,
 318         EF10_STAT_rx_overflow,
 319         EF10_STAT_tx_unicast,
 320         EF10_STAT_tx_unicast_bytes,
 321         EF10_STAT_tx_multicast,
 322         EF10_STAT_tx_multicast_bytes,
 323         EF10_STAT_tx_broadcast,
 324         EF10_STAT_tx_broadcast_bytes,
 325         EF10_STAT_tx_bad,
 326         EF10_STAT_tx_bad_bytes,
 327         EF10_STAT_tx_overflow,
 328         EF10_STAT_V1_COUNT,
 329         EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT,
 330         EF10_STAT_fec_corrected_errors,
 331         EF10_STAT_fec_corrected_symbols_lane0,
 332         EF10_STAT_fec_corrected_symbols_lane1,
 333         EF10_STAT_fec_corrected_symbols_lane2,
 334         EF10_STAT_fec_corrected_symbols_lane3,
 335         EF10_STAT_ctpio_dmabuf_start,
 336         EF10_STAT_ctpio_vi_busy_fallback,
 337         EF10_STAT_ctpio_long_write_success,
 338         EF10_STAT_ctpio_missing_dbell_fail,
 339         EF10_STAT_ctpio_overflow_fail,
 340         EF10_STAT_ctpio_underflow_fail,
 341         EF10_STAT_ctpio_timeout_fail,
 342         EF10_STAT_ctpio_noncontig_wr_fail,
 343         EF10_STAT_ctpio_frm_clobber_fail,
 344         EF10_STAT_ctpio_invalid_wr_fail,
 345         EF10_STAT_ctpio_vi_clobber_fallback,
 346         EF10_STAT_ctpio_unqualified_fallback,
 347         EF10_STAT_ctpio_runt_fallback,
 348         EF10_STAT_ctpio_success,
 349         EF10_STAT_ctpio_fallback,
 350         EF10_STAT_ctpio_poison,
 351         EF10_STAT_ctpio_erase,
 352         EF10_STAT_COUNT
 353 };
 354
 355 /* Maximum number of TX PIO buffers we may allocate to a function.
 356  * This matches the total number of buffers on each SFC9100-family
 357  * controller.
 358  */
 359 #define EF10_TX_PIOBUF_COUNT 16
 360
 361 /**
 362  * struct efx_ef10_nic_data - EF10 architecture NIC state
 363  * @mcdi_buf: DMA buffer for MCDI
 364  * @warm_boot_count: Last seen MC warm boot count
 365  * @vi_base: Absolute index of first VI in this function
 366  * @n_allocated_vis: Number of VIs allocated to this function
 367  * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
 368  * @must_restore_filters: Flag: filters have yet to be restored after MC reboot
 369  * @n_piobufs: Number of PIO buffers allocated to this function
 370  * @wc_membase: Base address of write-combining mapping of the memory BAR
 371  * @pio_write_base: Base address for writing PIO buffers
 372  * @pio_write_vi_base: Relative VI number for @pio_write_base
 373  * @piobuf_handle: Handle of each PIO buffer allocated
 374  * @piobuf_size: size of a single PIO buffer
 375  * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
 376  *      reboot
 377  * @rx_rss_context: Firmware handle for our RSS context
 378  * @rx_rss_context_exclusive: Whether our RSS context is exclusive or shared
 379  * @stats: Hardware statistics
 380  * @workaround_35388: Flag: firmware supports workaround for bug 35388
 381  * @workaround_26807: Flag: firmware supports workaround for bug 26807
 382  * @workaround_61265: Flag: firmware supports workaround for bug 61265
 383  * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
 384  *      after MC reboot
 385  * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
 386  *      %MC_CMD_GET_CAPABILITIES response)
 387  * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of
 388  * %MC_CMD_GET_CAPABILITIES response)
 389  * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU
 390  * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU
 391  * @vport_id: The function's vport ID, only relevant for PFs
 392  * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot
 393  * @pf_index: The number for this PF, or the parent PF if this is a VF
 394 #ifdef CONFIG_SFC_SRIOV
 395  * @vf: Pointer to VF data structure
 396 #endif
 397  * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero
 398  * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock.
 399  * @vlan_lock: Lock to serialize access to vlan_list.
 400  * @udp_tunnels: UDP tunnel port numbers and types.
 401  * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing
 402  *      @udp_tunnels to hardware and thus the push must be re-done.
 403  * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty.
 404  */
 405 struct efx_ef10_nic_data {
 406         struct efx_buffer mcdi_buf;
 407         u16 warm_boot_count;
 408         unsigned int vi_base;
 409         unsigned int n_allocated_vis;
 410         bool must_realloc_vis;
 411         bool must_restore_filters;
 412         unsigned int n_piobufs;
 413         void __iomem *wc_membase, *pio_write_base;
 414         unsigned int pio_write_vi_base;
 415         unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
 416         u16 piobuf_size;
 417         bool must_restore_piobufs;
 418         u32 rx_rss_context;
 419         bool rx_rss_context_exclusive;
 420         u64 stats[EF10_STAT_COUNT];
 421         bool workaround_35388;
 422         bool workaround_26807;
 423         bool workaround_61265;
 424         bool must_check_datapath_caps;
 425         u32 datapath_caps;
 426         u32 datapath_caps2;
 427         unsigned int rx_dpcpu_fw_id;
 428         unsigned int tx_dpcpu_fw_id;
 429         unsigned int vport_id;
 430         bool must_probe_vswitching;
 431         unsigned int pf_index;
 432         u8 port_id[ETH_ALEN];
 433 #ifdef CONFIG_SFC_SRIOV
 434         unsigned int vf_index;
 435         struct ef10_vf *vf;
 436 #endif
 437         u8 vport_mac[ETH_ALEN];
 438         struct list_head vlan_list;
 439         struct mutex vlan_lock;
 440         struct efx_udp_tunnel udp_tunnels[16];
 441         bool udp_tunnels_dirty;
 442         struct mutex udp_tunnels_lock;
 443         u64 licensed_features;
 444 };
 445
 446 int efx_init_sriov(void);
 447 void efx_fini_sriov(void);
 448
 449 struct ethtool_ts_info;
 450 int efx_ptp_probe(struct efx_nic *efx, struct efx_channel *channel);
 451 void efx_ptp_defer_probe_with_channel(struct efx_nic *efx);
 452 struct efx_channel *efx_ptp_channel(struct efx_nic *efx);
 453 void efx_ptp_remove(struct efx_nic *efx);
 454 int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr);
 455 int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr);
 456 void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info);
 457 bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
 458 int efx_ptp_get_mode(struct efx_nic *efx);
 459 int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted,
 460                         unsigned int new_mode);
 461 int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
 462 void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev);
 463 size_t efx_ptp_describe_stats(struct efx_nic *efx, u8 *strings);
 464 size_t efx_ptp_update_stats(struct efx_nic *efx, u64 *stats);
 465 void efx_time_sync_event(struct efx_channel *channel, efx_qword_t *ev);
 466 void __efx_rx_skb_attach_timestamp(struct efx_channel *channel,
 467                                    struct sk_buff *skb);
 468 static inline void efx_rx_skb_attach_timestamp(struct efx_channel *channel,
 469                                                struct sk_buff *skb)
 470 {
 471         if (channel->sync_events_state == SYNC_EVENTS_VALID)
 472                 __efx_rx_skb_attach_timestamp(channel, skb);
 473 }
 474 void efx_ptp_start_datapath(struct efx_nic *efx);
 475 void efx_ptp_stop_datapath(struct efx_nic *efx);
 476 bool efx_ptp_use_mac_tx_timestamps(struct efx_nic *efx);
 477 ktime_t efx_ptp_nic_to_kernel_time(struct efx_tx_queue *tx_queue);
 478
 479 extern const struct efx_nic_type falcon_a1_nic_type;
 480 extern const struct efx_nic_type falcon_b0_nic_type;
 481 extern const struct efx_nic_type siena_a0_nic_type;
 482 extern const struct efx_nic_type efx_hunt_a0_nic_type;
 483 extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
 484
 485 /**************************************************************************
 486  *
 487  * Externs
 488  *
 489  **************************************************************************
 490  */
 491
 492 int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
 493
 494 /* TX data path */
 495 static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
 496 {
 497         return tx_queue->efx->type->tx_probe(tx_queue);
 498 }
 499 static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
 500 {
 501         tx_queue->efx->type->tx_init(tx_queue);
 502 }
 503 static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
 504 {
 505         tx_queue->efx->type->tx_remove(tx_queue);
 506 }
 507 static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
 508 {
 509         tx_queue->efx->type->tx_write(tx_queue);
 510 }
 511
 512 /* RX data path */
 513 static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
 514 {
 515         return rx_queue->efx->type->rx_probe(rx_queue);
 516 }
 517 static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
 518 {
 519         rx_queue->efx->type->rx_init(rx_queue);
 520 }
 521 static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
 522 {
 523         rx_queue->efx->type->rx_remove(rx_queue);
 524 }
 525 static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
 526 {
 527         rx_queue->efx->type->rx_write(rx_queue);
 528 }
 529 static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
 530 {
 531         rx_queue->efx->type->rx_defer_refill(rx_queue);
 532 }
 533
 534 /* Event data path */
 535 static inline int efx_nic_probe_eventq(struct efx_channel *channel)
 536 {
 537         return channel->efx->type->ev_probe(channel);
 538 }
 539 static inline int efx_nic_init_eventq(struct efx_channel *channel)
 540 {
 541         return channel->efx->type->ev_init(channel);
 542 }
 543 static inline void efx_nic_fini_eventq(struct efx_channel *channel)
 544 {
 545         channel->efx->type->ev_fini(channel);
 546 }
 547 static inline void efx_nic_remove_eventq(struct efx_channel *channel)
 548 {
 549         channel->efx->type->ev_remove(channel);
 550 }
 551 static inline int
 552 efx_nic_process_eventq(struct efx_channel *channel, int quota)
 553 {
 554         return channel->efx->type->ev_process(channel, quota);
 555 }
 556 static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
 557 {
 558         channel->efx->type->ev_read_ack(channel);
 559 }
 560 void efx_nic_event_test_start(struct efx_channel *channel);
 561
 562 /* Falcon/Siena queue operations */
 563 int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
 564 void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
 565 void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
 566 void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
 567 void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
 568 unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,
 569                                     dma_addr_t dma_addr, unsigned int len);
 570 int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
 571 void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
 572 void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
 573 void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
 574 void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
 575 void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
 576 int efx_farch_ev_probe(struct efx_channel *channel);
 577 int efx_farch_ev_init(struct efx_channel *channel);
 578 void efx_farch_ev_fini(struct efx_channel *channel);
 579 void efx_farch_ev_remove(struct efx_channel *channel);
 580 int efx_farch_ev_process(struct efx_channel *channel, int quota);
 581 void efx_farch_ev_read_ack(struct efx_channel *channel);
 582 void efx_farch_ev_test_generate(struct efx_channel *channel);
 583
 584 /* Falcon/Siena filter operations */
 585 int efx_farch_filter_table_probe(struct efx_nic *efx);
 586 void efx_farch_filter_table_restore(struct efx_nic *efx);
 587 void efx_farch_filter_table_remove(struct efx_nic *efx);
 588 void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
 589 s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,
 590                             bool replace);
 591 int efx_farch_filter_remove_safe(struct efx_nic *efx,
 592                                  enum efx_filter_priority priority,
 593                                  u32 filter_id);
 594 int efx_farch_filter_get_safe(struct efx_nic *efx,
 595                               enum efx_filter_priority priority, u32 filter_id,
 596                               struct efx_filter_spec *);
 597 int efx_farch_filter_clear_rx(struct efx_nic *efx,
 598                               enum efx_filter_priority priority);
 599 u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
 600                                    enum efx_filter_priority priority);
 601 u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
 602 s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
 603                                 enum efx_filter_priority priority, u32 *buf,
 604                                 u32 size);
 605 #ifdef CONFIG_RFS_ACCEL
 606 s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
 607                                 struct efx_filter_spec *spec);
 608 bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
 609                                      unsigned int index);
 610 #endif
 611 void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
 612
 613 bool efx_nic_event_present(struct efx_channel *channel);
 614
 615 /* Some statistics are computed as A - B where A and B each increase
 616  * linearly with some hardware counter(s) and the counters are read
 617  * asynchronously.  If the counters contributing to B are always read
 618  * after those contributing to A, the computed value may be lower than
 619  * the true value by some variable amount, and may decrease between
 620  * subsequent computations.
 621  *
 622  * We should never allow statistics to decrease or to exceed the true
 623  * value.  Since the computed value will never be greater than the
 624  * true value, we can achieve this by only storing the computed value
 625  * when it increases.
 626  */
 627 static inline void efx_update_diff_stat(u64 *stat, u64 diff)
 628 {
 629         if ((s64)(diff - *stat) > 0)
 630                 *stat = diff;
 631 }
 632
 633 /* Interrupts */
 634 int efx_nic_init_interrupt(struct efx_nic *efx);
 635 int efx_nic_irq_test_start(struct efx_nic *efx);
 636 void efx_nic_fini_interrupt(struct efx_nic *efx);
 637
 638 /* Falcon/Siena interrupts */
 639 void efx_farch_irq_enable_master(struct efx_nic *efx);
 640 int efx_farch_irq_test_generate(struct efx_nic *efx);
 641 void efx_farch_irq_disable_master(struct efx_nic *efx);
 642 irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
 643 irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
 644 irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
 645
 646 static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
 647 {
 648         return READ_ONCE(channel->event_test_cpu);
 649 }
 650 static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
 651 {
 652         return READ_ONCE(efx->last_irq_cpu);
 653 }
 654
 655 /* Global Resources */
 656 int efx_nic_flush_queues(struct efx_nic *efx);
 657 void siena_prepare_flush(struct efx_nic *efx);
 658 int efx_farch_fini_dmaq(struct efx_nic *efx);
 659 void efx_farch_finish_flr(struct efx_nic *efx);
 660 void siena_finish_flush(struct efx_nic *efx);
 661 void falcon_start_nic_stats(struct efx_nic *efx);
 662 void falcon_stop_nic_stats(struct efx_nic *efx);
 663 int falcon_reset_xaui(struct efx_nic *efx);
 664 void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
 665 void efx_farch_init_common(struct efx_nic *efx);
 666 void efx_ef10_handle_drain_event(struct efx_nic *efx);
 667 void efx_farch_rx_push_indir_table(struct efx_nic *efx);
 668 void efx_farch_rx_pull_indir_table(struct efx_nic *efx);
 669
 670 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
 671                          unsigned int len, gfp_t gfp_flags);
 672 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
 673
 674 /* Tests */
 675 struct efx_farch_register_test {
 676         unsigned address;
 677         efx_oword_t mask;
 678 };
 679 int efx_farch_test_registers(struct efx_nic *efx,
 680                              const struct efx_farch_register_test *regs,
 681                              size_t n_regs);
 682
 683 size_t efx_nic_get_regs_len(struct efx_nic *efx);
 684 void efx_nic_get_regs(struct efx_nic *efx, void *buf);
 685
 686 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
 687                               const unsigned long *mask, u8 *names);
 688 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
 689                           const unsigned long *mask, u64 *stats,
 690                           const void *dma_buf, bool accumulate);
 691 void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat);
 692
 693 #define EFX_MAX_FLUSH_TIME 5000
 694
 695 void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
 696                               efx_qword_t *event);
 697
 698 #endif /* EFX_NIC_H */