1 // SPDX-License-Identifier: GPL-2.0
2 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
3 * sungem.c: Sun GEM ethernet driver.
5 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
7 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
8 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
9 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
11 * NAPI and NETPOLL support
12 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/fcntl.h>
22 #include <linux/interrupt.h>
23 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/string.h>
27 #include <linux/delay.h>
28 #include <linux/errno.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/mii.h>
35 #include <linux/ethtool.h>
36 #include <linux/crc32.h>
37 #include <linux/random.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/bitops.h>
42 #include <linux/gfp.h>
45 #include <asm/byteorder.h>
46 #include <linux/uaccess.h>
50 #include <asm/idprom.h>
54 #ifdef CONFIG_PPC_PMAC
56 #include <asm/machdep.h>
57 #include <asm/pmac_feature.h>
60 #include <linux/sungem_phy.h>
63 /* Stripping FCS is causing problems, disabled for now */
66 #define DEFAULT_MSG (NETIF_MSG_DRV | \
70 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
71 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
72 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
73 SUPPORTED_Pause | SUPPORTED_Autoneg)
75 #define DRV_NAME "sungem"
76 #define DRV_VERSION "1.0"
77 #define DRV_AUTHOR "David S. Miller <davem@redhat.com>"
79 static char version
[] =
80 DRV_NAME
".c:v" DRV_VERSION
" " DRV_AUTHOR
"\n";
82 MODULE_AUTHOR(DRV_AUTHOR
);
83 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
84 MODULE_LICENSE("GPL");
86 #define GEM_MODULE_NAME "gem"
88 static const struct pci_device_id gem_pci_tbl
[] = {
89 { PCI_VENDOR_ID_SUN
, PCI_DEVICE_ID_SUN_GEM
,
90 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
92 /* These models only differ from the original GEM in
93 * that their tx/rx fifos are of a different size and
94 * they only support 10/100 speeds. -DaveM
96 * Apple's GMAC does support gigabit on machines with
97 * the BCM54xx PHYs. -BenH
99 { PCI_VENDOR_ID_SUN
, PCI_DEVICE_ID_SUN_RIO_GEM
,
100 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
101 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_GMAC
,
102 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
103 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_GMACP
,
104 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
105 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2
,
106 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
107 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_K2_GMAC
,
108 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
109 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_SH_SUNGEM
,
110 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
111 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_IPID2_GMAC
,
112 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
116 MODULE_DEVICE_TABLE(pci
, gem_pci_tbl
);
118 static u16
__sungem_phy_read(struct gem
*gp
, int phy_addr
, int reg
)
125 cmd
|= (phy_addr
<< 23) & MIF_FRAME_PHYAD
;
126 cmd
|= (reg
<< 18) & MIF_FRAME_REGAD
;
127 cmd
|= (MIF_FRAME_TAMSB
);
128 writel(cmd
, gp
->regs
+ MIF_FRAME
);
131 cmd
= readl(gp
->regs
+ MIF_FRAME
);
132 if (cmd
& MIF_FRAME_TALSB
)
141 return cmd
& MIF_FRAME_DATA
;
144 static inline int _sungem_phy_read(struct net_device
*dev
, int mii_id
, int reg
)
146 struct gem
*gp
= netdev_priv(dev
);
147 return __sungem_phy_read(gp
, mii_id
, reg
);
150 static inline u16
sungem_phy_read(struct gem
*gp
, int reg
)
152 return __sungem_phy_read(gp
, gp
->mii_phy_addr
, reg
);
155 static void __sungem_phy_write(struct gem
*gp
, int phy_addr
, int reg
, u16 val
)
162 cmd
|= (phy_addr
<< 23) & MIF_FRAME_PHYAD
;
163 cmd
|= (reg
<< 18) & MIF_FRAME_REGAD
;
164 cmd
|= (MIF_FRAME_TAMSB
);
165 cmd
|= (val
& MIF_FRAME_DATA
);
166 writel(cmd
, gp
->regs
+ MIF_FRAME
);
169 cmd
= readl(gp
->regs
+ MIF_FRAME
);
170 if (cmd
& MIF_FRAME_TALSB
)
177 static inline void _sungem_phy_write(struct net_device
*dev
, int mii_id
, int reg
, int val
)
179 struct gem
*gp
= netdev_priv(dev
);
180 __sungem_phy_write(gp
, mii_id
, reg
, val
& 0xffff);
183 static inline void sungem_phy_write(struct gem
*gp
, int reg
, u16 val
)
185 __sungem_phy_write(gp
, gp
->mii_phy_addr
, reg
, val
);
188 static inline void gem_enable_ints(struct gem
*gp
)
190 /* Enable all interrupts but TXDONE */
191 writel(GREG_STAT_TXDONE
, gp
->regs
+ GREG_IMASK
);
194 static inline void gem_disable_ints(struct gem
*gp
)
196 /* Disable all interrupts, including TXDONE */
197 writel(GREG_STAT_NAPI
| GREG_STAT_TXDONE
, gp
->regs
+ GREG_IMASK
);
198 (void)readl(gp
->regs
+ GREG_IMASK
); /* write posting */
201 static void gem_get_cell(struct gem
*gp
)
203 BUG_ON(gp
->cell_enabled
< 0);
205 #ifdef CONFIG_PPC_PMAC
206 if (gp
->cell_enabled
== 1) {
208 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, gp
->of_node
, 0, 1);
211 #endif /* CONFIG_PPC_PMAC */
214 /* Turn off the chip's clock */
215 static void gem_put_cell(struct gem
*gp
)
217 BUG_ON(gp
->cell_enabled
<= 0);
219 #ifdef CONFIG_PPC_PMAC
220 if (gp
->cell_enabled
== 0) {
222 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, gp
->of_node
, 0, 0);
225 #endif /* CONFIG_PPC_PMAC */
228 static inline void gem_netif_stop(struct gem
*gp
)
230 netif_trans_update(gp
->dev
); /* prevent tx timeout */
231 napi_disable(&gp
->napi
);
232 netif_tx_disable(gp
->dev
);
235 static inline void gem_netif_start(struct gem
*gp
)
237 /* NOTE: unconditional netif_wake_queue is only
238 * appropriate so long as all callers are assured to
239 * have free tx slots.
241 netif_wake_queue(gp
->dev
);
242 napi_enable(&gp
->napi
);
245 static void gem_schedule_reset(struct gem
*gp
)
247 gp
->reset_task_pending
= 1;
248 schedule_work(&gp
->reset_task
);
251 static void gem_handle_mif_event(struct gem
*gp
, u32 reg_val
, u32 changed_bits
)
253 if (netif_msg_intr(gp
))
254 printk(KERN_DEBUG
"%s: mif interrupt\n", gp
->dev
->name
);
257 static int gem_pcs_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
259 u32 pcs_istat
= readl(gp
->regs
+ PCS_ISTAT
);
262 if (netif_msg_intr(gp
))
263 printk(KERN_DEBUG
"%s: pcs interrupt, pcs_istat: 0x%x\n",
264 gp
->dev
->name
, pcs_istat
);
266 if (!(pcs_istat
& PCS_ISTAT_LSC
)) {
267 netdev_err(dev
, "PCS irq but no link status change???\n");
271 /* The link status bit latches on zero, so you must
272 * read it twice in such a case to see a transition
273 * to the link being up.
275 pcs_miistat
= readl(gp
->regs
+ PCS_MIISTAT
);
276 if (!(pcs_miistat
& PCS_MIISTAT_LS
))
278 (readl(gp
->regs
+ PCS_MIISTAT
) &
281 if (pcs_miistat
& PCS_MIISTAT_ANC
) {
282 /* The remote-fault indication is only valid
283 * when autoneg has completed.
285 if (pcs_miistat
& PCS_MIISTAT_RF
)
286 netdev_info(dev
, "PCS AutoNEG complete, RemoteFault\n");
288 netdev_info(dev
, "PCS AutoNEG complete\n");
291 if (pcs_miistat
& PCS_MIISTAT_LS
) {
292 netdev_info(dev
, "PCS link is now up\n");
293 netif_carrier_on(gp
->dev
);
295 netdev_info(dev
, "PCS link is now down\n");
296 netif_carrier_off(gp
->dev
);
297 /* If this happens and the link timer is not running,
298 * reset so we re-negotiate.
300 if (!timer_pending(&gp
->link_timer
))
307 static int gem_txmac_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
309 u32 txmac_stat
= readl(gp
->regs
+ MAC_TXSTAT
);
311 if (netif_msg_intr(gp
))
312 printk(KERN_DEBUG
"%s: txmac interrupt, txmac_stat: 0x%x\n",
313 gp
->dev
->name
, txmac_stat
);
315 /* Defer timer expiration is quite normal,
316 * don't even log the event.
318 if ((txmac_stat
& MAC_TXSTAT_DTE
) &&
319 !(txmac_stat
& ~MAC_TXSTAT_DTE
))
322 if (txmac_stat
& MAC_TXSTAT_URUN
) {
323 netdev_err(dev
, "TX MAC xmit underrun\n");
324 dev
->stats
.tx_fifo_errors
++;
327 if (txmac_stat
& MAC_TXSTAT_MPE
) {
328 netdev_err(dev
, "TX MAC max packet size error\n");
329 dev
->stats
.tx_errors
++;
332 /* The rest are all cases of one of the 16-bit TX
335 if (txmac_stat
& MAC_TXSTAT_NCE
)
336 dev
->stats
.collisions
+= 0x10000;
338 if (txmac_stat
& MAC_TXSTAT_ECE
) {
339 dev
->stats
.tx_aborted_errors
+= 0x10000;
340 dev
->stats
.collisions
+= 0x10000;
343 if (txmac_stat
& MAC_TXSTAT_LCE
) {
344 dev
->stats
.tx_aborted_errors
+= 0x10000;
345 dev
->stats
.collisions
+= 0x10000;
348 /* We do not keep track of MAC_TXSTAT_FCE and
349 * MAC_TXSTAT_PCE events.
354 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
355 * so we do the following.
357 * If any part of the reset goes wrong, we return 1 and that causes the
358 * whole chip to be reset.
360 static int gem_rxmac_reset(struct gem
*gp
)
362 struct net_device
*dev
= gp
->dev
;
367 /* First, reset & disable MAC RX. */
368 writel(MAC_RXRST_CMD
, gp
->regs
+ MAC_RXRST
);
369 for (limit
= 0; limit
< 5000; limit
++) {
370 if (!(readl(gp
->regs
+ MAC_RXRST
) & MAC_RXRST_CMD
))
375 netdev_err(dev
, "RX MAC will not reset, resetting whole chip\n");
379 writel(gp
->mac_rx_cfg
& ~MAC_RXCFG_ENAB
,
380 gp
->regs
+ MAC_RXCFG
);
381 for (limit
= 0; limit
< 5000; limit
++) {
382 if (!(readl(gp
->regs
+ MAC_RXCFG
) & MAC_RXCFG_ENAB
))
387 netdev_err(dev
, "RX MAC will not disable, resetting whole chip\n");
391 /* Second, disable RX DMA. */
392 writel(0, gp
->regs
+ RXDMA_CFG
);
393 for (limit
= 0; limit
< 5000; limit
++) {
394 if (!(readl(gp
->regs
+ RXDMA_CFG
) & RXDMA_CFG_ENABLE
))
399 netdev_err(dev
, "RX DMA will not disable, resetting whole chip\n");
405 /* Execute RX reset command. */
406 writel(gp
->swrst_base
| GREG_SWRST_RXRST
,
407 gp
->regs
+ GREG_SWRST
);
408 for (limit
= 0; limit
< 5000; limit
++) {
409 if (!(readl(gp
->regs
+ GREG_SWRST
) & GREG_SWRST_RXRST
))
414 netdev_err(dev
, "RX reset command will not execute, resetting whole chip\n");
418 /* Refresh the RX ring. */
419 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
420 struct gem_rxd
*rxd
= &gp
->init_block
->rxd
[i
];
422 if (gp
->rx_skbs
[i
] == NULL
) {
423 netdev_err(dev
, "Parts of RX ring empty, resetting whole chip\n");
427 rxd
->status_word
= cpu_to_le64(RXDCTRL_FRESH(gp
));
429 gp
->rx_new
= gp
->rx_old
= 0;
431 /* Now we must reprogram the rest of RX unit. */
432 desc_dma
= (u64
) gp
->gblock_dvma
;
433 desc_dma
+= (INIT_BLOCK_TX_RING_SIZE
* sizeof(struct gem_txd
));
434 writel(desc_dma
>> 32, gp
->regs
+ RXDMA_DBHI
);
435 writel(desc_dma
& 0xffffffff, gp
->regs
+ RXDMA_DBLOW
);
436 writel(RX_RING_SIZE
- 4, gp
->regs
+ RXDMA_KICK
);
437 val
= (RXDMA_CFG_BASE
| (RX_OFFSET
<< 10) |
438 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128
);
439 writel(val
, gp
->regs
+ RXDMA_CFG
);
440 if (readl(gp
->regs
+ GREG_BIFCFG
) & GREG_BIFCFG_M66EN
)
441 writel(((5 & RXDMA_BLANK_IPKTS
) |
442 ((8 << 12) & RXDMA_BLANK_ITIME
)),
443 gp
->regs
+ RXDMA_BLANK
);
445 writel(((5 & RXDMA_BLANK_IPKTS
) |
446 ((4 << 12) & RXDMA_BLANK_ITIME
)),
447 gp
->regs
+ RXDMA_BLANK
);
448 val
= (((gp
->rx_pause_off
/ 64) << 0) & RXDMA_PTHRESH_OFF
);
449 val
|= (((gp
->rx_pause_on
/ 64) << 12) & RXDMA_PTHRESH_ON
);
450 writel(val
, gp
->regs
+ RXDMA_PTHRESH
);
451 val
= readl(gp
->regs
+ RXDMA_CFG
);
452 writel(val
| RXDMA_CFG_ENABLE
, gp
->regs
+ RXDMA_CFG
);
453 writel(MAC_RXSTAT_RCV
, gp
->regs
+ MAC_RXMASK
);
454 val
= readl(gp
->regs
+ MAC_RXCFG
);
455 writel(val
| MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
460 static int gem_rxmac_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
462 u32 rxmac_stat
= readl(gp
->regs
+ MAC_RXSTAT
);
465 if (netif_msg_intr(gp
))
466 printk(KERN_DEBUG
"%s: rxmac interrupt, rxmac_stat: 0x%x\n",
467 gp
->dev
->name
, rxmac_stat
);
469 if (rxmac_stat
& MAC_RXSTAT_OFLW
) {
470 u32 smac
= readl(gp
->regs
+ MAC_SMACHINE
);
472 netdev_err(dev
, "RX MAC fifo overflow smac[%08x]\n", smac
);
473 dev
->stats
.rx_over_errors
++;
474 dev
->stats
.rx_fifo_errors
++;
476 ret
= gem_rxmac_reset(gp
);
479 if (rxmac_stat
& MAC_RXSTAT_ACE
)
480 dev
->stats
.rx_frame_errors
+= 0x10000;
482 if (rxmac_stat
& MAC_RXSTAT_CCE
)
483 dev
->stats
.rx_crc_errors
+= 0x10000;
485 if (rxmac_stat
& MAC_RXSTAT_LCE
)
486 dev
->stats
.rx_length_errors
+= 0x10000;
488 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
494 static int gem_mac_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
496 u32 mac_cstat
= readl(gp
->regs
+ MAC_CSTAT
);
498 if (netif_msg_intr(gp
))
499 printk(KERN_DEBUG
"%s: mac interrupt, mac_cstat: 0x%x\n",
500 gp
->dev
->name
, mac_cstat
);
502 /* This interrupt is just for pause frame and pause
503 * tracking. It is useful for diagnostics and debug
504 * but probably by default we will mask these events.
506 if (mac_cstat
& MAC_CSTAT_PS
)
509 if (mac_cstat
& MAC_CSTAT_PRCV
)
510 gp
->pause_last_time_recvd
= (mac_cstat
>> 16);
515 static int gem_mif_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
517 u32 mif_status
= readl(gp
->regs
+ MIF_STATUS
);
518 u32 reg_val
, changed_bits
;
520 reg_val
= (mif_status
& MIF_STATUS_DATA
) >> 16;
521 changed_bits
= (mif_status
& MIF_STATUS_STAT
);
523 gem_handle_mif_event(gp
, reg_val
, changed_bits
);
528 static int gem_pci_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
530 u32 pci_estat
= readl(gp
->regs
+ GREG_PCIESTAT
);
532 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
533 gp
->pdev
->device
== PCI_DEVICE_ID_SUN_GEM
) {
534 netdev_err(dev
, "PCI error [%04x]", pci_estat
);
536 if (pci_estat
& GREG_PCIESTAT_BADACK
)
537 pr_cont(" <No ACK64# during ABS64 cycle>");
538 if (pci_estat
& GREG_PCIESTAT_DTRTO
)
539 pr_cont(" <Delayed transaction timeout>");
540 if (pci_estat
& GREG_PCIESTAT_OTHER
)
544 pci_estat
|= GREG_PCIESTAT_OTHER
;
545 netdev_err(dev
, "PCI error\n");
548 if (pci_estat
& GREG_PCIESTAT_OTHER
) {
551 /* Interrogate PCI config space for the
554 pci_read_config_word(gp
->pdev
, PCI_STATUS
,
556 netdev_err(dev
, "Read PCI cfg space status [%04x]\n",
558 if (pci_cfg_stat
& PCI_STATUS_PARITY
)
559 netdev_err(dev
, "PCI parity error detected\n");
560 if (pci_cfg_stat
& PCI_STATUS_SIG_TARGET_ABORT
)
561 netdev_err(dev
, "PCI target abort\n");
562 if (pci_cfg_stat
& PCI_STATUS_REC_TARGET_ABORT
)
563 netdev_err(dev
, "PCI master acks target abort\n");
564 if (pci_cfg_stat
& PCI_STATUS_REC_MASTER_ABORT
)
565 netdev_err(dev
, "PCI master abort\n");
566 if (pci_cfg_stat
& PCI_STATUS_SIG_SYSTEM_ERROR
)
567 netdev_err(dev
, "PCI system error SERR#\n");
568 if (pci_cfg_stat
& PCI_STATUS_DETECTED_PARITY
)
569 netdev_err(dev
, "PCI parity error\n");
571 /* Write the error bits back to clear them. */
572 pci_cfg_stat
&= (PCI_STATUS_PARITY
|
573 PCI_STATUS_SIG_TARGET_ABORT
|
574 PCI_STATUS_REC_TARGET_ABORT
|
575 PCI_STATUS_REC_MASTER_ABORT
|
576 PCI_STATUS_SIG_SYSTEM_ERROR
|
577 PCI_STATUS_DETECTED_PARITY
);
578 pci_write_config_word(gp
->pdev
,
579 PCI_STATUS
, pci_cfg_stat
);
582 /* For all PCI errors, we should reset the chip. */
586 /* All non-normal interrupt conditions get serviced here.
587 * Returns non-zero if we should just exit the interrupt
588 * handler right now (ie. if we reset the card which invalidates
589 * all of the other original irq status bits).
591 static int gem_abnormal_irq(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
593 if (gem_status
& GREG_STAT_RXNOBUF
) {
594 /* Frame arrived, no free RX buffers available. */
595 if (netif_msg_rx_err(gp
))
596 printk(KERN_DEBUG
"%s: no buffer for rx frame\n",
598 dev
->stats
.rx_dropped
++;
601 if (gem_status
& GREG_STAT_RXTAGERR
) {
602 /* corrupt RX tag framing */
603 if (netif_msg_rx_err(gp
))
604 printk(KERN_DEBUG
"%s: corrupt rx tag framing\n",
606 dev
->stats
.rx_errors
++;
611 if (gem_status
& GREG_STAT_PCS
) {
612 if (gem_pcs_interrupt(dev
, gp
, gem_status
))
616 if (gem_status
& GREG_STAT_TXMAC
) {
617 if (gem_txmac_interrupt(dev
, gp
, gem_status
))
621 if (gem_status
& GREG_STAT_RXMAC
) {
622 if (gem_rxmac_interrupt(dev
, gp
, gem_status
))
626 if (gem_status
& GREG_STAT_MAC
) {
627 if (gem_mac_interrupt(dev
, gp
, gem_status
))
631 if (gem_status
& GREG_STAT_MIF
) {
632 if (gem_mif_interrupt(dev
, gp
, gem_status
))
636 if (gem_status
& GREG_STAT_PCIERR
) {
637 if (gem_pci_interrupt(dev
, gp
, gem_status
))
644 static __inline__
void gem_tx(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
649 limit
= ((gem_status
& GREG_STAT_TXNR
) >> GREG_STAT_TXNR_SHIFT
);
650 while (entry
!= limit
) {
657 if (netif_msg_tx_done(gp
))
658 printk(KERN_DEBUG
"%s: tx done, slot %d\n",
659 gp
->dev
->name
, entry
);
660 skb
= gp
->tx_skbs
[entry
];
661 if (skb_shinfo(skb
)->nr_frags
) {
662 int last
= entry
+ skb_shinfo(skb
)->nr_frags
;
666 last
&= (TX_RING_SIZE
- 1);
668 walk
= NEXT_TX(walk
);
677 gp
->tx_skbs
[entry
] = NULL
;
678 dev
->stats
.tx_bytes
+= skb
->len
;
680 for (frag
= 0; frag
<= skb_shinfo(skb
)->nr_frags
; frag
++) {
681 txd
= &gp
->init_block
->txd
[entry
];
683 dma_addr
= le64_to_cpu(txd
->buffer
);
684 dma_len
= le64_to_cpu(txd
->control_word
) & TXDCTRL_BUFSZ
;
686 pci_unmap_page(gp
->pdev
, dma_addr
, dma_len
, PCI_DMA_TODEVICE
);
687 entry
= NEXT_TX(entry
);
690 dev
->stats
.tx_packets
++;
691 dev_consume_skb_any(skb
);
695 /* Need to make the tx_old update visible to gem_start_xmit()
696 * before checking for netif_queue_stopped(). Without the
697 * memory barrier, there is a small possibility that gem_start_xmit()
698 * will miss it and cause the queue to be stopped forever.
702 if (unlikely(netif_queue_stopped(dev
) &&
703 TX_BUFFS_AVAIL(gp
) > (MAX_SKB_FRAGS
+ 1))) {
704 struct netdev_queue
*txq
= netdev_get_tx_queue(dev
, 0);
706 __netif_tx_lock(txq
, smp_processor_id());
707 if (netif_queue_stopped(dev
) &&
708 TX_BUFFS_AVAIL(gp
) > (MAX_SKB_FRAGS
+ 1))
709 netif_wake_queue(dev
);
710 __netif_tx_unlock(txq
);
714 static __inline__
void gem_post_rxds(struct gem
*gp
, int limit
)
716 int cluster_start
, curr
, count
, kick
;
718 cluster_start
= curr
= (gp
->rx_new
& ~(4 - 1));
722 while (curr
!= limit
) {
723 curr
= NEXT_RX(curr
);
725 struct gem_rxd
*rxd
=
726 &gp
->init_block
->rxd
[cluster_start
];
728 rxd
->status_word
= cpu_to_le64(RXDCTRL_FRESH(gp
));
730 cluster_start
= NEXT_RX(cluster_start
);
731 if (cluster_start
== curr
)
740 writel(kick
, gp
->regs
+ RXDMA_KICK
);
744 #define ALIGNED_RX_SKB_ADDR(addr) \
745 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
746 static __inline__
struct sk_buff
*gem_alloc_skb(struct net_device
*dev
, int size
,
749 struct sk_buff
*skb
= alloc_skb(size
+ 64, gfp_flags
);
752 unsigned long offset
= ALIGNED_RX_SKB_ADDR(skb
->data
);
753 skb_reserve(skb
, offset
);
758 static int gem_rx(struct gem
*gp
, int work_to_do
)
760 struct net_device
*dev
= gp
->dev
;
761 int entry
, drops
, work_done
= 0;
765 if (netif_msg_rx_status(gp
))
766 printk(KERN_DEBUG
"%s: rx interrupt, done: %d, rx_new: %d\n",
767 gp
->dev
->name
, readl(gp
->regs
+ RXDMA_DONE
), gp
->rx_new
);
771 done
= readl(gp
->regs
+ RXDMA_DONE
);
773 struct gem_rxd
*rxd
= &gp
->init_block
->rxd
[entry
];
775 u64 status
= le64_to_cpu(rxd
->status_word
);
779 if ((status
& RXDCTRL_OWN
) != 0)
782 if (work_done
>= RX_RING_SIZE
|| work_done
>= work_to_do
)
785 /* When writing back RX descriptor, GEM writes status
786 * then buffer address, possibly in separate transactions.
787 * If we don't wait for the chip to write both, we could
788 * post a new buffer to this descriptor then have GEM spam
789 * on the buffer address. We sync on the RX completion
790 * register to prevent this from happening.
793 done
= readl(gp
->regs
+ RXDMA_DONE
);
798 /* We can now account for the work we're about to do */
801 skb
= gp
->rx_skbs
[entry
];
803 len
= (status
& RXDCTRL_BUFSZ
) >> 16;
804 if ((len
< ETH_ZLEN
) || (status
& RXDCTRL_BAD
)) {
805 dev
->stats
.rx_errors
++;
807 dev
->stats
.rx_length_errors
++;
808 if (len
& RXDCTRL_BAD
)
809 dev
->stats
.rx_crc_errors
++;
811 /* We'll just return it to GEM. */
813 dev
->stats
.rx_dropped
++;
817 dma_addr
= le64_to_cpu(rxd
->buffer
);
818 if (len
> RX_COPY_THRESHOLD
) {
819 struct sk_buff
*new_skb
;
821 new_skb
= gem_alloc_skb(dev
, RX_BUF_ALLOC_SIZE(gp
), GFP_ATOMIC
);
822 if (new_skb
== NULL
) {
826 pci_unmap_page(gp
->pdev
, dma_addr
,
827 RX_BUF_ALLOC_SIZE(gp
),
829 gp
->rx_skbs
[entry
] = new_skb
;
830 skb_put(new_skb
, (gp
->rx_buf_sz
+ RX_OFFSET
));
831 rxd
->buffer
= cpu_to_le64(pci_map_page(gp
->pdev
,
832 virt_to_page(new_skb
->data
),
833 offset_in_page(new_skb
->data
),
834 RX_BUF_ALLOC_SIZE(gp
),
835 PCI_DMA_FROMDEVICE
));
836 skb_reserve(new_skb
, RX_OFFSET
);
838 /* Trim the original skb for the netif. */
841 struct sk_buff
*copy_skb
= netdev_alloc_skb(dev
, len
+ 2);
843 if (copy_skb
== NULL
) {
848 skb_reserve(copy_skb
, 2);
849 skb_put(copy_skb
, len
);
850 pci_dma_sync_single_for_cpu(gp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
851 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
852 pci_dma_sync_single_for_device(gp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
854 /* We'll reuse the original ring buffer. */
858 csum
= (__force __sum16
)htons((status
& RXDCTRL_TCPCSUM
) ^ 0xffff);
859 skb
->csum
= csum_unfold(csum
);
860 skb
->ip_summed
= CHECKSUM_COMPLETE
;
861 skb
->protocol
= eth_type_trans(skb
, gp
->dev
);
863 napi_gro_receive(&gp
->napi
, skb
);
865 dev
->stats
.rx_packets
++;
866 dev
->stats
.rx_bytes
+= len
;
869 entry
= NEXT_RX(entry
);
872 gem_post_rxds(gp
, entry
);
877 netdev_info(gp
->dev
, "Memory squeeze, deferring packet\n");
882 static int gem_poll(struct napi_struct
*napi
, int budget
)
884 struct gem
*gp
= container_of(napi
, struct gem
, napi
);
885 struct net_device
*dev
= gp
->dev
;
890 /* Handle anomalies */
891 if (unlikely(gp
->status
& GREG_STAT_ABNORMAL
)) {
892 struct netdev_queue
*txq
= netdev_get_tx_queue(dev
, 0);
895 /* We run the abnormal interrupt handling code with
896 * the Tx lock. It only resets the Rx portion of the
897 * chip, but we need to guard it against DMA being
898 * restarted by the link poll timer
900 __netif_tx_lock(txq
, smp_processor_id());
901 reset
= gem_abnormal_irq(dev
, gp
, gp
->status
);
902 __netif_tx_unlock(txq
);
904 gem_schedule_reset(gp
);
910 /* Run TX completion thread */
911 gem_tx(dev
, gp
, gp
->status
);
913 /* Run RX thread. We don't use any locking here,
914 * code willing to do bad things - like cleaning the
915 * rx ring - must call napi_disable(), which
916 * schedule_timeout()'s if polling is already disabled.
918 work_done
+= gem_rx(gp
, budget
- work_done
);
920 if (work_done
>= budget
)
923 gp
->status
= readl(gp
->regs
+ GREG_STAT
);
924 } while (gp
->status
& GREG_STAT_NAPI
);
926 napi_complete_done(napi
, work_done
);
932 static irqreturn_t
gem_interrupt(int irq
, void *dev_id
)
934 struct net_device
*dev
= dev_id
;
935 struct gem
*gp
= netdev_priv(dev
);
937 if (napi_schedule_prep(&gp
->napi
)) {
938 u32 gem_status
= readl(gp
->regs
+ GREG_STAT
);
940 if (unlikely(gem_status
== 0)) {
941 napi_enable(&gp
->napi
);
944 if (netif_msg_intr(gp
))
945 printk(KERN_DEBUG
"%s: gem_interrupt() gem_status: 0x%x\n",
946 gp
->dev
->name
, gem_status
);
948 gp
->status
= gem_status
;
949 gem_disable_ints(gp
);
950 __napi_schedule(&gp
->napi
);
953 /* If polling was disabled at the time we received that
954 * interrupt, we may return IRQ_HANDLED here while we
955 * should return IRQ_NONE. No big deal...
960 #ifdef CONFIG_NET_POLL_CONTROLLER
961 static void gem_poll_controller(struct net_device
*dev
)
963 struct gem
*gp
= netdev_priv(dev
);
965 disable_irq(gp
->pdev
->irq
);
966 gem_interrupt(gp
->pdev
->irq
, dev
);
967 enable_irq(gp
->pdev
->irq
);
971 static void gem_tx_timeout(struct net_device
*dev
)
973 struct gem
*gp
= netdev_priv(dev
);
975 netdev_err(dev
, "transmit timed out, resetting\n");
977 netdev_err(dev
, "TX_STATE[%08x:%08x:%08x]\n",
978 readl(gp
->regs
+ TXDMA_CFG
),
979 readl(gp
->regs
+ MAC_TXSTAT
),
980 readl(gp
->regs
+ MAC_TXCFG
));
981 netdev_err(dev
, "RX_STATE[%08x:%08x:%08x]\n",
982 readl(gp
->regs
+ RXDMA_CFG
),
983 readl(gp
->regs
+ MAC_RXSTAT
),
984 readl(gp
->regs
+ MAC_RXCFG
));
986 gem_schedule_reset(gp
);
989 static __inline__
int gem_intme(int entry
)
991 /* Algorithm: IRQ every 1/2 of descriptors. */
992 if (!(entry
& ((TX_RING_SIZE
>>1)-1)))
998 static netdev_tx_t
gem_start_xmit(struct sk_buff
*skb
,
999 struct net_device
*dev
)
1001 struct gem
*gp
= netdev_priv(dev
);
1006 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1007 const u64 csum_start_off
= skb_checksum_start_offset(skb
);
1008 const u64 csum_stuff_off
= csum_start_off
+ skb
->csum_offset
;
1010 ctrl
= (TXDCTRL_CENAB
|
1011 (csum_start_off
<< 15) |
1012 (csum_stuff_off
<< 21));
1015 if (unlikely(TX_BUFFS_AVAIL(gp
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
1016 /* This is a hard error, log it. */
1017 if (!netif_queue_stopped(dev
)) {
1018 netif_stop_queue(dev
);
1019 netdev_err(dev
, "BUG! Tx Ring full when queue awake!\n");
1021 return NETDEV_TX_BUSY
;
1025 gp
->tx_skbs
[entry
] = skb
;
1027 if (skb_shinfo(skb
)->nr_frags
== 0) {
1028 struct gem_txd
*txd
= &gp
->init_block
->txd
[entry
];
1033 mapping
= pci_map_page(gp
->pdev
,
1034 virt_to_page(skb
->data
),
1035 offset_in_page(skb
->data
),
1036 len
, PCI_DMA_TODEVICE
);
1037 ctrl
|= TXDCTRL_SOF
| TXDCTRL_EOF
| len
;
1038 if (gem_intme(entry
))
1039 ctrl
|= TXDCTRL_INTME
;
1040 txd
->buffer
= cpu_to_le64(mapping
);
1042 txd
->control_word
= cpu_to_le64(ctrl
);
1043 entry
= NEXT_TX(entry
);
1045 struct gem_txd
*txd
;
1048 dma_addr_t first_mapping
;
1049 int frag
, first_entry
= entry
;
1052 if (gem_intme(entry
))
1053 intme
|= TXDCTRL_INTME
;
1055 /* We must give this initial chunk to the device last.
1056 * Otherwise we could race with the device.
1058 first_len
= skb_headlen(skb
);
1059 first_mapping
= pci_map_page(gp
->pdev
, virt_to_page(skb
->data
),
1060 offset_in_page(skb
->data
),
1061 first_len
, PCI_DMA_TODEVICE
);
1062 entry
= NEXT_TX(entry
);
1064 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1065 const skb_frag_t
*this_frag
= &skb_shinfo(skb
)->frags
[frag
];
1070 len
= skb_frag_size(this_frag
);
1071 mapping
= skb_frag_dma_map(&gp
->pdev
->dev
, this_frag
,
1072 0, len
, DMA_TO_DEVICE
);
1074 if (frag
== skb_shinfo(skb
)->nr_frags
- 1)
1075 this_ctrl
|= TXDCTRL_EOF
;
1077 txd
= &gp
->init_block
->txd
[entry
];
1078 txd
->buffer
= cpu_to_le64(mapping
);
1080 txd
->control_word
= cpu_to_le64(this_ctrl
| len
);
1082 if (gem_intme(entry
))
1083 intme
|= TXDCTRL_INTME
;
1085 entry
= NEXT_TX(entry
);
1087 txd
= &gp
->init_block
->txd
[first_entry
];
1088 txd
->buffer
= cpu_to_le64(first_mapping
);
1091 cpu_to_le64(ctrl
| TXDCTRL_SOF
| intme
| first_len
);
1095 if (unlikely(TX_BUFFS_AVAIL(gp
) <= (MAX_SKB_FRAGS
+ 1))) {
1096 netif_stop_queue(dev
);
1098 /* netif_stop_queue() must be done before checking
1099 * checking tx index in TX_BUFFS_AVAIL() below, because
1100 * in gem_tx(), we update tx_old before checking for
1101 * netif_queue_stopped().
1104 if (TX_BUFFS_AVAIL(gp
) > (MAX_SKB_FRAGS
+ 1))
1105 netif_wake_queue(dev
);
1107 if (netif_msg_tx_queued(gp
))
1108 printk(KERN_DEBUG
"%s: tx queued, slot %d, skblen %d\n",
1109 dev
->name
, entry
, skb
->len
);
1111 writel(gp
->tx_new
, gp
->regs
+ TXDMA_KICK
);
1113 return NETDEV_TX_OK
;
1116 static void gem_pcs_reset(struct gem
*gp
)
1121 /* Reset PCS unit. */
1122 val
= readl(gp
->regs
+ PCS_MIICTRL
);
1123 val
|= PCS_MIICTRL_RST
;
1124 writel(val
, gp
->regs
+ PCS_MIICTRL
);
1127 while (readl(gp
->regs
+ PCS_MIICTRL
) & PCS_MIICTRL_RST
) {
1133 netdev_warn(gp
->dev
, "PCS reset bit would not clear\n");
1136 static void gem_pcs_reinit_adv(struct gem
*gp
)
1140 /* Make sure PCS is disabled while changing advertisement
1143 val
= readl(gp
->regs
+ PCS_CFG
);
1144 val
&= ~(PCS_CFG_ENABLE
| PCS_CFG_TO
);
1145 writel(val
, gp
->regs
+ PCS_CFG
);
1147 /* Advertise all capabilities except asymmetric
1150 val
= readl(gp
->regs
+ PCS_MIIADV
);
1151 val
|= (PCS_MIIADV_FD
| PCS_MIIADV_HD
|
1152 PCS_MIIADV_SP
| PCS_MIIADV_AP
);
1153 writel(val
, gp
->regs
+ PCS_MIIADV
);
1155 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1156 * and re-enable PCS.
1158 val
= readl(gp
->regs
+ PCS_MIICTRL
);
1159 val
|= (PCS_MIICTRL_RAN
| PCS_MIICTRL_ANE
);
1160 val
&= ~PCS_MIICTRL_WB
;
1161 writel(val
, gp
->regs
+ PCS_MIICTRL
);
1163 val
= readl(gp
->regs
+ PCS_CFG
);
1164 val
|= PCS_CFG_ENABLE
;
1165 writel(val
, gp
->regs
+ PCS_CFG
);
1167 /* Make sure serialink loopback is off. The meaning
1168 * of this bit is logically inverted based upon whether
1169 * you are in Serialink or SERDES mode.
1171 val
= readl(gp
->regs
+ PCS_SCTRL
);
1172 if (gp
->phy_type
== phy_serialink
)
1173 val
&= ~PCS_SCTRL_LOOP
;
1175 val
|= PCS_SCTRL_LOOP
;
1176 writel(val
, gp
->regs
+ PCS_SCTRL
);
1179 #define STOP_TRIES 32
1181 static void gem_reset(struct gem
*gp
)
1186 /* Make sure we won't get any more interrupts */
1187 writel(0xffffffff, gp
->regs
+ GREG_IMASK
);
1189 /* Reset the chip */
1190 writel(gp
->swrst_base
| GREG_SWRST_TXRST
| GREG_SWRST_RXRST
,
1191 gp
->regs
+ GREG_SWRST
);
1197 val
= readl(gp
->regs
+ GREG_SWRST
);
1200 } while (val
& (GREG_SWRST_TXRST
| GREG_SWRST_RXRST
));
1203 netdev_err(gp
->dev
, "SW reset is ghetto\n");
1205 if (gp
->phy_type
== phy_serialink
|| gp
->phy_type
== phy_serdes
)
1206 gem_pcs_reinit_adv(gp
);
1209 static void gem_start_dma(struct gem
*gp
)
1213 /* We are ready to rock, turn everything on. */
1214 val
= readl(gp
->regs
+ TXDMA_CFG
);
1215 writel(val
| TXDMA_CFG_ENABLE
, gp
->regs
+ TXDMA_CFG
);
1216 val
= readl(gp
->regs
+ RXDMA_CFG
);
1217 writel(val
| RXDMA_CFG_ENABLE
, gp
->regs
+ RXDMA_CFG
);
1218 val
= readl(gp
->regs
+ MAC_TXCFG
);
1219 writel(val
| MAC_TXCFG_ENAB
, gp
->regs
+ MAC_TXCFG
);
1220 val
= readl(gp
->regs
+ MAC_RXCFG
);
1221 writel(val
| MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
1223 (void) readl(gp
->regs
+ MAC_RXCFG
);
1226 gem_enable_ints(gp
);
1228 writel(RX_RING_SIZE
- 4, gp
->regs
+ RXDMA_KICK
);
1231 /* DMA won't be actually stopped before about 4ms tho ...
1233 static void gem_stop_dma(struct gem
*gp
)
1237 /* We are done rocking, turn everything off. */
1238 val
= readl(gp
->regs
+ TXDMA_CFG
);
1239 writel(val
& ~TXDMA_CFG_ENABLE
, gp
->regs
+ TXDMA_CFG
);
1240 val
= readl(gp
->regs
+ RXDMA_CFG
);
1241 writel(val
& ~RXDMA_CFG_ENABLE
, gp
->regs
+ RXDMA_CFG
);
1242 val
= readl(gp
->regs
+ MAC_TXCFG
);
1243 writel(val
& ~MAC_TXCFG_ENAB
, gp
->regs
+ MAC_TXCFG
);
1244 val
= readl(gp
->regs
+ MAC_RXCFG
);
1245 writel(val
& ~MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
1247 (void) readl(gp
->regs
+ MAC_RXCFG
);
1249 /* Need to wait a bit ... done by the caller */
1253 // XXX dbl check what that function should do when called on PCS PHY
1254 static void gem_begin_auto_negotiation(struct gem
*gp
,
1255 const struct ethtool_link_ksettings
*ep
)
1257 u32 advertise
, features
;
1264 ethtool_convert_link_mode_to_legacy_u32(
1265 &advertising
, ep
->link_modes
.advertising
);
1267 if (gp
->phy_type
!= phy_mii_mdio0
&&
1268 gp
->phy_type
!= phy_mii_mdio1
)
1271 /* Setup advertise */
1272 if (found_mii_phy(gp
))
1273 features
= gp
->phy_mii
.def
->features
;
1277 advertise
= features
& ADVERTISE_MASK
;
1278 if (gp
->phy_mii
.advertising
!= 0)
1279 advertise
&= gp
->phy_mii
.advertising
;
1281 autoneg
= gp
->want_autoneg
;
1282 speed
= gp
->phy_mii
.speed
;
1283 duplex
= gp
->phy_mii
.duplex
;
1285 /* Setup link parameters */
1288 if (ep
->base
.autoneg
== AUTONEG_ENABLE
) {
1289 advertise
= advertising
;
1293 speed
= ep
->base
.speed
;
1294 duplex
= ep
->base
.duplex
;
1298 /* Sanitize settings based on PHY capabilities */
1299 if ((features
& SUPPORTED_Autoneg
) == 0)
1301 if (speed
== SPEED_1000
&&
1302 !(features
& (SUPPORTED_1000baseT_Half
| SUPPORTED_1000baseT_Full
)))
1304 if (speed
== SPEED_100
&&
1305 !(features
& (SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
)))
1307 if (duplex
== DUPLEX_FULL
&&
1308 !(features
& (SUPPORTED_1000baseT_Full
|
1309 SUPPORTED_100baseT_Full
|
1310 SUPPORTED_10baseT_Full
)))
1311 duplex
= DUPLEX_HALF
;
1315 /* If we are asleep, we don't try to actually setup the PHY, we
1316 * just store the settings
1318 if (!netif_device_present(gp
->dev
)) {
1319 gp
->phy_mii
.autoneg
= gp
->want_autoneg
= autoneg
;
1320 gp
->phy_mii
.speed
= speed
;
1321 gp
->phy_mii
.duplex
= duplex
;
1325 /* Configure PHY & start aneg */
1326 gp
->want_autoneg
= autoneg
;
1328 if (found_mii_phy(gp
))
1329 gp
->phy_mii
.def
->ops
->setup_aneg(&gp
->phy_mii
, advertise
);
1330 gp
->lstate
= link_aneg
;
1332 if (found_mii_phy(gp
))
1333 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
, speed
, duplex
);
1334 gp
->lstate
= link_force_ok
;
1338 gp
->timer_ticks
= 0;
1339 mod_timer(&gp
->link_timer
, jiffies
+ ((12 * HZ
) / 10));
1342 /* A link-up condition has occurred, initialize and enable the
1345 static int gem_set_link_modes(struct gem
*gp
)
1347 struct netdev_queue
*txq
= netdev_get_tx_queue(gp
->dev
, 0);
1348 int full_duplex
, speed
, pause
;
1355 if (found_mii_phy(gp
)) {
1356 if (gp
->phy_mii
.def
->ops
->read_link(&gp
->phy_mii
))
1358 full_duplex
= (gp
->phy_mii
.duplex
== DUPLEX_FULL
);
1359 speed
= gp
->phy_mii
.speed
;
1360 pause
= gp
->phy_mii
.pause
;
1361 } else if (gp
->phy_type
== phy_serialink
||
1362 gp
->phy_type
== phy_serdes
) {
1363 u32 pcs_lpa
= readl(gp
->regs
+ PCS_MIILP
);
1365 if ((pcs_lpa
& PCS_MIIADV_FD
) || gp
->phy_type
== phy_serdes
)
1370 netif_info(gp
, link
, gp
->dev
, "Link is up at %d Mbps, %s-duplex\n",
1371 speed
, (full_duplex
? "full" : "half"));
1374 /* We take the tx queue lock to avoid collisions between
1375 * this code, the tx path and the NAPI-driven error path
1377 __netif_tx_lock(txq
, smp_processor_id());
1379 val
= (MAC_TXCFG_EIPG0
| MAC_TXCFG_NGU
);
1381 val
|= (MAC_TXCFG_ICS
| MAC_TXCFG_ICOLL
);
1383 /* MAC_TXCFG_NBO must be zero. */
1385 writel(val
, gp
->regs
+ MAC_TXCFG
);
1387 val
= (MAC_XIFCFG_OE
| MAC_XIFCFG_LLED
);
1389 (gp
->phy_type
== phy_mii_mdio0
||
1390 gp
->phy_type
== phy_mii_mdio1
)) {
1391 val
|= MAC_XIFCFG_DISE
;
1392 } else if (full_duplex
) {
1393 val
|= MAC_XIFCFG_FLED
;
1396 if (speed
== SPEED_1000
)
1397 val
|= (MAC_XIFCFG_GMII
);
1399 writel(val
, gp
->regs
+ MAC_XIFCFG
);
1401 /* If gigabit and half-duplex, enable carrier extension
1402 * mode. Else, disable it.
1404 if (speed
== SPEED_1000
&& !full_duplex
) {
1405 val
= readl(gp
->regs
+ MAC_TXCFG
);
1406 writel(val
| MAC_TXCFG_TCE
, gp
->regs
+ MAC_TXCFG
);
1408 val
= readl(gp
->regs
+ MAC_RXCFG
);
1409 writel(val
| MAC_RXCFG_RCE
, gp
->regs
+ MAC_RXCFG
);
1411 val
= readl(gp
->regs
+ MAC_TXCFG
);
1412 writel(val
& ~MAC_TXCFG_TCE
, gp
->regs
+ MAC_TXCFG
);
1414 val
= readl(gp
->regs
+ MAC_RXCFG
);
1415 writel(val
& ~MAC_RXCFG_RCE
, gp
->regs
+ MAC_RXCFG
);
1418 if (gp
->phy_type
== phy_serialink
||
1419 gp
->phy_type
== phy_serdes
) {
1420 u32 pcs_lpa
= readl(gp
->regs
+ PCS_MIILP
);
1422 if (pcs_lpa
& (PCS_MIIADV_SP
| PCS_MIIADV_AP
))
1427 writel(512, gp
->regs
+ MAC_STIME
);
1429 writel(64, gp
->regs
+ MAC_STIME
);
1430 val
= readl(gp
->regs
+ MAC_MCCFG
);
1432 val
|= (MAC_MCCFG_SPE
| MAC_MCCFG_RPE
);
1434 val
&= ~(MAC_MCCFG_SPE
| MAC_MCCFG_RPE
);
1435 writel(val
, gp
->regs
+ MAC_MCCFG
);
1439 __netif_tx_unlock(txq
);
1441 if (netif_msg_link(gp
)) {
1443 netdev_info(gp
->dev
,
1444 "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
1449 netdev_info(gp
->dev
, "Pause is disabled\n");
1456 static int gem_mdio_link_not_up(struct gem
*gp
)
1458 switch (gp
->lstate
) {
1459 case link_force_ret
:
1460 netif_info(gp
, link
, gp
->dev
,
1461 "Autoneg failed again, keeping forced mode\n");
1462 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
,
1463 gp
->last_forced_speed
, DUPLEX_HALF
);
1464 gp
->timer_ticks
= 5;
1465 gp
->lstate
= link_force_ok
;
1468 /* We try forced modes after a failed aneg only on PHYs that don't
1469 * have "magic_aneg" bit set, which means they internally do the
1470 * while forced-mode thingy. On these, we just restart aneg
1472 if (gp
->phy_mii
.def
->magic_aneg
)
1474 netif_info(gp
, link
, gp
->dev
, "switching to forced 100bt\n");
1475 /* Try forced modes. */
1476 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
, SPEED_100
,
1478 gp
->timer_ticks
= 5;
1479 gp
->lstate
= link_force_try
;
1481 case link_force_try
:
1482 /* Downgrade from 100 to 10 Mbps if necessary.
1483 * If already at 10Mbps, warn user about the
1484 * situation every 10 ticks.
1486 if (gp
->phy_mii
.speed
== SPEED_100
) {
1487 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
, SPEED_10
,
1489 gp
->timer_ticks
= 5;
1490 netif_info(gp
, link
, gp
->dev
,
1491 "switching to forced 10bt\n");
1500 static void gem_link_timer(struct timer_list
*t
)
1502 struct gem
*gp
= from_timer(gp
, t
, link_timer
);
1503 struct net_device
*dev
= gp
->dev
;
1504 int restart_aneg
= 0;
1506 /* There's no point doing anything if we're going to be reset */
1507 if (gp
->reset_task_pending
)
1510 if (gp
->phy_type
== phy_serialink
||
1511 gp
->phy_type
== phy_serdes
) {
1512 u32 val
= readl(gp
->regs
+ PCS_MIISTAT
);
1514 if (!(val
& PCS_MIISTAT_LS
))
1515 val
= readl(gp
->regs
+ PCS_MIISTAT
);
1517 if ((val
& PCS_MIISTAT_LS
) != 0) {
1518 if (gp
->lstate
== link_up
)
1521 gp
->lstate
= link_up
;
1522 netif_carrier_on(dev
);
1523 (void)gem_set_link_modes(gp
);
1527 if (found_mii_phy(gp
) && gp
->phy_mii
.def
->ops
->poll_link(&gp
->phy_mii
)) {
1528 /* Ok, here we got a link. If we had it due to a forced
1529 * fallback, and we were configured for autoneg, we do
1530 * retry a short autoneg pass. If you know your hub is
1531 * broken, use ethtool ;)
1533 if (gp
->lstate
== link_force_try
&& gp
->want_autoneg
) {
1534 gp
->lstate
= link_force_ret
;
1535 gp
->last_forced_speed
= gp
->phy_mii
.speed
;
1536 gp
->timer_ticks
= 5;
1537 if (netif_msg_link(gp
))
1539 "Got link after fallback, retrying autoneg once...\n");
1540 gp
->phy_mii
.def
->ops
->setup_aneg(&gp
->phy_mii
, gp
->phy_mii
.advertising
);
1541 } else if (gp
->lstate
!= link_up
) {
1542 gp
->lstate
= link_up
;
1543 netif_carrier_on(dev
);
1544 if (gem_set_link_modes(gp
))
1548 /* If the link was previously up, we restart the
1551 if (gp
->lstate
== link_up
) {
1552 gp
->lstate
= link_down
;
1553 netif_info(gp
, link
, dev
, "Link down\n");
1554 netif_carrier_off(dev
);
1555 gem_schedule_reset(gp
);
1556 /* The reset task will restart the timer */
1558 } else if (++gp
->timer_ticks
> 10) {
1559 if (found_mii_phy(gp
))
1560 restart_aneg
= gem_mdio_link_not_up(gp
);
1566 gem_begin_auto_negotiation(gp
, NULL
);
1570 mod_timer(&gp
->link_timer
, jiffies
+ ((12 * HZ
) / 10));
1573 static void gem_clean_rings(struct gem
*gp
)
1575 struct gem_init_block
*gb
= gp
->init_block
;
1576 struct sk_buff
*skb
;
1578 dma_addr_t dma_addr
;
1580 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1581 struct gem_rxd
*rxd
;
1584 if (gp
->rx_skbs
[i
] != NULL
) {
1585 skb
= gp
->rx_skbs
[i
];
1586 dma_addr
= le64_to_cpu(rxd
->buffer
);
1587 pci_unmap_page(gp
->pdev
, dma_addr
,
1588 RX_BUF_ALLOC_SIZE(gp
),
1589 PCI_DMA_FROMDEVICE
);
1590 dev_kfree_skb_any(skb
);
1591 gp
->rx_skbs
[i
] = NULL
;
1593 rxd
->status_word
= 0;
1598 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1599 if (gp
->tx_skbs
[i
] != NULL
) {
1600 struct gem_txd
*txd
;
1603 skb
= gp
->tx_skbs
[i
];
1604 gp
->tx_skbs
[i
] = NULL
;
1606 for (frag
= 0; frag
<= skb_shinfo(skb
)->nr_frags
; frag
++) {
1607 int ent
= i
& (TX_RING_SIZE
- 1);
1609 txd
= &gb
->txd
[ent
];
1610 dma_addr
= le64_to_cpu(txd
->buffer
);
1611 pci_unmap_page(gp
->pdev
, dma_addr
,
1612 le64_to_cpu(txd
->control_word
) &
1613 TXDCTRL_BUFSZ
, PCI_DMA_TODEVICE
);
1615 if (frag
!= skb_shinfo(skb
)->nr_frags
)
1618 dev_kfree_skb_any(skb
);
1623 static void gem_init_rings(struct gem
*gp
)
1625 struct gem_init_block
*gb
= gp
->init_block
;
1626 struct net_device
*dev
= gp
->dev
;
1628 dma_addr_t dma_addr
;
1630 gp
->rx_new
= gp
->rx_old
= gp
->tx_new
= gp
->tx_old
= 0;
1632 gem_clean_rings(gp
);
1634 gp
->rx_buf_sz
= max(dev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
,
1635 (unsigned)VLAN_ETH_FRAME_LEN
);
1637 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1638 struct sk_buff
*skb
;
1639 struct gem_rxd
*rxd
= &gb
->rxd
[i
];
1641 skb
= gem_alloc_skb(dev
, RX_BUF_ALLOC_SIZE(gp
), GFP_KERNEL
);
1644 rxd
->status_word
= 0;
1648 gp
->rx_skbs
[i
] = skb
;
1649 skb_put(skb
, (gp
->rx_buf_sz
+ RX_OFFSET
));
1650 dma_addr
= pci_map_page(gp
->pdev
,
1651 virt_to_page(skb
->data
),
1652 offset_in_page(skb
->data
),
1653 RX_BUF_ALLOC_SIZE(gp
),
1654 PCI_DMA_FROMDEVICE
);
1655 rxd
->buffer
= cpu_to_le64(dma_addr
);
1657 rxd
->status_word
= cpu_to_le64(RXDCTRL_FRESH(gp
));
1658 skb_reserve(skb
, RX_OFFSET
);
1661 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1662 struct gem_txd
*txd
= &gb
->txd
[i
];
1664 txd
->control_word
= 0;
1671 /* Init PHY interface and start link poll state machine */
1672 static void gem_init_phy(struct gem
*gp
)
1676 /* Revert MIF CFG setting done on stop_phy */
1677 mifcfg
= readl(gp
->regs
+ MIF_CFG
);
1678 mifcfg
&= ~MIF_CFG_BBMODE
;
1679 writel(mifcfg
, gp
->regs
+ MIF_CFG
);
1681 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_APPLE
) {
1684 /* Those delay sucks, the HW seem to love them though, I'll
1685 * serisouly consider breaking some locks here to be able
1686 * to schedule instead
1688 for (i
= 0; i
< 3; i
++) {
1689 #ifdef CONFIG_PPC_PMAC
1690 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET
, gp
->of_node
, 0, 0);
1693 /* Some PHYs used by apple have problem getting back to us,
1694 * we do an additional reset here
1696 sungem_phy_write(gp
, MII_BMCR
, BMCR_RESET
);
1698 if (sungem_phy_read(gp
, MII_BMCR
) != 0xffff)
1701 netdev_warn(gp
->dev
, "GMAC PHY not responding !\n");
1705 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
1706 gp
->pdev
->device
== PCI_DEVICE_ID_SUN_GEM
) {
1709 /* Init datapath mode register. */
1710 if (gp
->phy_type
== phy_mii_mdio0
||
1711 gp
->phy_type
== phy_mii_mdio1
) {
1712 val
= PCS_DMODE_MGM
;
1713 } else if (gp
->phy_type
== phy_serialink
) {
1714 val
= PCS_DMODE_SM
| PCS_DMODE_GMOE
;
1716 val
= PCS_DMODE_ESM
;
1719 writel(val
, gp
->regs
+ PCS_DMODE
);
1722 if (gp
->phy_type
== phy_mii_mdio0
||
1723 gp
->phy_type
== phy_mii_mdio1
) {
1724 /* Reset and detect MII PHY */
1725 sungem_phy_probe(&gp
->phy_mii
, gp
->mii_phy_addr
);
1728 if (gp
->phy_mii
.def
&& gp
->phy_mii
.def
->ops
->init
)
1729 gp
->phy_mii
.def
->ops
->init(&gp
->phy_mii
);
1732 gem_pcs_reinit_adv(gp
);
1735 /* Default aneg parameters */
1736 gp
->timer_ticks
= 0;
1737 gp
->lstate
= link_down
;
1738 netif_carrier_off(gp
->dev
);
1740 /* Print things out */
1741 if (gp
->phy_type
== phy_mii_mdio0
||
1742 gp
->phy_type
== phy_mii_mdio1
)
1743 netdev_info(gp
->dev
, "Found %s PHY\n",
1744 gp
->phy_mii
.def
? gp
->phy_mii
.def
->name
: "no");
1746 gem_begin_auto_negotiation(gp
, NULL
);
1749 static void gem_init_dma(struct gem
*gp
)
1751 u64 desc_dma
= (u64
) gp
->gblock_dvma
;
1754 val
= (TXDMA_CFG_BASE
| (0x7ff << 10) | TXDMA_CFG_PMODE
);
1755 writel(val
, gp
->regs
+ TXDMA_CFG
);
1757 writel(desc_dma
>> 32, gp
->regs
+ TXDMA_DBHI
);
1758 writel(desc_dma
& 0xffffffff, gp
->regs
+ TXDMA_DBLOW
);
1759 desc_dma
+= (INIT_BLOCK_TX_RING_SIZE
* sizeof(struct gem_txd
));
1761 writel(0, gp
->regs
+ TXDMA_KICK
);
1763 val
= (RXDMA_CFG_BASE
| (RX_OFFSET
<< 10) |
1764 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128
);
1765 writel(val
, gp
->regs
+ RXDMA_CFG
);
1767 writel(desc_dma
>> 32, gp
->regs
+ RXDMA_DBHI
);
1768 writel(desc_dma
& 0xffffffff, gp
->regs
+ RXDMA_DBLOW
);
1770 writel(RX_RING_SIZE
- 4, gp
->regs
+ RXDMA_KICK
);
1772 val
= (((gp
->rx_pause_off
/ 64) << 0) & RXDMA_PTHRESH_OFF
);
1773 val
|= (((gp
->rx_pause_on
/ 64) << 12) & RXDMA_PTHRESH_ON
);
1774 writel(val
, gp
->regs
+ RXDMA_PTHRESH
);
1776 if (readl(gp
->regs
+ GREG_BIFCFG
) & GREG_BIFCFG_M66EN
)
1777 writel(((5 & RXDMA_BLANK_IPKTS
) |
1778 ((8 << 12) & RXDMA_BLANK_ITIME
)),
1779 gp
->regs
+ RXDMA_BLANK
);
1781 writel(((5 & RXDMA_BLANK_IPKTS
) |
1782 ((4 << 12) & RXDMA_BLANK_ITIME
)),
1783 gp
->regs
+ RXDMA_BLANK
);
1786 static u32
gem_setup_multicast(struct gem
*gp
)
1791 if ((gp
->dev
->flags
& IFF_ALLMULTI
) ||
1792 (netdev_mc_count(gp
->dev
) > 256)) {
1793 for (i
=0; i
<16; i
++)
1794 writel(0xffff, gp
->regs
+ MAC_HASH0
+ (i
<< 2));
1795 rxcfg
|= MAC_RXCFG_HFE
;
1796 } else if (gp
->dev
->flags
& IFF_PROMISC
) {
1797 rxcfg
|= MAC_RXCFG_PROM
;
1801 struct netdev_hw_addr
*ha
;
1804 memset(hash_table
, 0, sizeof(hash_table
));
1805 netdev_for_each_mc_addr(ha
, gp
->dev
) {
1806 crc
= ether_crc_le(6, ha
->addr
);
1808 hash_table
[crc
>> 4] |= 1 << (15 - (crc
& 0xf));
1810 for (i
=0; i
<16; i
++)
1811 writel(hash_table
[i
], gp
->regs
+ MAC_HASH0
+ (i
<< 2));
1812 rxcfg
|= MAC_RXCFG_HFE
;
1818 static void gem_init_mac(struct gem
*gp
)
1820 unsigned char *e
= &gp
->dev
->dev_addr
[0];
1822 writel(0x1bf0, gp
->regs
+ MAC_SNDPAUSE
);
1824 writel(0x00, gp
->regs
+ MAC_IPG0
);
1825 writel(0x08, gp
->regs
+ MAC_IPG1
);
1826 writel(0x04, gp
->regs
+ MAC_IPG2
);
1827 writel(0x40, gp
->regs
+ MAC_STIME
);
1828 writel(0x40, gp
->regs
+ MAC_MINFSZ
);
1830 /* Ethernet payload + header + FCS + optional VLAN tag. */
1831 writel(0x20000000 | (gp
->rx_buf_sz
+ 4), gp
->regs
+ MAC_MAXFSZ
);
1833 writel(0x07, gp
->regs
+ MAC_PASIZE
);
1834 writel(0x04, gp
->regs
+ MAC_JAMSIZE
);
1835 writel(0x10, gp
->regs
+ MAC_ATTLIM
);
1836 writel(0x8808, gp
->regs
+ MAC_MCTYPE
);
1838 writel((e
[5] | (e
[4] << 8)) & 0x3ff, gp
->regs
+ MAC_RANDSEED
);
1840 writel((e
[4] << 8) | e
[5], gp
->regs
+ MAC_ADDR0
);
1841 writel((e
[2] << 8) | e
[3], gp
->regs
+ MAC_ADDR1
);
1842 writel((e
[0] << 8) | e
[1], gp
->regs
+ MAC_ADDR2
);
1844 writel(0, gp
->regs
+ MAC_ADDR3
);
1845 writel(0, gp
->regs
+ MAC_ADDR4
);
1846 writel(0, gp
->regs
+ MAC_ADDR5
);
1848 writel(0x0001, gp
->regs
+ MAC_ADDR6
);
1849 writel(0xc200, gp
->regs
+ MAC_ADDR7
);
1850 writel(0x0180, gp
->regs
+ MAC_ADDR8
);
1852 writel(0, gp
->regs
+ MAC_AFILT0
);
1853 writel(0, gp
->regs
+ MAC_AFILT1
);
1854 writel(0, gp
->regs
+ MAC_AFILT2
);
1855 writel(0, gp
->regs
+ MAC_AF21MSK
);
1856 writel(0, gp
->regs
+ MAC_AF0MSK
);
1858 gp
->mac_rx_cfg
= gem_setup_multicast(gp
);
1860 gp
->mac_rx_cfg
|= MAC_RXCFG_SFCS
;
1862 writel(0, gp
->regs
+ MAC_NCOLL
);
1863 writel(0, gp
->regs
+ MAC_FASUCC
);
1864 writel(0, gp
->regs
+ MAC_ECOLL
);
1865 writel(0, gp
->regs
+ MAC_LCOLL
);
1866 writel(0, gp
->regs
+ MAC_DTIMER
);
1867 writel(0, gp
->regs
+ MAC_PATMPS
);
1868 writel(0, gp
->regs
+ MAC_RFCTR
);
1869 writel(0, gp
->regs
+ MAC_LERR
);
1870 writel(0, gp
->regs
+ MAC_AERR
);
1871 writel(0, gp
->regs
+ MAC_FCSERR
);
1872 writel(0, gp
->regs
+ MAC_RXCVERR
);
1874 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1875 * them once a link is established.
1877 writel(0, gp
->regs
+ MAC_TXCFG
);
1878 writel(gp
->mac_rx_cfg
, gp
->regs
+ MAC_RXCFG
);
1879 writel(0, gp
->regs
+ MAC_MCCFG
);
1880 writel(0, gp
->regs
+ MAC_XIFCFG
);
1882 /* Setup MAC interrupts. We want to get all of the interesting
1883 * counter expiration events, but we do not want to hear about
1884 * normal rx/tx as the DMA engine tells us that.
1886 writel(MAC_TXSTAT_XMIT
, gp
->regs
+ MAC_TXMASK
);
1887 writel(MAC_RXSTAT_RCV
, gp
->regs
+ MAC_RXMASK
);
1889 /* Don't enable even the PAUSE interrupts for now, we
1890 * make no use of those events other than to record them.
1892 writel(0xffffffff, gp
->regs
+ MAC_MCMASK
);
1894 /* Don't enable GEM's WOL in normal operations
1897 writel(0, gp
->regs
+ WOL_WAKECSR
);
1900 static void gem_init_pause_thresholds(struct gem
*gp
)
1904 /* Calculate pause thresholds. Setting the OFF threshold to the
1905 * full RX fifo size effectively disables PAUSE generation which
1906 * is what we do for 10/100 only GEMs which have FIFOs too small
1907 * to make real gains from PAUSE.
1909 if (gp
->rx_fifo_sz
<= (2 * 1024)) {
1910 gp
->rx_pause_off
= gp
->rx_pause_on
= gp
->rx_fifo_sz
;
1912 int max_frame
= (gp
->rx_buf_sz
+ 4 + 64) & ~63;
1913 int off
= (gp
->rx_fifo_sz
- (max_frame
* 2));
1914 int on
= off
- max_frame
;
1916 gp
->rx_pause_off
= off
;
1917 gp
->rx_pause_on
= on
;
1921 /* Configure the chip "burst" DMA mode & enable some
1922 * HW bug fixes on Apple version
1925 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_APPLE
)
1926 cfg
|= GREG_CFG_RONPAULBIT
| GREG_CFG_ENBUG2FIX
;
1927 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1928 cfg
|= GREG_CFG_IBURST
;
1930 cfg
|= ((31 << 1) & GREG_CFG_TXDMALIM
);
1931 cfg
|= ((31 << 6) & GREG_CFG_RXDMALIM
);
1932 writel(cfg
, gp
->regs
+ GREG_CFG
);
1934 /* If Infinite Burst didn't stick, then use different
1935 * thresholds (and Apple bug fixes don't exist)
1937 if (!(readl(gp
->regs
+ GREG_CFG
) & GREG_CFG_IBURST
)) {
1938 cfg
= ((2 << 1) & GREG_CFG_TXDMALIM
);
1939 cfg
|= ((8 << 6) & GREG_CFG_RXDMALIM
);
1940 writel(cfg
, gp
->regs
+ GREG_CFG
);
1944 static int gem_check_invariants(struct gem
*gp
)
1946 struct pci_dev
*pdev
= gp
->pdev
;
1949 /* On Apple's sungem, we can't rely on registers as the chip
1950 * was been powered down by the firmware. The PHY is looked
1953 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
) {
1954 gp
->phy_type
= phy_mii_mdio0
;
1955 gp
->tx_fifo_sz
= readl(gp
->regs
+ TXDMA_FSZ
) * 64;
1956 gp
->rx_fifo_sz
= readl(gp
->regs
+ RXDMA_FSZ
) * 64;
1959 mif_cfg
= readl(gp
->regs
+ MIF_CFG
);
1960 mif_cfg
&= ~(MIF_CFG_PSELECT
|MIF_CFG_POLL
|MIF_CFG_BBMODE
|MIF_CFG_MDI1
);
1961 mif_cfg
|= MIF_CFG_MDI0
;
1962 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
1963 writel(PCS_DMODE_MGM
, gp
->regs
+ PCS_DMODE
);
1964 writel(MAC_XIFCFG_OE
, gp
->regs
+ MAC_XIFCFG
);
1966 /* We hard-code the PHY address so we can properly bring it out of
1967 * reset later on, we can't really probe it at this point, though
1968 * that isn't an issue.
1970 if (gp
->pdev
->device
== PCI_DEVICE_ID_APPLE_K2_GMAC
)
1971 gp
->mii_phy_addr
= 1;
1973 gp
->mii_phy_addr
= 0;
1978 mif_cfg
= readl(gp
->regs
+ MIF_CFG
);
1980 if (pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
1981 pdev
->device
== PCI_DEVICE_ID_SUN_RIO_GEM
) {
1982 /* One of the MII PHYs _must_ be present
1983 * as this chip has no gigabit PHY.
1985 if ((mif_cfg
& (MIF_CFG_MDI0
| MIF_CFG_MDI1
)) == 0) {
1986 pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1992 /* Determine initial PHY interface type guess. MDIO1 is the
1993 * external PHY and thus takes precedence over MDIO0.
1996 if (mif_cfg
& MIF_CFG_MDI1
) {
1997 gp
->phy_type
= phy_mii_mdio1
;
1998 mif_cfg
|= MIF_CFG_PSELECT
;
1999 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
2000 } else if (mif_cfg
& MIF_CFG_MDI0
) {
2001 gp
->phy_type
= phy_mii_mdio0
;
2002 mif_cfg
&= ~MIF_CFG_PSELECT
;
2003 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
2008 p
= of_get_property(gp
->of_node
, "shared-pins", NULL
);
2009 if (p
&& !strcmp(p
, "serdes"))
2010 gp
->phy_type
= phy_serdes
;
2013 gp
->phy_type
= phy_serialink
;
2015 if (gp
->phy_type
== phy_mii_mdio1
||
2016 gp
->phy_type
== phy_mii_mdio0
) {
2019 for (i
= 0; i
< 32; i
++) {
2020 gp
->mii_phy_addr
= i
;
2021 if (sungem_phy_read(gp
, MII_BMCR
) != 0xffff)
2025 if (pdev
->device
!= PCI_DEVICE_ID_SUN_GEM
) {
2026 pr_err("RIO MII phy will not respond\n");
2029 gp
->phy_type
= phy_serdes
;
2033 /* Fetch the FIFO configurations now too. */
2034 gp
->tx_fifo_sz
= readl(gp
->regs
+ TXDMA_FSZ
) * 64;
2035 gp
->rx_fifo_sz
= readl(gp
->regs
+ RXDMA_FSZ
) * 64;
2037 if (pdev
->vendor
== PCI_VENDOR_ID_SUN
) {
2038 if (pdev
->device
== PCI_DEVICE_ID_SUN_GEM
) {
2039 if (gp
->tx_fifo_sz
!= (9 * 1024) ||
2040 gp
->rx_fifo_sz
!= (20 * 1024)) {
2041 pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2042 gp
->tx_fifo_sz
, gp
->rx_fifo_sz
);
2047 if (gp
->tx_fifo_sz
!= (2 * 1024) ||
2048 gp
->rx_fifo_sz
!= (2 * 1024)) {
2049 pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2050 gp
->tx_fifo_sz
, gp
->rx_fifo_sz
);
2053 gp
->swrst_base
= (64 / 4) << GREG_SWRST_CACHE_SHIFT
;
2060 static void gem_reinit_chip(struct gem
*gp
)
2062 /* Reset the chip */
2065 /* Make sure ints are disabled */
2066 gem_disable_ints(gp
);
2068 /* Allocate & setup ring buffers */
2071 /* Configure pause thresholds */
2072 gem_init_pause_thresholds(gp
);
2074 /* Init DMA & MAC engines */
2080 static void gem_stop_phy(struct gem
*gp
, int wol
)
2084 /* Let the chip settle down a bit, it seems that helps
2085 * for sleep mode on some models
2089 /* Make sure we aren't polling PHY status change. We
2090 * don't currently use that feature though
2092 mifcfg
= readl(gp
->regs
+ MIF_CFG
);
2093 mifcfg
&= ~MIF_CFG_POLL
;
2094 writel(mifcfg
, gp
->regs
+ MIF_CFG
);
2096 if (wol
&& gp
->has_wol
) {
2097 unsigned char *e
= &gp
->dev
->dev_addr
[0];
2100 /* Setup wake-on-lan for MAGIC packet */
2101 writel(MAC_RXCFG_HFE
| MAC_RXCFG_SFCS
| MAC_RXCFG_ENAB
,
2102 gp
->regs
+ MAC_RXCFG
);
2103 writel((e
[4] << 8) | e
[5], gp
->regs
+ WOL_MATCH0
);
2104 writel((e
[2] << 8) | e
[3], gp
->regs
+ WOL_MATCH1
);
2105 writel((e
[0] << 8) | e
[1], gp
->regs
+ WOL_MATCH2
);
2107 writel(WOL_MCOUNT_N
| WOL_MCOUNT_M
, gp
->regs
+ WOL_MCOUNT
);
2108 csr
= WOL_WAKECSR_ENABLE
;
2109 if ((readl(gp
->regs
+ MAC_XIFCFG
) & MAC_XIFCFG_GMII
) == 0)
2110 csr
|= WOL_WAKECSR_MII
;
2111 writel(csr
, gp
->regs
+ WOL_WAKECSR
);
2113 writel(0, gp
->regs
+ MAC_RXCFG
);
2114 (void)readl(gp
->regs
+ MAC_RXCFG
);
2115 /* Machine sleep will die in strange ways if we
2116 * dont wait a bit here, looks like the chip takes
2117 * some time to really shut down
2122 writel(0, gp
->regs
+ MAC_TXCFG
);
2123 writel(0, gp
->regs
+ MAC_XIFCFG
);
2124 writel(0, gp
->regs
+ TXDMA_CFG
);
2125 writel(0, gp
->regs
+ RXDMA_CFG
);
2129 writel(MAC_TXRST_CMD
, gp
->regs
+ MAC_TXRST
);
2130 writel(MAC_RXRST_CMD
, gp
->regs
+ MAC_RXRST
);
2132 if (found_mii_phy(gp
) && gp
->phy_mii
.def
->ops
->suspend
)
2133 gp
->phy_mii
.def
->ops
->suspend(&gp
->phy_mii
);
2135 /* According to Apple, we must set the MDIO pins to this begnign
2136 * state or we may 1) eat more current, 2) damage some PHYs
2138 writel(mifcfg
| MIF_CFG_BBMODE
, gp
->regs
+ MIF_CFG
);
2139 writel(0, gp
->regs
+ MIF_BBCLK
);
2140 writel(0, gp
->regs
+ MIF_BBDATA
);
2141 writel(0, gp
->regs
+ MIF_BBOENAB
);
2142 writel(MAC_XIFCFG_GMII
| MAC_XIFCFG_LBCK
, gp
->regs
+ MAC_XIFCFG
);
2143 (void) readl(gp
->regs
+ MAC_XIFCFG
);
2147 static int gem_do_start(struct net_device
*dev
)
2149 struct gem
*gp
= netdev_priv(dev
);
2152 /* Enable the cell */
2155 /* Make sure PCI access and bus master are enabled */
2156 rc
= pci_enable_device(gp
->pdev
);
2158 netdev_err(dev
, "Failed to enable chip on PCI bus !\n");
2160 /* Put cell and forget it for now, it will be considered as
2161 * still asleep, a new sleep cycle may bring it back
2166 pci_set_master(gp
->pdev
);
2168 /* Init & setup chip hardware */
2169 gem_reinit_chip(gp
);
2171 /* An interrupt might come in handy */
2172 rc
= request_irq(gp
->pdev
->irq
, gem_interrupt
,
2173 IRQF_SHARED
, dev
->name
, (void *)dev
);
2175 netdev_err(dev
, "failed to request irq !\n");
2178 gem_clean_rings(gp
);
2183 /* Mark us as attached again if we come from resume(), this has
2184 * no effect if we weren't detached and needs to be done now.
2186 netif_device_attach(dev
);
2188 /* Restart NAPI & queues */
2189 gem_netif_start(gp
);
2191 /* Detect & init PHY, start autoneg etc... this will
2192 * eventually result in starting DMA operations when
2200 static void gem_do_stop(struct net_device
*dev
, int wol
)
2202 struct gem
*gp
= netdev_priv(dev
);
2204 /* Stop NAPI and stop tx queue */
2207 /* Make sure ints are disabled. We don't care about
2208 * synchronizing as NAPI is disabled, thus a stray
2209 * interrupt will do nothing bad (our irq handler
2210 * just schedules NAPI)
2212 gem_disable_ints(gp
);
2214 /* Stop the link timer */
2215 del_timer_sync(&gp
->link_timer
);
2217 /* We cannot cancel the reset task while holding the
2218 * rtnl lock, we'd get an A->B / B->A deadlock stituation
2219 * if we did. This is not an issue however as the reset
2220 * task is synchronized vs. us (rtnl_lock) and will do
2221 * nothing if the device is down or suspended. We do
2222 * still clear reset_task_pending to avoid a spurrious
2223 * reset later on in case we do resume before it gets
2226 gp
->reset_task_pending
= 0;
2228 /* If we are going to sleep with WOL */
2235 /* Get rid of rings */
2236 gem_clean_rings(gp
);
2238 /* No irq needed anymore */
2239 free_irq(gp
->pdev
->irq
, (void *) dev
);
2241 /* Shut the PHY down eventually and setup WOL */
2242 gem_stop_phy(gp
, wol
);
2244 /* Make sure bus master is disabled */
2245 pci_disable_device(gp
->pdev
);
2247 /* Cell not needed neither if no WOL */
2252 static void gem_reset_task(struct work_struct
*work
)
2254 struct gem
*gp
= container_of(work
, struct gem
, reset_task
);
2256 /* Lock out the network stack (essentially shield ourselves
2257 * against a racing open, close, control call, or suspend
2261 /* Skip the reset task if suspended or closed, or if it's
2262 * been cancelled by gem_do_stop (see comment there)
2264 if (!netif_device_present(gp
->dev
) ||
2265 !netif_running(gp
->dev
) ||
2266 !gp
->reset_task_pending
) {
2271 /* Stop the link timer */
2272 del_timer_sync(&gp
->link_timer
);
2274 /* Stop NAPI and tx */
2277 /* Reset the chip & rings */
2278 gem_reinit_chip(gp
);
2279 if (gp
->lstate
== link_up
)
2280 gem_set_link_modes(gp
);
2282 /* Restart NAPI and Tx */
2283 gem_netif_start(gp
);
2286 gp
->reset_task_pending
= 0;
2288 /* If the link is not up, restart autoneg, else restart the
2291 if (gp
->lstate
!= link_up
)
2292 gem_begin_auto_negotiation(gp
, NULL
);
2294 mod_timer(&gp
->link_timer
, jiffies
+ ((12 * HZ
) / 10));
2299 static int gem_open(struct net_device
*dev
)
2301 /* We allow open while suspended, we just do nothing,
2302 * the chip will be initialized in resume()
2304 if (netif_device_present(dev
))
2305 return gem_do_start(dev
);
2309 static int gem_close(struct net_device
*dev
)
2311 if (netif_device_present(dev
))
2312 gem_do_stop(dev
, 0);
2318 static int gem_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2320 struct net_device
*dev
= pci_get_drvdata(pdev
);
2321 struct gem
*gp
= netdev_priv(dev
);
2323 /* Lock the network stack first to avoid racing with open/close,
2324 * reset task and setting calls
2328 /* Not running, mark ourselves non-present, no need for
2331 if (!netif_running(dev
)) {
2332 netif_device_detach(dev
);
2336 netdev_info(dev
, "suspending, WakeOnLan %s\n",
2337 (gp
->wake_on_lan
&& netif_running(dev
)) ?
2338 "enabled" : "disabled");
2340 /* Tell the network stack we're gone. gem_do_stop() below will
2341 * synchronize with TX, stop NAPI etc...
2343 netif_device_detach(dev
);
2345 /* Switch off chip, remember WOL setting */
2346 gp
->asleep_wol
= !!gp
->wake_on_lan
;
2347 gem_do_stop(dev
, gp
->asleep_wol
);
2349 /* Unlock the network stack */
2355 static int gem_resume(struct pci_dev
*pdev
)
2357 struct net_device
*dev
= pci_get_drvdata(pdev
);
2358 struct gem
*gp
= netdev_priv(dev
);
2360 /* See locking comment in gem_suspend */
2363 /* Not running, mark ourselves present, no need for
2366 if (!netif_running(dev
)) {
2367 netif_device_attach(dev
);
2372 /* Restart chip. If that fails there isn't much we can do, we
2373 * leave things stopped.
2377 /* If we had WOL enabled, the cell clock was never turned off during
2378 * sleep, so we end up beeing unbalanced. Fix that here
2383 /* Unlock the network stack */
2388 #endif /* CONFIG_PM */
2390 static struct net_device_stats
*gem_get_stats(struct net_device
*dev
)
2392 struct gem
*gp
= netdev_priv(dev
);
2394 /* I have seen this being called while the PM was in progress,
2395 * so we shield against this. Let's also not poke at registers
2396 * while the reset task is going on.
2398 * TODO: Move stats collection elsewhere (link timer ?) and
2399 * make this a nop to avoid all those synchro issues
2401 if (!netif_device_present(dev
) || !netif_running(dev
))
2404 /* Better safe than sorry... */
2405 if (WARN_ON(!gp
->cell_enabled
))
2408 dev
->stats
.rx_crc_errors
+= readl(gp
->regs
+ MAC_FCSERR
);
2409 writel(0, gp
->regs
+ MAC_FCSERR
);
2411 dev
->stats
.rx_frame_errors
+= readl(gp
->regs
+ MAC_AERR
);
2412 writel(0, gp
->regs
+ MAC_AERR
);
2414 dev
->stats
.rx_length_errors
+= readl(gp
->regs
+ MAC_LERR
);
2415 writel(0, gp
->regs
+ MAC_LERR
);
2417 dev
->stats
.tx_aborted_errors
+= readl(gp
->regs
+ MAC_ECOLL
);
2418 dev
->stats
.collisions
+=
2419 (readl(gp
->regs
+ MAC_ECOLL
) + readl(gp
->regs
+ MAC_LCOLL
));
2420 writel(0, gp
->regs
+ MAC_ECOLL
);
2421 writel(0, gp
->regs
+ MAC_LCOLL
);
2426 static int gem_set_mac_address(struct net_device
*dev
, void *addr
)
2428 struct sockaddr
*macaddr
= (struct sockaddr
*) addr
;
2429 struct gem
*gp
= netdev_priv(dev
);
2430 unsigned char *e
= &dev
->dev_addr
[0];
2432 if (!is_valid_ether_addr(macaddr
->sa_data
))
2433 return -EADDRNOTAVAIL
;
2435 memcpy(dev
->dev_addr
, macaddr
->sa_data
, dev
->addr_len
);
2437 /* We'll just catch it later when the device is up'd or resumed */
2438 if (!netif_running(dev
) || !netif_device_present(dev
))
2441 /* Better safe than sorry... */
2442 if (WARN_ON(!gp
->cell_enabled
))
2445 writel((e
[4] << 8) | e
[5], gp
->regs
+ MAC_ADDR0
);
2446 writel((e
[2] << 8) | e
[3], gp
->regs
+ MAC_ADDR1
);
2447 writel((e
[0] << 8) | e
[1], gp
->regs
+ MAC_ADDR2
);
2452 static void gem_set_multicast(struct net_device
*dev
)
2454 struct gem
*gp
= netdev_priv(dev
);
2455 u32 rxcfg
, rxcfg_new
;
2458 if (!netif_running(dev
) || !netif_device_present(dev
))
2461 /* Better safe than sorry... */
2462 if (gp
->reset_task_pending
|| WARN_ON(!gp
->cell_enabled
))
2465 rxcfg
= readl(gp
->regs
+ MAC_RXCFG
);
2466 rxcfg_new
= gem_setup_multicast(gp
);
2468 rxcfg_new
|= MAC_RXCFG_SFCS
;
2470 gp
->mac_rx_cfg
= rxcfg_new
;
2472 writel(rxcfg
& ~MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
2473 while (readl(gp
->regs
+ MAC_RXCFG
) & MAC_RXCFG_ENAB
) {
2479 rxcfg
&= ~(MAC_RXCFG_PROM
| MAC_RXCFG_HFE
);
2482 writel(rxcfg
, gp
->regs
+ MAC_RXCFG
);
2485 /* Jumbo-grams don't seem to work :-( */
2486 #define GEM_MIN_MTU ETH_MIN_MTU
2488 #define GEM_MAX_MTU ETH_DATA_LEN
2490 #define GEM_MAX_MTU 9000
2493 static int gem_change_mtu(struct net_device
*dev
, int new_mtu
)
2495 struct gem
*gp
= netdev_priv(dev
);
2499 /* We'll just catch it later when the device is up'd or resumed */
2500 if (!netif_running(dev
) || !netif_device_present(dev
))
2503 /* Better safe than sorry... */
2504 if (WARN_ON(!gp
->cell_enabled
))
2508 gem_reinit_chip(gp
);
2509 if (gp
->lstate
== link_up
)
2510 gem_set_link_modes(gp
);
2511 gem_netif_start(gp
);
2516 static void gem_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
2518 struct gem
*gp
= netdev_priv(dev
);
2520 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
2521 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
2522 strlcpy(info
->bus_info
, pci_name(gp
->pdev
), sizeof(info
->bus_info
));
2525 static int gem_get_link_ksettings(struct net_device
*dev
,
2526 struct ethtool_link_ksettings
*cmd
)
2528 struct gem
*gp
= netdev_priv(dev
);
2529 u32 supported
, advertising
;
2531 if (gp
->phy_type
== phy_mii_mdio0
||
2532 gp
->phy_type
== phy_mii_mdio1
) {
2533 if (gp
->phy_mii
.def
)
2534 supported
= gp
->phy_mii
.def
->features
;
2536 supported
= (SUPPORTED_10baseT_Half
|
2537 SUPPORTED_10baseT_Full
);
2539 /* XXX hardcoded stuff for now */
2540 cmd
->base
.port
= PORT_MII
;
2541 cmd
->base
.phy_address
= 0; /* XXX fixed PHYAD */
2543 /* Return current PHY settings */
2544 cmd
->base
.autoneg
= gp
->want_autoneg
;
2545 cmd
->base
.speed
= gp
->phy_mii
.speed
;
2546 cmd
->base
.duplex
= gp
->phy_mii
.duplex
;
2547 advertising
= gp
->phy_mii
.advertising
;
2549 /* If we started with a forced mode, we don't have a default
2550 * advertise set, we need to return something sensible so
2551 * userland can re-enable autoneg properly.
2553 if (advertising
== 0)
2554 advertising
= supported
;
2555 } else { // XXX PCS ?
2557 (SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
2558 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
2560 advertising
= supported
;
2561 cmd
->base
.speed
= 0;
2562 cmd
->base
.duplex
= 0;
2564 cmd
->base
.phy_address
= 0;
2565 cmd
->base
.autoneg
= 0;
2567 /* serdes means usually a Fibre connector, with most fixed */
2568 if (gp
->phy_type
== phy_serdes
) {
2569 cmd
->base
.port
= PORT_FIBRE
;
2570 supported
= (SUPPORTED_1000baseT_Half
|
2571 SUPPORTED_1000baseT_Full
|
2572 SUPPORTED_FIBRE
| SUPPORTED_Autoneg
|
2573 SUPPORTED_Pause
| SUPPORTED_Asym_Pause
);
2574 advertising
= supported
;
2575 if (gp
->lstate
== link_up
)
2576 cmd
->base
.speed
= SPEED_1000
;
2577 cmd
->base
.duplex
= DUPLEX_FULL
;
2578 cmd
->base
.autoneg
= 1;
2582 ethtool_convert_legacy_u32_to_link_mode(cmd
->link_modes
.supported
,
2584 ethtool_convert_legacy_u32_to_link_mode(cmd
->link_modes
.advertising
,
2590 static int gem_set_link_ksettings(struct net_device
*dev
,
2591 const struct ethtool_link_ksettings
*cmd
)
2593 struct gem
*gp
= netdev_priv(dev
);
2594 u32 speed
= cmd
->base
.speed
;
2597 ethtool_convert_link_mode_to_legacy_u32(&advertising
,
2598 cmd
->link_modes
.advertising
);
2600 /* Verify the settings we care about. */
2601 if (cmd
->base
.autoneg
!= AUTONEG_ENABLE
&&
2602 cmd
->base
.autoneg
!= AUTONEG_DISABLE
)
2605 if (cmd
->base
.autoneg
== AUTONEG_ENABLE
&&
2609 if (cmd
->base
.autoneg
== AUTONEG_DISABLE
&&
2610 ((speed
!= SPEED_1000
&&
2611 speed
!= SPEED_100
&&
2612 speed
!= SPEED_10
) ||
2613 (cmd
->base
.duplex
!= DUPLEX_HALF
&&
2614 cmd
->base
.duplex
!= DUPLEX_FULL
)))
2617 /* Apply settings and restart link process. */
2618 if (netif_device_present(gp
->dev
)) {
2619 del_timer_sync(&gp
->link_timer
);
2620 gem_begin_auto_negotiation(gp
, cmd
);
2626 static int gem_nway_reset(struct net_device
*dev
)
2628 struct gem
*gp
= netdev_priv(dev
);
2630 if (!gp
->want_autoneg
)
2633 /* Restart link process */
2634 if (netif_device_present(gp
->dev
)) {
2635 del_timer_sync(&gp
->link_timer
);
2636 gem_begin_auto_negotiation(gp
, NULL
);
2642 static u32
gem_get_msglevel(struct net_device
*dev
)
2644 struct gem
*gp
= netdev_priv(dev
);
2645 return gp
->msg_enable
;
2648 static void gem_set_msglevel(struct net_device
*dev
, u32 value
)
2650 struct gem
*gp
= netdev_priv(dev
);
2651 gp
->msg_enable
= value
;
2655 /* Add more when I understand how to program the chip */
2656 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2658 #define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2660 static void gem_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2662 struct gem
*gp
= netdev_priv(dev
);
2664 /* Add more when I understand how to program the chip */
2666 wol
->supported
= WOL_SUPPORTED_MASK
;
2667 wol
->wolopts
= gp
->wake_on_lan
;
2674 static int gem_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2676 struct gem
*gp
= netdev_priv(dev
);
2680 gp
->wake_on_lan
= wol
->wolopts
& WOL_SUPPORTED_MASK
;
2684 static const struct ethtool_ops gem_ethtool_ops
= {
2685 .get_drvinfo
= gem_get_drvinfo
,
2686 .get_link
= ethtool_op_get_link
,
2687 .nway_reset
= gem_nway_reset
,
2688 .get_msglevel
= gem_get_msglevel
,
2689 .set_msglevel
= gem_set_msglevel
,
2690 .get_wol
= gem_get_wol
,
2691 .set_wol
= gem_set_wol
,
2692 .get_link_ksettings
= gem_get_link_ksettings
,
2693 .set_link_ksettings
= gem_set_link_ksettings
,
2696 static int gem_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2698 struct gem
*gp
= netdev_priv(dev
);
2699 struct mii_ioctl_data
*data
= if_mii(ifr
);
2700 int rc
= -EOPNOTSUPP
;
2702 /* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that
2703 * netif_device_present() is true and holds rtnl_lock for us
2704 * so we have nothing to worry about
2708 case SIOCGMIIPHY
: /* Get address of MII PHY in use. */
2709 data
->phy_id
= gp
->mii_phy_addr
;
2710 /* Fallthrough... */
2712 case SIOCGMIIREG
: /* Read MII PHY register. */
2713 data
->val_out
= __sungem_phy_read(gp
, data
->phy_id
& 0x1f,
2714 data
->reg_num
& 0x1f);
2718 case SIOCSMIIREG
: /* Write MII PHY register. */
2719 __sungem_phy_write(gp
, data
->phy_id
& 0x1f, data
->reg_num
& 0x1f,
2727 #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2728 /* Fetch MAC address from vital product data of PCI ROM. */
2729 static int find_eth_addr_in_vpd(void __iomem
*rom_base
, int len
, unsigned char *dev_addr
)
2733 for (this_offset
= 0x20; this_offset
< len
; this_offset
++) {
2734 void __iomem
*p
= rom_base
+ this_offset
;
2737 if (readb(p
+ 0) != 0x90 ||
2738 readb(p
+ 1) != 0x00 ||
2739 readb(p
+ 2) != 0x09 ||
2740 readb(p
+ 3) != 0x4e ||
2741 readb(p
+ 4) != 0x41 ||
2742 readb(p
+ 5) != 0x06)
2748 for (i
= 0; i
< 6; i
++)
2749 dev_addr
[i
] = readb(p
+ i
);
2755 static void get_gem_mac_nonobp(struct pci_dev
*pdev
, unsigned char *dev_addr
)
2758 void __iomem
*p
= pci_map_rom(pdev
, &size
);
2763 found
= readb(p
) == 0x55 &&
2764 readb(p
+ 1) == 0xaa &&
2765 find_eth_addr_in_vpd(p
, (64 * 1024), dev_addr
);
2766 pci_unmap_rom(pdev
, p
);
2771 /* Sun MAC prefix then 3 random bytes. */
2775 get_random_bytes(dev_addr
+ 3, 3);
2777 #endif /* not Sparc and not PPC */
2779 static int gem_get_device_address(struct gem
*gp
)
2781 #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2782 struct net_device
*dev
= gp
->dev
;
2783 const unsigned char *addr
;
2785 addr
= of_get_property(gp
->of_node
, "local-mac-address", NULL
);
2788 addr
= idprom
->id_ethaddr
;
2791 pr_err("%s: can't get mac-address\n", dev
->name
);
2795 memcpy(dev
->dev_addr
, addr
, ETH_ALEN
);
2797 get_gem_mac_nonobp(gp
->pdev
, gp
->dev
->dev_addr
);
2802 static void gem_remove_one(struct pci_dev
*pdev
)
2804 struct net_device
*dev
= pci_get_drvdata(pdev
);
2807 struct gem
*gp
= netdev_priv(dev
);
2809 unregister_netdev(dev
);
2811 /* Ensure reset task is truly gone */
2812 cancel_work_sync(&gp
->reset_task
);
2814 /* Free resources */
2815 pci_free_consistent(pdev
,
2816 sizeof(struct gem_init_block
),
2820 pci_release_regions(pdev
);
2825 static const struct net_device_ops gem_netdev_ops
= {
2826 .ndo_open
= gem_open
,
2827 .ndo_stop
= gem_close
,
2828 .ndo_start_xmit
= gem_start_xmit
,
2829 .ndo_get_stats
= gem_get_stats
,
2830 .ndo_set_rx_mode
= gem_set_multicast
,
2831 .ndo_do_ioctl
= gem_ioctl
,
2832 .ndo_tx_timeout
= gem_tx_timeout
,
2833 .ndo_change_mtu
= gem_change_mtu
,
2834 .ndo_validate_addr
= eth_validate_addr
,
2835 .ndo_set_mac_address
= gem_set_mac_address
,
2836 #ifdef CONFIG_NET_POLL_CONTROLLER
2837 .ndo_poll_controller
= gem_poll_controller
,
2841 static int gem_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
2843 unsigned long gemreg_base
, gemreg_len
;
2844 struct net_device
*dev
;
2846 int err
, pci_using_dac
;
2848 printk_once(KERN_INFO
"%s", version
);
2850 /* Apple gmac note: during probe, the chip is powered up by
2851 * the arch code to allow the code below to work (and to let
2852 * the chip be probed on the config space. It won't stay powered
2853 * up until the interface is brought up however, so we can't rely
2854 * on register configuration done at this point.
2856 err
= pci_enable_device(pdev
);
2858 pr_err("Cannot enable MMIO operation, aborting\n");
2861 pci_set_master(pdev
);
2863 /* Configure DMA attributes. */
2865 /* All of the GEM documentation states that 64-bit DMA addressing
2866 * is fully supported and should work just fine. However the
2867 * front end for RIO based GEMs is different and only supports
2868 * 32-bit addressing.
2870 * For now we assume the various PPC GEMs are 32-bit only as well.
2872 if (pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
2873 pdev
->device
== PCI_DEVICE_ID_SUN_GEM
&&
2874 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64))) {
2877 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2879 pr_err("No usable DMA configuration, aborting\n");
2880 goto err_disable_device
;
2885 gemreg_base
= pci_resource_start(pdev
, 0);
2886 gemreg_len
= pci_resource_len(pdev
, 0);
2888 if ((pci_resource_flags(pdev
, 0) & IORESOURCE_IO
) != 0) {
2889 pr_err("Cannot find proper PCI device base address, aborting\n");
2891 goto err_disable_device
;
2894 dev
= alloc_etherdev(sizeof(*gp
));
2897 goto err_disable_device
;
2899 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2901 gp
= netdev_priv(dev
);
2903 err
= pci_request_regions(pdev
, DRV_NAME
);
2905 pr_err("Cannot obtain PCI resources, aborting\n");
2906 goto err_out_free_netdev
;
2912 gp
->msg_enable
= DEFAULT_MSG
;
2914 timer_setup(&gp
->link_timer
, gem_link_timer
, 0);
2916 INIT_WORK(&gp
->reset_task
, gem_reset_task
);
2918 gp
->lstate
= link_down
;
2919 gp
->timer_ticks
= 0;
2920 netif_carrier_off(dev
);
2922 gp
->regs
= ioremap(gemreg_base
, gemreg_len
);
2924 pr_err("Cannot map device registers, aborting\n");
2926 goto err_out_free_res
;
2929 /* On Apple, we want a reference to the Open Firmware device-tree
2930 * node. We use it for clock control.
2932 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
2933 gp
->of_node
= pci_device_to_OF_node(pdev
);
2936 /* Only Apple version supports WOL afaik */
2937 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
)
2940 /* Make sure cell is enabled */
2943 /* Make sure everything is stopped and in init state */
2946 /* Fill up the mii_phy structure (even if we won't use it) */
2947 gp
->phy_mii
.dev
= dev
;
2948 gp
->phy_mii
.mdio_read
= _sungem_phy_read
;
2949 gp
->phy_mii
.mdio_write
= _sungem_phy_write
;
2950 #ifdef CONFIG_PPC_PMAC
2951 gp
->phy_mii
.platform_data
= gp
->of_node
;
2953 /* By default, we start with autoneg */
2954 gp
->want_autoneg
= 1;
2956 /* Check fifo sizes, PHY type, etc... */
2957 if (gem_check_invariants(gp
)) {
2959 goto err_out_iounmap
;
2962 /* It is guaranteed that the returned buffer will be at least
2963 * PAGE_SIZE aligned.
2965 gp
->init_block
= (struct gem_init_block
*)
2966 pci_alloc_consistent(pdev
, sizeof(struct gem_init_block
),
2968 if (!gp
->init_block
) {
2969 pr_err("Cannot allocate init block, aborting\n");
2971 goto err_out_iounmap
;
2974 err
= gem_get_device_address(gp
);
2976 goto err_out_free_consistent
;
2978 dev
->netdev_ops
= &gem_netdev_ops
;
2979 netif_napi_add(dev
, &gp
->napi
, gem_poll
, 64);
2980 dev
->ethtool_ops
= &gem_ethtool_ops
;
2981 dev
->watchdog_timeo
= 5 * HZ
;
2984 /* Set that now, in case PM kicks in now */
2985 pci_set_drvdata(pdev
, dev
);
2987 /* We can do scatter/gather and HW checksum */
2988 dev
->hw_features
= NETIF_F_SG
| NETIF_F_HW_CSUM
;
2989 dev
->features
|= dev
->hw_features
| NETIF_F_RXCSUM
;
2991 dev
->features
|= NETIF_F_HIGHDMA
;
2993 /* MTU range: 68 - 1500 (Jumbo mode is broken) */
2994 dev
->min_mtu
= GEM_MIN_MTU
;
2995 dev
->max_mtu
= GEM_MAX_MTU
;
2997 /* Register with kernel */
2998 if (register_netdev(dev
)) {
2999 pr_err("Cannot register net device, aborting\n");
3001 goto err_out_free_consistent
;
3004 /* Undo the get_cell with appropriate locking (we could use
3005 * ndo_init/uninit but that would be even more clumsy imho)
3011 netdev_info(dev
, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3015 err_out_free_consistent
:
3016 gem_remove_one(pdev
);
3022 pci_release_regions(pdev
);
3024 err_out_free_netdev
:
3027 pci_disable_device(pdev
);
3033 static struct pci_driver gem_driver
= {
3034 .name
= GEM_MODULE_NAME
,
3035 .id_table
= gem_pci_tbl
,
3036 .probe
= gem_init_one
,
3037 .remove
= gem_remove_one
,
3039 .suspend
= gem_suspend
,
3040 .resume
= gem_resume
,
3041 #endif /* CONFIG_PM */
3044 module_pci_driver(gem_driver
);