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Linux 4.16.11
[linux/fpc-iii.git] / drivers / net / ethernet / ti / cpsw.c
blob5490c7d09c168dded546ba1000c7a61247e5053f
1 /*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio.h>
33 #include <linux/of.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
38
39 #include <linux/pinctrl/consumer.h>
40
41 #include "cpsw.h"
42 #include "cpsw_ale.h"
43 #include "cpts.h"
44 #include "davinci_cpdma.h"
45
46 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55 #define cpsw_info(priv, type, format, ...) \
56 do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59 } while (0)
60
61 #define cpsw_err(priv, type, format, ...) \
62 do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65 } while (0)
66
67 #define cpsw_dbg(priv, type, format, ...) \
68 do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71 } while (0)
72
73 #define cpsw_notice(priv, type, format, ...) \
74 do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77 } while (0)
78
79 #define ALE_ALL_PORTS 0x7
80
81 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
85 #define CPSW_VERSION_1 0x19010a
86 #define CPSW_VERSION_2 0x19010c
87 #define CPSW_VERSION_3 0x19010f
88 #define CPSW_VERSION_4 0x190112
89
90 #define HOST_PORT_NUM 0
91 #define CPSW_ALE_PORTS_NUM 3
92 #define SLIVER_SIZE 0x40
93
94 #define CPSW1_HOST_PORT_OFFSET 0x028
95 #define CPSW1_SLAVE_OFFSET 0x050
96 #define CPSW1_SLAVE_SIZE 0x040
97 #define CPSW1_CPDMA_OFFSET 0x100
98 #define CPSW1_STATERAM_OFFSET 0x200
99 #define CPSW1_HW_STATS 0x400
100 #define CPSW1_CPTS_OFFSET 0x500
101 #define CPSW1_ALE_OFFSET 0x600
102 #define CPSW1_SLIVER_OFFSET 0x700
103
104 #define CPSW2_HOST_PORT_OFFSET 0x108
105 #define CPSW2_SLAVE_OFFSET 0x200
106 #define CPSW2_SLAVE_SIZE 0x100
107 #define CPSW2_CPDMA_OFFSET 0x800
108 #define CPSW2_HW_STATS 0x900
109 #define CPSW2_STATERAM_OFFSET 0xa00
110 #define CPSW2_CPTS_OFFSET 0xc00
111 #define CPSW2_ALE_OFFSET 0xd00
112 #define CPSW2_SLIVER_OFFSET 0xd80
113 #define CPSW2_BD_OFFSET 0x2000
114
115 #define CPDMA_RXTHRESH 0x0c0
116 #define CPDMA_RXFREE 0x0e0
117 #define CPDMA_TXHDP 0x00
118 #define CPDMA_RXHDP 0x20
119 #define CPDMA_TXCP 0x40
120 #define CPDMA_RXCP 0x60
121
122 #define CPSW_POLL_WEIGHT 64
123 #define CPSW_MIN_PACKET_SIZE (VLAN_ETH_ZLEN)
124 #define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
125
126 #define RX_PRIORITY_MAPPING 0x76543210
127 #define TX_PRIORITY_MAPPING 0x33221100
128 #define CPDMA_TX_PRIORITY_MAP 0x76543210
129
130 #define CPSW_VLAN_AWARE BIT(1)
131 #define CPSW_ALE_VLAN_AWARE 1
132
133 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
134 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
135 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
136
137 #define CPSW_INTPACEEN (0x3f << 16)
138 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
139 #define CPSW_CMINTMAX_CNT 63
140 #define CPSW_CMINTMIN_CNT 2
141 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
142 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
143
144 #define cpsw_slave_index(cpsw, priv) \
145 ((cpsw->data.dual_emac) ? priv->emac_port : \
146 cpsw->data.active_slave)
147 #define IRQ_NUM 2
148 #define CPSW_MAX_QUEUES 8
149 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
150
151 static int debug_level;
152 module_param(debug_level, int, 0);
153 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
154
155 static int ale_ageout = 10;
156 module_param(ale_ageout, int, 0);
157 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
158
159 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
160 module_param(rx_packet_max, int, 0);
161 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
162
163 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
164 module_param(descs_pool_size, int, 0444);
165 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
166
167 struct cpsw_wr_regs {
168 u32 id_ver;
169 u32 soft_reset;
170 u32 control;
171 u32 int_control;
172 u32 rx_thresh_en;
173 u32 rx_en;
174 u32 tx_en;
175 u32 misc_en;
176 u32 mem_allign1[8];
177 u32 rx_thresh_stat;
178 u32 rx_stat;
179 u32 tx_stat;
180 u32 misc_stat;
181 u32 mem_allign2[8];
182 u32 rx_imax;
183 u32 tx_imax;
184
185 };
186
187 struct cpsw_ss_regs {
188 u32 id_ver;
189 u32 control;
190 u32 soft_reset;
191 u32 stat_port_en;
192 u32 ptype;
193 u32 soft_idle;
194 u32 thru_rate;
195 u32 gap_thresh;
196 u32 tx_start_wds;
197 u32 flow_control;
198 u32 vlan_ltype;
199 u32 ts_ltype;
200 u32 dlr_ltype;
201 };
202
203 /* CPSW_PORT_V1 */
204 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
205 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
206 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
207 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
208 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
209 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
210 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
211 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
212
213 /* CPSW_PORT_V2 */
214 #define CPSW2_CONTROL 0x00 /* Control Register */
215 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
216 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
217 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
218 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
219 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
220 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
221
222 /* CPSW_PORT_V1 and V2 */
223 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
224 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
225 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
226
227 /* CPSW_PORT_V2 only */
228 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
229 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
230 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
231 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
232 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
233 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
234 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
235 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
236
237 /* Bit definitions for the CPSW2_CONTROL register */
238 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
239 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
240 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
241 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
242 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
243 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
244 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
245 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
246 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
247 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
248 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
249 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
250 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
251 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
252 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
253 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
254 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
255
256 #define CTRL_V2_TS_BITS \
257 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
258 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
259
260 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
261 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
262 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
263
264
265 #define CTRL_V3_TS_BITS \
266 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
267 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
268 TS_LTYPE1_EN)
269
270 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
271 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
272 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
273
274 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
275 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
276 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
277 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
278 #define TS_MSG_TYPE_EN_MASK (0xffff)
279
280 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
281 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
282
283 /* Bit definitions for the CPSW1_TS_CTL register */
284 #define CPSW_V1_TS_RX_EN BIT(0)
285 #define CPSW_V1_TS_TX_EN BIT(4)
286 #define CPSW_V1_MSG_TYPE_OFS 16
287
288 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
289 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
290
291 #define CPSW_MAX_BLKS_TX 15
292 #define CPSW_MAX_BLKS_TX_SHIFT 4
293 #define CPSW_MAX_BLKS_RX 5
294
295 struct cpsw_host_regs {
296 u32 max_blks;
297 u32 blk_cnt;
298 u32 tx_in_ctl;
299 u32 port_vlan;
300 u32 tx_pri_map;
301 u32 cpdma_tx_pri_map;
302 u32 cpdma_rx_chan_map;
303 };
304
305 struct cpsw_sliver_regs {
306 u32 id_ver;
307 u32 mac_control;
308 u32 mac_status;
309 u32 soft_reset;
310 u32 rx_maxlen;
311 u32 __reserved_0;
312 u32 rx_pause;
313 u32 tx_pause;
314 u32 __reserved_1;
315 u32 rx_pri_map;
316 };
317
318 struct cpsw_hw_stats {
319 u32 rxgoodframes;
320 u32 rxbroadcastframes;
321 u32 rxmulticastframes;
322 u32 rxpauseframes;
323 u32 rxcrcerrors;
324 u32 rxaligncodeerrors;
325 u32 rxoversizedframes;
326 u32 rxjabberframes;
327 u32 rxundersizedframes;
328 u32 rxfragments;
329 u32 __pad_0[2];
330 u32 rxoctets;
331 u32 txgoodframes;
332 u32 txbroadcastframes;
333 u32 txmulticastframes;
334 u32 txpauseframes;
335 u32 txdeferredframes;
336 u32 txcollisionframes;
337 u32 txsinglecollframes;
338 u32 txmultcollframes;
339 u32 txexcessivecollisions;
340 u32 txlatecollisions;
341 u32 txunderrun;
342 u32 txcarriersenseerrors;
343 u32 txoctets;
344 u32 octetframes64;
345 u32 octetframes65t127;
346 u32 octetframes128t255;
347 u32 octetframes256t511;
348 u32 octetframes512t1023;
349 u32 octetframes1024tup;
350 u32 netoctets;
351 u32 rxsofoverruns;
352 u32 rxmofoverruns;
353 u32 rxdmaoverruns;
354 };
355
356 struct cpsw_slave_data {
357 struct device_node *phy_node;
358 char phy_id[MII_BUS_ID_SIZE];
359 int phy_if;
360 u8 mac_addr[ETH_ALEN];
361 u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */
362 };
363
364 struct cpsw_platform_data {
365 struct cpsw_slave_data *slave_data;
366 u32 ss_reg_ofs; /* Subsystem control register offset */
367 u32 channels; /* number of cpdma channels (symmetric) */
368 u32 slaves; /* number of slave cpgmac ports */
369 u32 active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
370 u32 ale_entries; /* ale table size */
371 u32 bd_ram_size; /*buffer descriptor ram size */
372 u32 mac_control; /* Mac control register */
373 u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/
374 bool dual_emac; /* Enable Dual EMAC mode */
375 };
376
377 struct cpsw_slave {
378 void __iomem *regs;
379 struct cpsw_sliver_regs __iomem *sliver;
380 int slave_num;
381 u32 mac_control;
382 struct cpsw_slave_data *data;
383 struct phy_device *phy;
384 struct net_device *ndev;
385 u32 port_vlan;
386 };
387
388 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
389 {
390 return readl_relaxed(slave->regs + offset);
391 }
392
393 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
394 {
395 writel_relaxed(val, slave->regs + offset);
396 }
397
398 struct cpsw_vector {
399 struct cpdma_chan *ch;
400 int budget;
401 };
402
403 struct cpsw_common {
404 struct device *dev;
405 struct cpsw_platform_data data;
406 struct napi_struct napi_rx;
407 struct napi_struct napi_tx;
408 struct cpsw_ss_regs __iomem *regs;
409 struct cpsw_wr_regs __iomem *wr_regs;
410 u8 __iomem *hw_stats;
411 struct cpsw_host_regs __iomem *host_port_regs;
412 u32 version;
413 u32 coal_intvl;
414 u32 bus_freq_mhz;
415 int rx_packet_max;
416 struct cpsw_slave *slaves;
417 struct cpdma_ctlr *dma;
418 struct cpsw_vector txv[CPSW_MAX_QUEUES];
419 struct cpsw_vector rxv[CPSW_MAX_QUEUES];
420 struct cpsw_ale *ale;
421 bool quirk_irq;
422 bool rx_irq_disabled;
423 bool tx_irq_disabled;
424 u32 irqs_table[IRQ_NUM];
425 struct cpts *cpts;
426 int rx_ch_num, tx_ch_num;
427 int speed;
428 int usage_count;
429 };
430
431 struct cpsw_priv {
432 struct net_device *ndev;
433 struct device *dev;
434 u32 msg_enable;
435 u8 mac_addr[ETH_ALEN];
436 bool rx_pause;
437 bool tx_pause;
438 u32 emac_port;
439 struct cpsw_common *cpsw;
440 };
441
442 struct cpsw_stats {
443 char stat_string[ETH_GSTRING_LEN];
444 int type;
445 int sizeof_stat;
446 int stat_offset;
447 };
448
449 enum {
450 CPSW_STATS,
451 CPDMA_RX_STATS,
452 CPDMA_TX_STATS,
453 };
454
455 #define CPSW_STAT(m) CPSW_STATS, \
456 sizeof(((struct cpsw_hw_stats *)0)->m), \
457 offsetof(struct cpsw_hw_stats, m)
458 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
459 sizeof(((struct cpdma_chan_stats *)0)->m), \
460 offsetof(struct cpdma_chan_stats, m)
461 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
462 sizeof(((struct cpdma_chan_stats *)0)->m), \
463 offsetof(struct cpdma_chan_stats, m)
464
465 static const struct cpsw_stats cpsw_gstrings_stats[] = {
466 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
467 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
468 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
469 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
470 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
471 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
472 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
473 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
474 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
475 { "Rx Fragments", CPSW_STAT(rxfragments) },
476 { "Rx Octets", CPSW_STAT(rxoctets) },
477 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
478 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
479 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
480 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
481 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
482 { "Collisions", CPSW_STAT(txcollisionframes) },
483 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
484 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
485 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
486 { "Late Collisions", CPSW_STAT(txlatecollisions) },
487 { "Tx Underrun", CPSW_STAT(txunderrun) },
488 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
489 { "Tx Octets", CPSW_STAT(txoctets) },
490 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
491 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
492 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
493 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
494 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
495 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
496 { "Net Octets", CPSW_STAT(netoctets) },
497 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
498 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
499 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
500 };
501
502 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
503 { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
504 { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
505 { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
506 { "misqueued", CPDMA_RX_STAT(misqueued) },
507 { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
508 { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
509 { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
510 { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
511 { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
512 { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
513 { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
514 { "requeue", CPDMA_RX_STAT(requeue) },
515 { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
516 };
517
518 #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats)
519 #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats)
520
521 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
522 #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
523 #define for_each_slave(priv, func, arg...) \
524 do { \
525 struct cpsw_slave *slave; \
526 struct cpsw_common *cpsw = (priv)->cpsw; \
527 int n; \
528 if (cpsw->data.dual_emac) \
529 (func)((cpsw)->slaves + priv->emac_port, ##arg);\
530 else \
531 for (n = cpsw->data.slaves, \
532 slave = cpsw->slaves; \
533 n; n--) \
534 (func)(slave++, ##arg); \
535 } while (0)
536
537 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \
538 do { \
539 if (!cpsw->data.dual_emac) \
540 break; \
541 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
542 ndev = cpsw->slaves[0].ndev; \
543 skb->dev = ndev; \
544 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
545 ndev = cpsw->slaves[1].ndev; \
546 skb->dev = ndev; \
547 } \
548 } while (0)
549 #define cpsw_add_mcast(cpsw, priv, addr) \
550 do { \
551 if (cpsw->data.dual_emac) { \
552 struct cpsw_slave *slave = cpsw->slaves + \
553 priv->emac_port; \
554 int slave_port = cpsw_get_slave_port( \
555 slave->slave_num); \
556 cpsw_ale_add_mcast(cpsw->ale, addr, \
557 1 << slave_port | ALE_PORT_HOST, \
558 ALE_VLAN, slave->port_vlan, 0); \
559 } else { \
560 cpsw_ale_add_mcast(cpsw->ale, addr, \
561 ALE_ALL_PORTS, \
562 0, 0, 0); \
563 } \
564 } while (0)
565
566 static inline int cpsw_get_slave_port(u32 slave_num)
567 {
568 return slave_num + 1;
569 }
570
571 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
572 {
573 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
574 struct cpsw_ale *ale = cpsw->ale;
575 int i;
576
577 if (cpsw->data.dual_emac) {
578 bool flag = false;
579
580 /* Enabling promiscuous mode for one interface will be
581 * common for both the interface as the interface shares
582 * the same hardware resource.
583 */
584 for (i = 0; i < cpsw->data.slaves; i++)
585 if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
586 flag = true;
587
588 if (!enable && flag) {
589 enable = true;
590 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
591 }
592
593 if (enable) {
594 /* Enable Bypass */
595 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
596
597 dev_dbg(&ndev->dev, "promiscuity enabled\n");
598 } else {
599 /* Disable Bypass */
600 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
601 dev_dbg(&ndev->dev, "promiscuity disabled\n");
602 }
603 } else {
604 if (enable) {
605 unsigned long timeout = jiffies + HZ;
606
607 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
608 for (i = 0; i <= cpsw->data.slaves; i++) {
609 cpsw_ale_control_set(ale, i,
610 ALE_PORT_NOLEARN, 1);
611 cpsw_ale_control_set(ale, i,
612 ALE_PORT_NO_SA_UPDATE, 1);
613 }
614
615 /* Clear All Untouched entries */
616 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
617 do {
618 cpu_relax();
619 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
620 break;
621 } while (time_after(timeout, jiffies));
622 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
623
624 /* Clear all mcast from ALE */
625 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
626
627 /* Flood All Unicast Packets to Host port */
628 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
629 dev_dbg(&ndev->dev, "promiscuity enabled\n");
630 } else {
631 /* Don't Flood All Unicast Packets to Host port */
632 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
633
634 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
635 for (i = 0; i <= cpsw->data.slaves; i++) {
636 cpsw_ale_control_set(ale, i,
637 ALE_PORT_NOLEARN, 0);
638 cpsw_ale_control_set(ale, i,
639 ALE_PORT_NO_SA_UPDATE, 0);
640 }
641 dev_dbg(&ndev->dev, "promiscuity disabled\n");
642 }
643 }
644 }
645
646 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
647 {
648 struct cpsw_priv *priv = netdev_priv(ndev);
649 struct cpsw_common *cpsw = priv->cpsw;
650 int vid;
651
652 if (cpsw->data.dual_emac)
653 vid = cpsw->slaves[priv->emac_port].port_vlan;
654 else
655 vid = cpsw->data.default_vlan;
656
657 if (ndev->flags & IFF_PROMISC) {
658 /* Enable promiscuous mode */
659 cpsw_set_promiscious(ndev, true);
660 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
661 return;
662 } else {
663 /* Disable promiscuous mode */
664 cpsw_set_promiscious(ndev, false);
665 }
666
667 /* Restore allmulti on vlans if necessary */
668 cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
669
670 /* Clear all mcast from ALE */
671 cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
672
673 if (!netdev_mc_empty(ndev)) {
674 struct netdev_hw_addr *ha;
675
676 /* program multicast address list into ALE register */
677 netdev_for_each_mc_addr(ha, ndev) {
678 cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
679 }
680 }
681 }
682
683 static void cpsw_intr_enable(struct cpsw_common *cpsw)
684 {
685 writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
686 writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
687
688 cpdma_ctlr_int_ctrl(cpsw->dma, true);
689 return;
690 }
691
692 static void cpsw_intr_disable(struct cpsw_common *cpsw)
693 {
694 writel_relaxed(0, &cpsw->wr_regs->tx_en);
695 writel_relaxed(0, &cpsw->wr_regs->rx_en);
696
697 cpdma_ctlr_int_ctrl(cpsw->dma, false);
698 return;
699 }
700
701 static void cpsw_tx_handler(void *token, int len, int status)
702 {
703 struct netdev_queue *txq;
704 struct sk_buff *skb = token;
705 struct net_device *ndev = skb->dev;
706 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
707
708 /* Check whether the queue is stopped due to stalled tx dma, if the
709 * queue is stopped then start the queue as we have free desc for tx
710 */
711 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
712 if (unlikely(netif_tx_queue_stopped(txq)))
713 netif_tx_wake_queue(txq);
714
715 cpts_tx_timestamp(cpsw->cpts, skb);
716 ndev->stats.tx_packets++;
717 ndev->stats.tx_bytes += len;
718 dev_kfree_skb_any(skb);
719 }
720
721 static void cpsw_rx_handler(void *token, int len, int status)
722 {
723 struct cpdma_chan *ch;
724 struct sk_buff *skb = token;
725 struct sk_buff *new_skb;
726 struct net_device *ndev = skb->dev;
727 int ret = 0;
728 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
729
730 cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
731
732 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
733 /* In dual emac mode check for all interfaces */
734 if (cpsw->data.dual_emac && cpsw->usage_count &&
735 (status >= 0)) {
736 /* The packet received is for the interface which
737 * is already down and the other interface is up
738 * and running, instead of freeing which results
739 * in reducing of the number of rx descriptor in
740 * DMA engine, requeue skb back to cpdma.
741 */
742 new_skb = skb;
743 goto requeue;
744 }
745
746 /* the interface is going down, skbs are purged */
747 dev_kfree_skb_any(skb);
748 return;
749 }
750
751 new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
752 if (new_skb) {
753 skb_copy_queue_mapping(new_skb, skb);
754 skb_put(skb, len);
755 cpts_rx_timestamp(cpsw->cpts, skb);
756 skb->protocol = eth_type_trans(skb, ndev);
757 netif_receive_skb(skb);
758 ndev->stats.rx_bytes += len;
759 ndev->stats.rx_packets++;
760 kmemleak_not_leak(new_skb);
761 } else {
762 ndev->stats.rx_dropped++;
763 new_skb = skb;
764 }
765
766 requeue:
767 if (netif_dormant(ndev)) {
768 dev_kfree_skb_any(new_skb);
769 return;
770 }
771
772 ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
773 ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
774 skb_tailroom(new_skb), 0);
775 if (WARN_ON(ret < 0))
776 dev_kfree_skb_any(new_skb);
777 }
778
779 static void cpsw_split_res(struct net_device *ndev)
780 {
781 struct cpsw_priv *priv = netdev_priv(ndev);
782 u32 consumed_rate = 0, bigest_rate = 0;
783 struct cpsw_common *cpsw = priv->cpsw;
784 struct cpsw_vector *txv = cpsw->txv;
785 int i, ch_weight, rlim_ch_num = 0;
786 int budget, bigest_rate_ch = 0;
787 u32 ch_rate, max_rate;
788 int ch_budget = 0;
789
790 for (i = 0; i < cpsw->tx_ch_num; i++) {
791 ch_rate = cpdma_chan_get_rate(txv[i].ch);
792 if (!ch_rate)
793 continue;
794
795 rlim_ch_num++;
796 consumed_rate += ch_rate;
797 }
798
799 if (cpsw->tx_ch_num == rlim_ch_num) {
800 max_rate = consumed_rate;
801 } else if (!rlim_ch_num) {
802 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
803 bigest_rate = 0;
804 max_rate = consumed_rate;
805 } else {
806 max_rate = cpsw->speed * 1000;
807
808 /* if max_rate is less then expected due to reduced link speed,
809 * split proportionally according next potential max speed
810 */
811 if (max_rate < consumed_rate)
812 max_rate *= 10;
813
814 if (max_rate < consumed_rate)
815 max_rate *= 10;
816
817 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
818 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
819 (cpsw->tx_ch_num - rlim_ch_num);
820 bigest_rate = (max_rate - consumed_rate) /
821 (cpsw->tx_ch_num - rlim_ch_num);
822 }
823
824 /* split tx weight/budget */
825 budget = CPSW_POLL_WEIGHT;
826 for (i = 0; i < cpsw->tx_ch_num; i++) {
827 ch_rate = cpdma_chan_get_rate(txv[i].ch);
828 if (ch_rate) {
829 txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
830 if (!txv[i].budget)
831 txv[i].budget++;
832 if (ch_rate > bigest_rate) {
833 bigest_rate_ch = i;
834 bigest_rate = ch_rate;
835 }
836
837 ch_weight = (ch_rate * 100) / max_rate;
838 if (!ch_weight)
839 ch_weight++;
840 cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
841 } else {
842 txv[i].budget = ch_budget;
843 if (!bigest_rate_ch)
844 bigest_rate_ch = i;
845 cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
846 }
847
848 budget -= txv[i].budget;
849 }
850
851 if (budget)
852 txv[bigest_rate_ch].budget += budget;
853
854 /* split rx budget */
855 budget = CPSW_POLL_WEIGHT;
856 ch_budget = budget / cpsw->rx_ch_num;
857 for (i = 0; i < cpsw->rx_ch_num; i++) {
858 cpsw->rxv[i].budget = ch_budget;
859 budget -= ch_budget;
860 }
861
862 if (budget)
863 cpsw->rxv[0].budget += budget;
864 }
865
866 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
867 {
868 struct cpsw_common *cpsw = dev_id;
869
870 writel(0, &cpsw->wr_regs->tx_en);
871 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
872
873 if (cpsw->quirk_irq) {
874 disable_irq_nosync(cpsw->irqs_table[1]);
875 cpsw->tx_irq_disabled = true;
876 }
877
878 napi_schedule(&cpsw->napi_tx);
879 return IRQ_HANDLED;
880 }
881
882 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
883 {
884 struct cpsw_common *cpsw = dev_id;
885
886 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
887 writel(0, &cpsw->wr_regs->rx_en);
888
889 if (cpsw->quirk_irq) {
890 disable_irq_nosync(cpsw->irqs_table[0]);
891 cpsw->rx_irq_disabled = true;
892 }
893
894 napi_schedule(&cpsw->napi_rx);
895 return IRQ_HANDLED;
896 }
897
898 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
899 {
900 u32 ch_map;
901 int num_tx, cur_budget, ch;
902 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
903 struct cpsw_vector *txv;
904
905 /* process every unprocessed channel */
906 ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
907 for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
908 if (!(ch_map & 0x01))
909 continue;
910
911 txv = &cpsw->txv[ch];
912 if (unlikely(txv->budget > budget - num_tx))
913 cur_budget = budget - num_tx;
914 else
915 cur_budget = txv->budget;
916
917 num_tx += cpdma_chan_process(txv->ch, cur_budget);
918 if (num_tx >= budget)
919 break;
920 }
921
922 if (num_tx < budget) {
923 napi_complete(napi_tx);
924 writel(0xff, &cpsw->wr_regs->tx_en);
925 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
926 cpsw->tx_irq_disabled = false;
927 enable_irq(cpsw->irqs_table[1]);
928 }
929 }
930
931 return num_tx;
932 }
933
934 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
935 {
936 u32 ch_map;
937 int num_rx, cur_budget, ch;
938 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
939 struct cpsw_vector *rxv;
940
941 /* process every unprocessed channel */
942 ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
943 for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
944 if (!(ch_map & 0x01))
945 continue;
946
947 rxv = &cpsw->rxv[ch];
948 if (unlikely(rxv->budget > budget - num_rx))
949 cur_budget = budget - num_rx;
950 else
951 cur_budget = rxv->budget;
952
953 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
954 if (num_rx >= budget)
955 break;
956 }
957
958 if (num_rx < budget) {
959 napi_complete_done(napi_rx, num_rx);
960 writel(0xff, &cpsw->wr_regs->rx_en);
961 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
962 cpsw->rx_irq_disabled = false;
963 enable_irq(cpsw->irqs_table[0]);
964 }
965 }
966
967 return num_rx;
968 }
969
970 static inline void soft_reset(const char *module, void __iomem *reg)
971 {
972 unsigned long timeout = jiffies + HZ;
973
974 writel_relaxed(1, reg);
975 do {
976 cpu_relax();
977 } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies));
978
979 WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module);
980 }
981
982 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
983 struct cpsw_priv *priv)
984 {
985 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
986 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
987 }
988
989 static void _cpsw_adjust_link(struct cpsw_slave *slave,
990 struct cpsw_priv *priv, bool *link)
991 {
992 struct phy_device *phy = slave->phy;
993 u32 mac_control = 0;
994 u32 slave_port;
995 struct cpsw_common *cpsw = priv->cpsw;
996
997 if (!phy)
998 return;
999
1000 slave_port = cpsw_get_slave_port(slave->slave_num);
1001
1002 if (phy->link) {
1003 mac_control = cpsw->data.mac_control;
1004
1005 /* enable forwarding */
1006 cpsw_ale_control_set(cpsw->ale, slave_port,
1007 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1008
1009 if (phy->speed == 1000)
1010 mac_control |= BIT(7); /* GIGABITEN */
1011 if (phy->duplex)
1012 mac_control |= BIT(0); /* FULLDUPLEXEN */
1013
1014 /* set speed_in input in case RMII mode is used in 100Mbps */
1015 if (phy->speed == 100)
1016 mac_control |= BIT(15);
1017 /* in band mode only works in 10Mbps RGMII mode */
1018 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
1019 mac_control |= BIT(18); /* In Band mode */
1020
1021 if (priv->rx_pause)
1022 mac_control |= BIT(3);
1023
1024 if (priv->tx_pause)
1025 mac_control |= BIT(4);
1026
1027 *link = true;
1028 } else {
1029 mac_control = 0;
1030 /* disable forwarding */
1031 cpsw_ale_control_set(cpsw->ale, slave_port,
1032 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1033 }
1034
1035 if (mac_control != slave->mac_control) {
1036 phy_print_status(phy);
1037 writel_relaxed(mac_control, &slave->sliver->mac_control);
1038 }
1039
1040 slave->mac_control = mac_control;
1041 }
1042
1043 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1044 {
1045 int i, speed;
1046
1047 for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1048 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1049 speed += cpsw->slaves[i].phy->speed;
1050
1051 return speed;
1052 }
1053
1054 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1055 {
1056 int i, rlim_ch_num;
1057 int speed, ch_rate;
1058
1059 /* re-split resources only in case speed was changed */
1060 speed = cpsw_get_common_speed(cpsw);
1061 if (speed == cpsw->speed || !speed)
1062 return 0;
1063
1064 cpsw->speed = speed;
1065
1066 for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1067 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1068 if (!ch_rate)
1069 break;
1070
1071 rlim_ch_num++;
1072 }
1073
1074 /* cases not dependent on speed */
1075 if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1076 return 0;
1077
1078 return 1;
1079 }
1080
1081 static void cpsw_adjust_link(struct net_device *ndev)
1082 {
1083 struct cpsw_priv *priv = netdev_priv(ndev);
1084 struct cpsw_common *cpsw = priv->cpsw;
1085 bool link = false;
1086
1087 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1088
1089 if (link) {
1090 if (cpsw_need_resplit(cpsw))
1091 cpsw_split_res(ndev);
1092
1093 netif_carrier_on(ndev);
1094 if (netif_running(ndev))
1095 netif_tx_wake_all_queues(ndev);
1096 } else {
1097 netif_carrier_off(ndev);
1098 netif_tx_stop_all_queues(ndev);
1099 }
1100 }
1101
1102 static int cpsw_get_coalesce(struct net_device *ndev,
1103 struct ethtool_coalesce *coal)
1104 {
1105 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1106
1107 coal->rx_coalesce_usecs = cpsw->coal_intvl;
1108 return 0;
1109 }
1110
1111 static int cpsw_set_coalesce(struct net_device *ndev,
1112 struct ethtool_coalesce *coal)
1113 {
1114 struct cpsw_priv *priv = netdev_priv(ndev);
1115 u32 int_ctrl;
1116 u32 num_interrupts = 0;
1117 u32 prescale = 0;
1118 u32 addnl_dvdr = 1;
1119 u32 coal_intvl = 0;
1120 struct cpsw_common *cpsw = priv->cpsw;
1121
1122 coal_intvl = coal->rx_coalesce_usecs;
1123
1124 int_ctrl = readl(&cpsw->wr_regs->int_control);
1125 prescale = cpsw->bus_freq_mhz * 4;
1126
1127 if (!coal->rx_coalesce_usecs) {
1128 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1129 goto update_return;
1130 }
1131
1132 if (coal_intvl < CPSW_CMINTMIN_INTVL)
1133 coal_intvl = CPSW_CMINTMIN_INTVL;
1134
1135 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1136 /* Interrupt pacer works with 4us Pulse, we can
1137 * throttle further by dilating the 4us pulse.
1138 */
1139 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1140
1141 if (addnl_dvdr > 1) {
1142 prescale *= addnl_dvdr;
1143 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1144 coal_intvl = (CPSW_CMINTMAX_INTVL
1145 * addnl_dvdr);
1146 } else {
1147 addnl_dvdr = 1;
1148 coal_intvl = CPSW_CMINTMAX_INTVL;
1149 }
1150 }
1151
1152 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1153 writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1154 writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1155
1156 int_ctrl |= CPSW_INTPACEEN;
1157 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1158 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1159
1160 update_return:
1161 writel(int_ctrl, &cpsw->wr_regs->int_control);
1162
1163 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1164 cpsw->coal_intvl = coal_intvl;
1165
1166 return 0;
1167 }
1168
1169 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1170 {
1171 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1172
1173 switch (sset) {
1174 case ETH_SS_STATS:
1175 return (CPSW_STATS_COMMON_LEN +
1176 (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1177 CPSW_STATS_CH_LEN);
1178 default:
1179 return -EOPNOTSUPP;
1180 }
1181 }
1182
1183 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1184 {
1185 int ch_stats_len;
1186 int line;
1187 int i;
1188
1189 ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1190 for (i = 0; i < ch_stats_len; i++) {
1191 line = i % CPSW_STATS_CH_LEN;
1192 snprintf(*p, ETH_GSTRING_LEN,
1193 "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1194 i / CPSW_STATS_CH_LEN,
1195 cpsw_gstrings_ch_stats[line].stat_string);
1196 *p += ETH_GSTRING_LEN;
1197 }
1198 }
1199
1200 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1201 {
1202 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1203 u8 *p = data;
1204 int i;
1205
1206 switch (stringset) {
1207 case ETH_SS_STATS:
1208 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1209 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1210 ETH_GSTRING_LEN);
1211 p += ETH_GSTRING_LEN;
1212 }
1213
1214 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1215 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1216 break;
1217 }
1218 }
1219
1220 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1221 struct ethtool_stats *stats, u64 *data)
1222 {
1223 u8 *p;
1224 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1225 struct cpdma_chan_stats ch_stats;
1226 int i, l, ch;
1227
1228 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1229 for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1230 data[l] = readl(cpsw->hw_stats +
1231 cpsw_gstrings_stats[l].stat_offset);
1232
1233 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1234 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1235 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1236 p = (u8 *)&ch_stats +
1237 cpsw_gstrings_ch_stats[i].stat_offset;
1238 data[l] = *(u32 *)p;
1239 }
1240 }
1241
1242 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1243 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1244 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1245 p = (u8 *)&ch_stats +
1246 cpsw_gstrings_ch_stats[i].stat_offset;
1247 data[l] = *(u32 *)p;
1248 }
1249 }
1250 }
1251
1252 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1253 struct sk_buff *skb,
1254 struct cpdma_chan *txch)
1255 {
1256 struct cpsw_common *cpsw = priv->cpsw;
1257
1258 skb_tx_timestamp(skb);
1259 return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1260 priv->emac_port + cpsw->data.dual_emac);
1261 }
1262
1263 static inline void cpsw_add_dual_emac_def_ale_entries(
1264 struct cpsw_priv *priv, struct cpsw_slave *slave,
1265 u32 slave_port)
1266 {
1267 struct cpsw_common *cpsw = priv->cpsw;
1268 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1269
1270 if (cpsw->version == CPSW_VERSION_1)
1271 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1272 else
1273 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1274 cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1275 port_mask, port_mask, 0);
1276 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1277 port_mask, ALE_VLAN, slave->port_vlan, 0);
1278 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1279 HOST_PORT_NUM, ALE_VLAN |
1280 ALE_SECURE, slave->port_vlan);
1281 cpsw_ale_control_set(cpsw->ale, slave_port,
1282 ALE_PORT_DROP_UNKNOWN_VLAN, 1);
1283 }
1284
1285 static void soft_reset_slave(struct cpsw_slave *slave)
1286 {
1287 char name[32];
1288
1289 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1290 soft_reset(name, &slave->sliver->soft_reset);
1291 }
1292
1293 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1294 {
1295 u32 slave_port;
1296 struct phy_device *phy;
1297 struct cpsw_common *cpsw = priv->cpsw;
1298
1299 soft_reset_slave(slave);
1300
1301 /* setup priority mapping */
1302 writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1303
1304 switch (cpsw->version) {
1305 case CPSW_VERSION_1:
1306 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1307 /* Increase RX FIFO size to 5 for supporting fullduplex
1308 * flow control mode
1309 */
1310 slave_write(slave,
1311 (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1312 CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1313 break;
1314 case CPSW_VERSION_2:
1315 case CPSW_VERSION_3:
1316 case CPSW_VERSION_4:
1317 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1318 /* Increase RX FIFO size to 5 for supporting fullduplex
1319 * flow control mode
1320 */
1321 slave_write(slave,
1322 (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1323 CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1324 break;
1325 }
1326
1327 /* setup max packet size, and mac address */
1328 writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1329 cpsw_set_slave_mac(slave, priv);
1330
1331 slave->mac_control = 0; /* no link yet */
1332
1333 slave_port = cpsw_get_slave_port(slave->slave_num);
1334
1335 if (cpsw->data.dual_emac)
1336 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1337 else
1338 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1339 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1340
1341 if (slave->data->phy_node) {
1342 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1343 &cpsw_adjust_link, 0, slave->data->phy_if);
1344 if (!phy) {
1345 dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1346 slave->data->phy_node,
1347 slave->slave_num);
1348 return;
1349 }
1350 } else {
1351 phy = phy_connect(priv->ndev, slave->data->phy_id,
1352 &cpsw_adjust_link, slave->data->phy_if);
1353 if (IS_ERR(phy)) {
1354 dev_err(priv->dev,
1355 "phy \"%s\" not found on slave %d, err %ld\n",
1356 slave->data->phy_id, slave->slave_num,
1357 PTR_ERR(phy));
1358 return;
1359 }
1360 }
1361
1362 slave->phy = phy;
1363
1364 phy_attached_info(slave->phy);
1365
1366 phy_start(slave->phy);
1367
1368 /* Configure GMII_SEL register */
1369 cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1370 }
1371
1372 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1373 {
1374 struct cpsw_common *cpsw = priv->cpsw;
1375 const int vlan = cpsw->data.default_vlan;
1376 u32 reg;
1377 int i;
1378 int unreg_mcast_mask;
1379
1380 reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1381 CPSW2_PORT_VLAN;
1382
1383 writel(vlan, &cpsw->host_port_regs->port_vlan);
1384
1385 for (i = 0; i < cpsw->data.slaves; i++)
1386 slave_write(cpsw->slaves + i, vlan, reg);
1387
1388 if (priv->ndev->flags & IFF_ALLMULTI)
1389 unreg_mcast_mask = ALE_ALL_PORTS;
1390 else
1391 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1392
1393 cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1394 ALE_ALL_PORTS, ALE_ALL_PORTS,
1395 unreg_mcast_mask);
1396 }
1397
1398 static void cpsw_init_host_port(struct cpsw_priv *priv)
1399 {
1400 u32 fifo_mode;
1401 u32 control_reg;
1402 struct cpsw_common *cpsw = priv->cpsw;
1403
1404 /* soft reset the controller and initialize ale */
1405 soft_reset("cpsw", &cpsw->regs->soft_reset);
1406 cpsw_ale_start(cpsw->ale);
1407
1408 /* switch to vlan unaware mode */
1409 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1410 CPSW_ALE_VLAN_AWARE);
1411 control_reg = readl(&cpsw->regs->control);
1412 control_reg |= CPSW_VLAN_AWARE;
1413 writel(control_reg, &cpsw->regs->control);
1414 fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1415 CPSW_FIFO_NORMAL_MODE;
1416 writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1417
1418 /* setup host port priority mapping */
1419 writel_relaxed(CPDMA_TX_PRIORITY_MAP,
1420 &cpsw->host_port_regs->cpdma_tx_pri_map);
1421 writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1422
1423 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1424 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1425
1426 if (!cpsw->data.dual_emac) {
1427 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1428 0, 0);
1429 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1430 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1431 }
1432 }
1433
1434 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1435 {
1436 struct cpsw_common *cpsw = priv->cpsw;
1437 struct sk_buff *skb;
1438 int ch_buf_num;
1439 int ch, i, ret;
1440
1441 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1442 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1443 for (i = 0; i < ch_buf_num; i++) {
1444 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1445 cpsw->rx_packet_max,
1446 GFP_KERNEL);
1447 if (!skb) {
1448 cpsw_err(priv, ifup, "cannot allocate skb\n");
1449 return -ENOMEM;
1450 }
1451
1452 skb_set_queue_mapping(skb, ch);
1453 ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1454 skb->data, skb_tailroom(skb),
1455 0);
1456 if (ret < 0) {
1457 cpsw_err(priv, ifup,
1458 "cannot submit skb to channel %d rx, error %d\n",
1459 ch, ret);
1460 kfree_skb(skb);
1461 return ret;
1462 }
1463 kmemleak_not_leak(skb);
1464 }
1465
1466 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1467 ch, ch_buf_num);
1468 }
1469
1470 return 0;
1471 }
1472
1473 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1474 {
1475 u32 slave_port;
1476
1477 slave_port = cpsw_get_slave_port(slave->slave_num);
1478
1479 if (!slave->phy)
1480 return;
1481 phy_stop(slave->phy);
1482 phy_disconnect(slave->phy);
1483 slave->phy = NULL;
1484 cpsw_ale_control_set(cpsw->ale, slave_port,
1485 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1486 soft_reset_slave(slave);
1487 }
1488
1489 static int cpsw_ndo_open(struct net_device *ndev)
1490 {
1491 struct cpsw_priv *priv = netdev_priv(ndev);
1492 struct cpsw_common *cpsw = priv->cpsw;
1493 int ret;
1494 u32 reg;
1495
1496 ret = pm_runtime_get_sync(cpsw->dev);
1497 if (ret < 0) {
1498 pm_runtime_put_noidle(cpsw->dev);
1499 return ret;
1500 }
1501
1502 netif_carrier_off(ndev);
1503
1504 /* Notify the stack of the actual queue counts. */
1505 ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1506 if (ret) {
1507 dev_err(priv->dev, "cannot set real number of tx queues\n");
1508 goto err_cleanup;
1509 }
1510
1511 ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1512 if (ret) {
1513 dev_err(priv->dev, "cannot set real number of rx queues\n");
1514 goto err_cleanup;
1515 }
1516
1517 reg = cpsw->version;
1518
1519 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1520 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1521 CPSW_RTL_VERSION(reg));
1522
1523 /* Initialize host and slave ports */
1524 if (!cpsw->usage_count)
1525 cpsw_init_host_port(priv);
1526 for_each_slave(priv, cpsw_slave_open, priv);
1527
1528 /* Add default VLAN */
1529 if (!cpsw->data.dual_emac)
1530 cpsw_add_default_vlan(priv);
1531 else
1532 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1533 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1534
1535 /* initialize shared resources for every ndev */
1536 if (!cpsw->usage_count) {
1537 /* disable priority elevation */
1538 writel_relaxed(0, &cpsw->regs->ptype);
1539
1540 /* enable statistics collection only on all ports */
1541 writel_relaxed(0x7, &cpsw->regs->stat_port_en);
1542
1543 /* Enable internal fifo flow control */
1544 writel(0x7, &cpsw->regs->flow_control);
1545
1546 napi_enable(&cpsw->napi_rx);
1547 napi_enable(&cpsw->napi_tx);
1548
1549 if (cpsw->tx_irq_disabled) {
1550 cpsw->tx_irq_disabled = false;
1551 enable_irq(cpsw->irqs_table[1]);
1552 }
1553
1554 if (cpsw->rx_irq_disabled) {
1555 cpsw->rx_irq_disabled = false;
1556 enable_irq(cpsw->irqs_table[0]);
1557 }
1558
1559 ret = cpsw_fill_rx_channels(priv);
1560 if (ret < 0)
1561 goto err_cleanup;
1562
1563 if (cpts_register(cpsw->cpts))
1564 dev_err(priv->dev, "error registering cpts device\n");
1565
1566 }
1567
1568 /* Enable Interrupt pacing if configured */
1569 if (cpsw->coal_intvl != 0) {
1570 struct ethtool_coalesce coal;
1571
1572 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1573 cpsw_set_coalesce(ndev, &coal);
1574 }
1575
1576 cpdma_ctlr_start(cpsw->dma);
1577 cpsw_intr_enable(cpsw);
1578 cpsw->usage_count++;
1579
1580 return 0;
1581
1582 err_cleanup:
1583 cpdma_ctlr_stop(cpsw->dma);
1584 for_each_slave(priv, cpsw_slave_stop, cpsw);
1585 pm_runtime_put_sync(cpsw->dev);
1586 netif_carrier_off(priv->ndev);
1587 return ret;
1588 }
1589
1590 static int cpsw_ndo_stop(struct net_device *ndev)
1591 {
1592 struct cpsw_priv *priv = netdev_priv(ndev);
1593 struct cpsw_common *cpsw = priv->cpsw;
1594
1595 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1596 netif_tx_stop_all_queues(priv->ndev);
1597 netif_carrier_off(priv->ndev);
1598
1599 if (cpsw->usage_count <= 1) {
1600 napi_disable(&cpsw->napi_rx);
1601 napi_disable(&cpsw->napi_tx);
1602 cpts_unregister(cpsw->cpts);
1603 cpsw_intr_disable(cpsw);
1604 cpdma_ctlr_stop(cpsw->dma);
1605 cpsw_ale_stop(cpsw->ale);
1606 }
1607 for_each_slave(priv, cpsw_slave_stop, cpsw);
1608
1609 if (cpsw_need_resplit(cpsw))
1610 cpsw_split_res(ndev);
1611
1612 cpsw->usage_count--;
1613 pm_runtime_put_sync(cpsw->dev);
1614 return 0;
1615 }
1616
1617 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1618 struct net_device *ndev)
1619 {
1620 struct cpsw_priv *priv = netdev_priv(ndev);
1621 struct cpsw_common *cpsw = priv->cpsw;
1622 struct cpts *cpts = cpsw->cpts;
1623 struct netdev_queue *txq;
1624 struct cpdma_chan *txch;
1625 int ret, q_idx;
1626
1627 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1628 cpsw_err(priv, tx_err, "packet pad failed\n");
1629 ndev->stats.tx_dropped++;
1630 return NET_XMIT_DROP;
1631 }
1632
1633 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1634 cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
1635 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1636
1637 q_idx = skb_get_queue_mapping(skb);
1638 if (q_idx >= cpsw->tx_ch_num)
1639 q_idx = q_idx % cpsw->tx_ch_num;
1640
1641 txch = cpsw->txv[q_idx].ch;
1642 txq = netdev_get_tx_queue(ndev, q_idx);
1643 ret = cpsw_tx_packet_submit(priv, skb, txch);
1644 if (unlikely(ret != 0)) {
1645 cpsw_err(priv, tx_err, "desc submit failed\n");
1646 goto fail;
1647 }
1648
1649 /* If there is no more tx desc left free then we need to
1650 * tell the kernel to stop sending us tx frames.
1651 */
1652 if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1653 netif_tx_stop_queue(txq);
1654
1655 /* Barrier, so that stop_queue visible to other cpus */
1656 smp_mb__after_atomic();
1657
1658 if (cpdma_check_free_tx_desc(txch))
1659 netif_tx_wake_queue(txq);
1660 }
1661
1662 return NETDEV_TX_OK;
1663 fail:
1664 ndev->stats.tx_dropped++;
1665 netif_tx_stop_queue(txq);
1666
1667 /* Barrier, so that stop_queue visible to other cpus */
1668 smp_mb__after_atomic();
1669
1670 if (cpdma_check_free_tx_desc(txch))
1671 netif_tx_wake_queue(txq);
1672
1673 return NETDEV_TX_BUSY;
1674 }
1675
1676 #if IS_ENABLED(CONFIG_TI_CPTS)
1677
1678 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1679 {
1680 struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1681 u32 ts_en, seq_id;
1682
1683 if (!cpts_is_tx_enabled(cpsw->cpts) &&
1684 !cpts_is_rx_enabled(cpsw->cpts)) {
1685 slave_write(slave, 0, CPSW1_TS_CTL);
1686 return;
1687 }
1688
1689 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1690 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1691
1692 if (cpts_is_tx_enabled(cpsw->cpts))
1693 ts_en |= CPSW_V1_TS_TX_EN;
1694
1695 if (cpts_is_rx_enabled(cpsw->cpts))
1696 ts_en |= CPSW_V1_TS_RX_EN;
1697
1698 slave_write(slave, ts_en, CPSW1_TS_CTL);
1699 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1700 }
1701
1702 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1703 {
1704 struct cpsw_slave *slave;
1705 struct cpsw_common *cpsw = priv->cpsw;
1706 u32 ctrl, mtype;
1707
1708 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1709
1710 ctrl = slave_read(slave, CPSW2_CONTROL);
1711 switch (cpsw->version) {
1712 case CPSW_VERSION_2:
1713 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1714
1715 if (cpts_is_tx_enabled(cpsw->cpts))
1716 ctrl |= CTRL_V2_TX_TS_BITS;
1717
1718 if (cpts_is_rx_enabled(cpsw->cpts))
1719 ctrl |= CTRL_V2_RX_TS_BITS;
1720 break;
1721 case CPSW_VERSION_3:
1722 default:
1723 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1724
1725 if (cpts_is_tx_enabled(cpsw->cpts))
1726 ctrl |= CTRL_V3_TX_TS_BITS;
1727
1728 if (cpts_is_rx_enabled(cpsw->cpts))
1729 ctrl |= CTRL_V3_RX_TS_BITS;
1730 break;
1731 }
1732
1733 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1734
1735 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1736 slave_write(slave, ctrl, CPSW2_CONTROL);
1737 writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
1738 }
1739
1740 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1741 {
1742 struct cpsw_priv *priv = netdev_priv(dev);
1743 struct hwtstamp_config cfg;
1744 struct cpsw_common *cpsw = priv->cpsw;
1745 struct cpts *cpts = cpsw->cpts;
1746
1747 if (cpsw->version != CPSW_VERSION_1 &&
1748 cpsw->version != CPSW_VERSION_2 &&
1749 cpsw->version != CPSW_VERSION_3)
1750 return -EOPNOTSUPP;
1751
1752 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1753 return -EFAULT;
1754
1755 /* reserved for future extensions */
1756 if (cfg.flags)
1757 return -EINVAL;
1758
1759 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1760 return -ERANGE;
1761
1762 switch (cfg.rx_filter) {
1763 case HWTSTAMP_FILTER_NONE:
1764 cpts_rx_enable(cpts, 0);
1765 break;
1766 case HWTSTAMP_FILTER_ALL:
1767 case HWTSTAMP_FILTER_NTP_ALL:
1768 return -ERANGE;
1769 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1770 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1771 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1772 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
1773 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1774 break;
1775 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1776 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1777 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1778 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1779 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1780 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1781 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1782 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1783 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1784 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
1785 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1786 break;
1787 default:
1788 return -ERANGE;
1789 }
1790
1791 cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
1792
1793 switch (cpsw->version) {
1794 case CPSW_VERSION_1:
1795 cpsw_hwtstamp_v1(cpsw);
1796 break;
1797 case CPSW_VERSION_2:
1798 case CPSW_VERSION_3:
1799 cpsw_hwtstamp_v2(priv);
1800 break;
1801 default:
1802 WARN_ON(1);
1803 }
1804
1805 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1806 }
1807
1808 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1809 {
1810 struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1811 struct cpts *cpts = cpsw->cpts;
1812 struct hwtstamp_config cfg;
1813
1814 if (cpsw->version != CPSW_VERSION_1 &&
1815 cpsw->version != CPSW_VERSION_2 &&
1816 cpsw->version != CPSW_VERSION_3)
1817 return -EOPNOTSUPP;
1818
1819 cfg.flags = 0;
1820 cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1821 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1822 cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
1823 cpts->rx_enable : HWTSTAMP_FILTER_NONE);
1824
1825 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1826 }
1827 #else
1828 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1829 {
1830 return -EOPNOTSUPP;
1831 }
1832
1833 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1834 {
1835 return -EOPNOTSUPP;
1836 }
1837 #endif /*CONFIG_TI_CPTS*/
1838
1839 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1840 {
1841 struct cpsw_priv *priv = netdev_priv(dev);
1842 struct cpsw_common *cpsw = priv->cpsw;
1843 int slave_no = cpsw_slave_index(cpsw, priv);
1844
1845 if (!netif_running(dev))
1846 return -EINVAL;
1847
1848 switch (cmd) {
1849 case SIOCSHWTSTAMP:
1850 return cpsw_hwtstamp_set(dev, req);
1851 case SIOCGHWTSTAMP:
1852 return cpsw_hwtstamp_get(dev, req);
1853 }
1854
1855 if (!cpsw->slaves[slave_no].phy)
1856 return -EOPNOTSUPP;
1857 return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1858 }
1859
1860 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1861 {
1862 struct cpsw_priv *priv = netdev_priv(ndev);
1863 struct cpsw_common *cpsw = priv->cpsw;
1864 int ch;
1865
1866 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1867 ndev->stats.tx_errors++;
1868 cpsw_intr_disable(cpsw);
1869 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1870 cpdma_chan_stop(cpsw->txv[ch].ch);
1871 cpdma_chan_start(cpsw->txv[ch].ch);
1872 }
1873
1874 cpsw_intr_enable(cpsw);
1875 netif_trans_update(ndev);
1876 netif_tx_wake_all_queues(ndev);
1877 }
1878
1879 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1880 {
1881 struct cpsw_priv *priv = netdev_priv(ndev);
1882 struct sockaddr *addr = (struct sockaddr *)p;
1883 struct cpsw_common *cpsw = priv->cpsw;
1884 int flags = 0;
1885 u16 vid = 0;
1886 int ret;
1887
1888 if (!is_valid_ether_addr(addr->sa_data))
1889 return -EADDRNOTAVAIL;
1890
1891 ret = pm_runtime_get_sync(cpsw->dev);
1892 if (ret < 0) {
1893 pm_runtime_put_noidle(cpsw->dev);
1894 return ret;
1895 }
1896
1897 if (cpsw->data.dual_emac) {
1898 vid = cpsw->slaves[priv->emac_port].port_vlan;
1899 flags = ALE_VLAN;
1900 }
1901
1902 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1903 flags, vid);
1904 cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1905 flags, vid);
1906
1907 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1908 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1909 for_each_slave(priv, cpsw_set_slave_mac, priv);
1910
1911 pm_runtime_put(cpsw->dev);
1912
1913 return 0;
1914 }
1915
1916 #ifdef CONFIG_NET_POLL_CONTROLLER
1917 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1918 {
1919 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1920
1921 cpsw_intr_disable(cpsw);
1922 cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1923 cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1924 cpsw_intr_enable(cpsw);
1925 }
1926 #endif
1927
1928 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1929 unsigned short vid)
1930 {
1931 int ret;
1932 int unreg_mcast_mask = 0;
1933 u32 port_mask;
1934 struct cpsw_common *cpsw = priv->cpsw;
1935
1936 if (cpsw->data.dual_emac) {
1937 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1938
1939 if (priv->ndev->flags & IFF_ALLMULTI)
1940 unreg_mcast_mask = port_mask;
1941 } else {
1942 port_mask = ALE_ALL_PORTS;
1943
1944 if (priv->ndev->flags & IFF_ALLMULTI)
1945 unreg_mcast_mask = ALE_ALL_PORTS;
1946 else
1947 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1948 }
1949
1950 ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1951 unreg_mcast_mask);
1952 if (ret != 0)
1953 return ret;
1954
1955 ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1956 HOST_PORT_NUM, ALE_VLAN, vid);
1957 if (ret != 0)
1958 goto clean_vid;
1959
1960 ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1961 port_mask, ALE_VLAN, vid, 0);
1962 if (ret != 0)
1963 goto clean_vlan_ucast;
1964 return 0;
1965
1966 clean_vlan_ucast:
1967 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1968 HOST_PORT_NUM, ALE_VLAN, vid);
1969 clean_vid:
1970 cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1971 return ret;
1972 }
1973
1974 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1975 __be16 proto, u16 vid)
1976 {
1977 struct cpsw_priv *priv = netdev_priv(ndev);
1978 struct cpsw_common *cpsw = priv->cpsw;
1979 int ret;
1980
1981 if (vid == cpsw->data.default_vlan)
1982 return 0;
1983
1984 ret = pm_runtime_get_sync(cpsw->dev);
1985 if (ret < 0) {
1986 pm_runtime_put_noidle(cpsw->dev);
1987 return ret;
1988 }
1989
1990 if (cpsw->data.dual_emac) {
1991 /* In dual EMAC, reserved VLAN id should not be used for
1992 * creating VLAN interfaces as this can break the dual
1993 * EMAC port separation
1994 */
1995 int i;
1996
1997 for (i = 0; i < cpsw->data.slaves; i++) {
1998 if (vid == cpsw->slaves[i].port_vlan)
1999 return -EINVAL;
2000 }
2001 }
2002
2003 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
2004 ret = cpsw_add_vlan_ale_entry(priv, vid);
2005
2006 pm_runtime_put(cpsw->dev);
2007 return ret;
2008 }
2009
2010 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
2011 __be16 proto, u16 vid)
2012 {
2013 struct cpsw_priv *priv = netdev_priv(ndev);
2014 struct cpsw_common *cpsw = priv->cpsw;
2015 int ret;
2016
2017 if (vid == cpsw->data.default_vlan)
2018 return 0;
2019
2020 ret = pm_runtime_get_sync(cpsw->dev);
2021 if (ret < 0) {
2022 pm_runtime_put_noidle(cpsw->dev);
2023 return ret;
2024 }
2025
2026 if (cpsw->data.dual_emac) {
2027 int i;
2028
2029 for (i = 0; i < cpsw->data.slaves; i++) {
2030 if (vid == cpsw->slaves[i].port_vlan)
2031 return -EINVAL;
2032 }
2033 }
2034
2035 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2036 ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2037 if (ret != 0)
2038 return ret;
2039
2040 ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2041 HOST_PORT_NUM, ALE_VLAN, vid);
2042 if (ret != 0)
2043 return ret;
2044
2045 ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2046 0, ALE_VLAN, vid);
2047 pm_runtime_put(cpsw->dev);
2048 return ret;
2049 }
2050
2051 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2052 {
2053 struct cpsw_priv *priv = netdev_priv(ndev);
2054 struct cpsw_common *cpsw = priv->cpsw;
2055 struct cpsw_slave *slave;
2056 u32 min_rate;
2057 u32 ch_rate;
2058 int i, ret;
2059
2060 ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2061 if (ch_rate == rate)
2062 return 0;
2063
2064 ch_rate = rate * 1000;
2065 min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2066 if ((ch_rate < min_rate && ch_rate)) {
2067 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2068 min_rate);
2069 return -EINVAL;
2070 }
2071
2072 if (rate > cpsw->speed) {
2073 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2074 return -EINVAL;
2075 }
2076
2077 ret = pm_runtime_get_sync(cpsw->dev);
2078 if (ret < 0) {
2079 pm_runtime_put_noidle(cpsw->dev);
2080 return ret;
2081 }
2082
2083 ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2084 pm_runtime_put(cpsw->dev);
2085
2086 if (ret)
2087 return ret;
2088
2089 /* update rates for slaves tx queues */
2090 for (i = 0; i < cpsw->data.slaves; i++) {
2091 slave = &cpsw->slaves[i];
2092 if (!slave->ndev)
2093 continue;
2094
2095 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2096 }
2097
2098 cpsw_split_res(ndev);
2099 return ret;
2100 }
2101
2102 static const struct net_device_ops cpsw_netdev_ops = {
2103 .ndo_open = cpsw_ndo_open,
2104 .ndo_stop = cpsw_ndo_stop,
2105 .ndo_start_xmit = cpsw_ndo_start_xmit,
2106 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2107 .ndo_do_ioctl = cpsw_ndo_ioctl,
2108 .ndo_validate_addr = eth_validate_addr,
2109 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
2110 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
2111 .ndo_set_tx_maxrate = cpsw_ndo_set_tx_maxrate,
2112 #ifdef CONFIG_NET_POLL_CONTROLLER
2113 .ndo_poll_controller = cpsw_ndo_poll_controller,
2114 #endif
2115 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
2116 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
2117 };
2118
2119 static int cpsw_get_regs_len(struct net_device *ndev)
2120 {
2121 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2122
2123 return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2124 }
2125
2126 static void cpsw_get_regs(struct net_device *ndev,
2127 struct ethtool_regs *regs, void *p)
2128 {
2129 u32 *reg = p;
2130 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2131
2132 /* update CPSW IP version */
2133 regs->version = cpsw->version;
2134
2135 cpsw_ale_dump(cpsw->ale, reg);
2136 }
2137
2138 static void cpsw_get_drvinfo(struct net_device *ndev,
2139 struct ethtool_drvinfo *info)
2140 {
2141 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2142 struct platform_device *pdev = to_platform_device(cpsw->dev);
2143
2144 strlcpy(info->driver, "cpsw", sizeof(info->driver));
2145 strlcpy(info->version, "1.0", sizeof(info->version));
2146 strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2147 }
2148
2149 static u32 cpsw_get_msglevel(struct net_device *ndev)
2150 {
2151 struct cpsw_priv *priv = netdev_priv(ndev);
2152 return priv->msg_enable;
2153 }
2154
2155 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2156 {
2157 struct cpsw_priv *priv = netdev_priv(ndev);
2158 priv->msg_enable = value;
2159 }
2160
2161 #if IS_ENABLED(CONFIG_TI_CPTS)
2162 static int cpsw_get_ts_info(struct net_device *ndev,
2163 struct ethtool_ts_info *info)
2164 {
2165 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2166
2167 info->so_timestamping =
2168 SOF_TIMESTAMPING_TX_HARDWARE |
2169 SOF_TIMESTAMPING_TX_SOFTWARE |
2170 SOF_TIMESTAMPING_RX_HARDWARE |
2171 SOF_TIMESTAMPING_RX_SOFTWARE |
2172 SOF_TIMESTAMPING_SOFTWARE |
2173 SOF_TIMESTAMPING_RAW_HARDWARE;
2174 info->phc_index = cpsw->cpts->phc_index;
2175 info->tx_types =
2176 (1 << HWTSTAMP_TX_OFF) |
2177 (1 << HWTSTAMP_TX_ON);
2178 info->rx_filters =
2179 (1 << HWTSTAMP_FILTER_NONE) |
2180 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2181 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2182 return 0;
2183 }
2184 #else
2185 static int cpsw_get_ts_info(struct net_device *ndev,
2186 struct ethtool_ts_info *info)
2187 {
2188 info->so_timestamping =
2189 SOF_TIMESTAMPING_TX_SOFTWARE |
2190 SOF_TIMESTAMPING_RX_SOFTWARE |
2191 SOF_TIMESTAMPING_SOFTWARE;
2192 info->phc_index = -1;
2193 info->tx_types = 0;
2194 info->rx_filters = 0;
2195 return 0;
2196 }
2197 #endif
2198
2199 static int cpsw_get_link_ksettings(struct net_device *ndev,
2200 struct ethtool_link_ksettings *ecmd)
2201 {
2202 struct cpsw_priv *priv = netdev_priv(ndev);
2203 struct cpsw_common *cpsw = priv->cpsw;
2204 int slave_no = cpsw_slave_index(cpsw, priv);
2205
2206 if (!cpsw->slaves[slave_no].phy)
2207 return -EOPNOTSUPP;
2208
2209 phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2210 return 0;
2211 }
2212
2213 static int cpsw_set_link_ksettings(struct net_device *ndev,
2214 const struct ethtool_link_ksettings *ecmd)
2215 {
2216 struct cpsw_priv *priv = netdev_priv(ndev);
2217 struct cpsw_common *cpsw = priv->cpsw;
2218 int slave_no = cpsw_slave_index(cpsw, priv);
2219
2220 if (cpsw->slaves[slave_no].phy)
2221 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2222 ecmd);
2223 else
2224 return -EOPNOTSUPP;
2225 }
2226
2227 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2228 {
2229 struct cpsw_priv *priv = netdev_priv(ndev);
2230 struct cpsw_common *cpsw = priv->cpsw;
2231 int slave_no = cpsw_slave_index(cpsw, priv);
2232
2233 wol->supported = 0;
2234 wol->wolopts = 0;
2235
2236 if (cpsw->slaves[slave_no].phy)
2237 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2238 }
2239
2240 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2241 {
2242 struct cpsw_priv *priv = netdev_priv(ndev);
2243 struct cpsw_common *cpsw = priv->cpsw;
2244 int slave_no = cpsw_slave_index(cpsw, priv);
2245
2246 if (cpsw->slaves[slave_no].phy)
2247 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2248 else
2249 return -EOPNOTSUPP;
2250 }
2251
2252 static void cpsw_get_pauseparam(struct net_device *ndev,
2253 struct ethtool_pauseparam *pause)
2254 {
2255 struct cpsw_priv *priv = netdev_priv(ndev);
2256
2257 pause->autoneg = AUTONEG_DISABLE;
2258 pause->rx_pause = priv->rx_pause ? true : false;
2259 pause->tx_pause = priv->tx_pause ? true : false;
2260 }
2261
2262 static int cpsw_set_pauseparam(struct net_device *ndev,
2263 struct ethtool_pauseparam *pause)
2264 {
2265 struct cpsw_priv *priv = netdev_priv(ndev);
2266 bool link;
2267
2268 priv->rx_pause = pause->rx_pause ? true : false;
2269 priv->tx_pause = pause->tx_pause ? true : false;
2270
2271 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2272 return 0;
2273 }
2274
2275 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2276 {
2277 struct cpsw_priv *priv = netdev_priv(ndev);
2278 struct cpsw_common *cpsw = priv->cpsw;
2279 int ret;
2280
2281 ret = pm_runtime_get_sync(cpsw->dev);
2282 if (ret < 0) {
2283 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2284 pm_runtime_put_noidle(cpsw->dev);
2285 }
2286
2287 return ret;
2288 }
2289
2290 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2291 {
2292 struct cpsw_priv *priv = netdev_priv(ndev);
2293 int ret;
2294
2295 ret = pm_runtime_put(priv->cpsw->dev);
2296 if (ret < 0)
2297 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2298 }
2299
2300 static void cpsw_get_channels(struct net_device *ndev,
2301 struct ethtool_channels *ch)
2302 {
2303 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2304
2305 ch->max_combined = 0;
2306 ch->max_rx = CPSW_MAX_QUEUES;
2307 ch->max_tx = CPSW_MAX_QUEUES;
2308 ch->max_other = 0;
2309 ch->other_count = 0;
2310 ch->rx_count = cpsw->rx_ch_num;
2311 ch->tx_count = cpsw->tx_ch_num;
2312 ch->combined_count = 0;
2313 }
2314
2315 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2316 struct ethtool_channels *ch)
2317 {
2318 if (ch->combined_count)
2319 return -EINVAL;
2320
2321 /* verify we have at least one channel in each direction */
2322 if (!ch->rx_count || !ch->tx_count)
2323 return -EINVAL;
2324
2325 if (ch->rx_count > cpsw->data.channels ||
2326 ch->tx_count > cpsw->data.channels)
2327 return -EINVAL;
2328
2329 return 0;
2330 }
2331
2332 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2333 {
2334 struct cpsw_common *cpsw = priv->cpsw;
2335 void (*handler)(void *, int, int);
2336 struct netdev_queue *queue;
2337 struct cpsw_vector *vec;
2338 int ret, *ch;
2339
2340 if (rx) {
2341 ch = &cpsw->rx_ch_num;
2342 vec = cpsw->rxv;
2343 handler = cpsw_rx_handler;
2344 } else {
2345 ch = &cpsw->tx_ch_num;
2346 vec = cpsw->txv;
2347 handler = cpsw_tx_handler;
2348 }
2349
2350 while (*ch < ch_num) {
2351 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2352 queue = netdev_get_tx_queue(priv->ndev, *ch);
2353 queue->tx_maxrate = 0;
2354
2355 if (IS_ERR(vec[*ch].ch))
2356 return PTR_ERR(vec[*ch].ch);
2357
2358 if (!vec[*ch].ch)
2359 return -EINVAL;
2360
2361 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2362 (rx ? "rx" : "tx"));
2363 (*ch)++;
2364 }
2365
2366 while (*ch > ch_num) {
2367 (*ch)--;
2368
2369 ret = cpdma_chan_destroy(vec[*ch].ch);
2370 if (ret)
2371 return ret;
2372
2373 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2374 (rx ? "rx" : "tx"));
2375 }
2376
2377 return 0;
2378 }
2379
2380 static int cpsw_update_channels(struct cpsw_priv *priv,
2381 struct ethtool_channels *ch)
2382 {
2383 int ret;
2384
2385 ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2386 if (ret)
2387 return ret;
2388
2389 ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2390 if (ret)
2391 return ret;
2392
2393 return 0;
2394 }
2395
2396 static void cpsw_suspend_data_pass(struct net_device *ndev)
2397 {
2398 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2399 struct cpsw_slave *slave;
2400 int i;
2401
2402 /* Disable NAPI scheduling */
2403 cpsw_intr_disable(cpsw);
2404
2405 /* Stop all transmit queues for every network device.
2406 * Disable re-using rx descriptors with dormant_on.
2407 */
2408 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2409 if (!(slave->ndev && netif_running(slave->ndev)))
2410 continue;
2411
2412 netif_tx_stop_all_queues(slave->ndev);
2413 netif_dormant_on(slave->ndev);
2414 }
2415
2416 /* Handle rest of tx packets and stop cpdma channels */
2417 cpdma_ctlr_stop(cpsw->dma);
2418 }
2419
2420 static int cpsw_resume_data_pass(struct net_device *ndev)
2421 {
2422 struct cpsw_priv *priv = netdev_priv(ndev);
2423 struct cpsw_common *cpsw = priv->cpsw;
2424 struct cpsw_slave *slave;
2425 int i, ret;
2426
2427 /* Allow rx packets handling */
2428 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2429 if (slave->ndev && netif_running(slave->ndev))
2430 netif_dormant_off(slave->ndev);
2431
2432 /* After this receive is started */
2433 if (cpsw->usage_count) {
2434 ret = cpsw_fill_rx_channels(priv);
2435 if (ret)
2436 return ret;
2437
2438 cpdma_ctlr_start(cpsw->dma);
2439 cpsw_intr_enable(cpsw);
2440 }
2441
2442 /* Resume transmit for every affected interface */
2443 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2444 if (slave->ndev && netif_running(slave->ndev))
2445 netif_tx_start_all_queues(slave->ndev);
2446
2447 return 0;
2448 }
2449
2450 static int cpsw_set_channels(struct net_device *ndev,
2451 struct ethtool_channels *chs)
2452 {
2453 struct cpsw_priv *priv = netdev_priv(ndev);
2454 struct cpsw_common *cpsw = priv->cpsw;
2455 struct cpsw_slave *slave;
2456 int i, ret;
2457
2458 ret = cpsw_check_ch_settings(cpsw, chs);
2459 if (ret < 0)
2460 return ret;
2461
2462 cpsw_suspend_data_pass(ndev);
2463 ret = cpsw_update_channels(priv, chs);
2464 if (ret)
2465 goto err;
2466
2467 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2468 if (!(slave->ndev && netif_running(slave->ndev)))
2469 continue;
2470
2471 /* Inform stack about new count of queues */
2472 ret = netif_set_real_num_tx_queues(slave->ndev,
2473 cpsw->tx_ch_num);
2474 if (ret) {
2475 dev_err(priv->dev, "cannot set real number of tx queues\n");
2476 goto err;
2477 }
2478
2479 ret = netif_set_real_num_rx_queues(slave->ndev,
2480 cpsw->rx_ch_num);
2481 if (ret) {
2482 dev_err(priv->dev, "cannot set real number of rx queues\n");
2483 goto err;
2484 }
2485 }
2486
2487 if (cpsw->usage_count)
2488 cpsw_split_res(ndev);
2489
2490 ret = cpsw_resume_data_pass(ndev);
2491 if (!ret)
2492 return 0;
2493 err:
2494 dev_err(priv->dev, "cannot update channels number, closing device\n");
2495 dev_close(ndev);
2496 return ret;
2497 }
2498
2499 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2500 {
2501 struct cpsw_priv *priv = netdev_priv(ndev);
2502 struct cpsw_common *cpsw = priv->cpsw;
2503 int slave_no = cpsw_slave_index(cpsw, priv);
2504
2505 if (cpsw->slaves[slave_no].phy)
2506 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2507 else
2508 return -EOPNOTSUPP;
2509 }
2510
2511 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2512 {
2513 struct cpsw_priv *priv = netdev_priv(ndev);
2514 struct cpsw_common *cpsw = priv->cpsw;
2515 int slave_no = cpsw_slave_index(cpsw, priv);
2516
2517 if (cpsw->slaves[slave_no].phy)
2518 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2519 else
2520 return -EOPNOTSUPP;
2521 }
2522
2523 static int cpsw_nway_reset(struct net_device *ndev)
2524 {
2525 struct cpsw_priv *priv = netdev_priv(ndev);
2526 struct cpsw_common *cpsw = priv->cpsw;
2527 int slave_no = cpsw_slave_index(cpsw, priv);
2528
2529 if (cpsw->slaves[slave_no].phy)
2530 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2531 else
2532 return -EOPNOTSUPP;
2533 }
2534
2535 static void cpsw_get_ringparam(struct net_device *ndev,
2536 struct ethtool_ringparam *ering)
2537 {
2538 struct cpsw_priv *priv = netdev_priv(ndev);
2539 struct cpsw_common *cpsw = priv->cpsw;
2540
2541 /* not supported */
2542 ering->tx_max_pending = 0;
2543 ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2544 ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2545 ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2546 }
2547
2548 static int cpsw_set_ringparam(struct net_device *ndev,
2549 struct ethtool_ringparam *ering)
2550 {
2551 struct cpsw_priv *priv = netdev_priv(ndev);
2552 struct cpsw_common *cpsw = priv->cpsw;
2553 int ret;
2554
2555 /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2556
2557 if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
2558 ering->rx_pending < CPSW_MAX_QUEUES ||
2559 ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
2560 return -EINVAL;
2561
2562 if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
2563 return 0;
2564
2565 cpsw_suspend_data_pass(ndev);
2566
2567 cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
2568
2569 if (cpsw->usage_count)
2570 cpdma_chan_split_pool(cpsw->dma);
2571
2572 ret = cpsw_resume_data_pass(ndev);
2573 if (!ret)
2574 return 0;
2575
2576 dev_err(&ndev->dev, "cannot set ring params, closing device\n");
2577 dev_close(ndev);
2578 return ret;
2579 }
2580
2581 static const struct ethtool_ops cpsw_ethtool_ops = {
2582 .get_drvinfo = cpsw_get_drvinfo,
2583 .get_msglevel = cpsw_get_msglevel,
2584 .set_msglevel = cpsw_set_msglevel,
2585 .get_link = ethtool_op_get_link,
2586 .get_ts_info = cpsw_get_ts_info,
2587 .get_coalesce = cpsw_get_coalesce,
2588 .set_coalesce = cpsw_set_coalesce,
2589 .get_sset_count = cpsw_get_sset_count,
2590 .get_strings = cpsw_get_strings,
2591 .get_ethtool_stats = cpsw_get_ethtool_stats,
2592 .get_pauseparam = cpsw_get_pauseparam,
2593 .set_pauseparam = cpsw_set_pauseparam,
2594 .get_wol = cpsw_get_wol,
2595 .set_wol = cpsw_set_wol,
2596 .get_regs_len = cpsw_get_regs_len,
2597 .get_regs = cpsw_get_regs,
2598 .begin = cpsw_ethtool_op_begin,
2599 .complete = cpsw_ethtool_op_complete,
2600 .get_channels = cpsw_get_channels,
2601 .set_channels = cpsw_set_channels,
2602 .get_link_ksettings = cpsw_get_link_ksettings,
2603 .set_link_ksettings = cpsw_set_link_ksettings,
2604 .get_eee = cpsw_get_eee,
2605 .set_eee = cpsw_set_eee,
2606 .nway_reset = cpsw_nway_reset,
2607 .get_ringparam = cpsw_get_ringparam,
2608 .set_ringparam = cpsw_set_ringparam,
2609 };
2610
2611 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2612 u32 slave_reg_ofs, u32 sliver_reg_ofs)
2613 {
2614 void __iomem *regs = cpsw->regs;
2615 int slave_num = slave->slave_num;
2616 struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num;
2617
2618 slave->data = data;
2619 slave->regs = regs + slave_reg_ofs;
2620 slave->sliver = regs + sliver_reg_ofs;
2621 slave->port_vlan = data->dual_emac_res_vlan;
2622 }
2623
2624 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2625 struct platform_device *pdev)
2626 {
2627 struct device_node *node = pdev->dev.of_node;
2628 struct device_node *slave_node;
2629 int i = 0, ret;
2630 u32 prop;
2631
2632 if (!node)
2633 return -EINVAL;
2634
2635 if (of_property_read_u32(node, "slaves", &prop)) {
2636 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2637 return -EINVAL;
2638 }
2639 data->slaves = prop;
2640
2641 if (of_property_read_u32(node, "active_slave", &prop)) {
2642 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2643 return -EINVAL;
2644 }
2645 data->active_slave = prop;
2646
2647 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2648 * sizeof(struct cpsw_slave_data),
2649 GFP_KERNEL);
2650 if (!data->slave_data)
2651 return -ENOMEM;
2652
2653 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2654 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2655 return -EINVAL;
2656 }
2657 data->channels = prop;
2658
2659 if (of_property_read_u32(node, "ale_entries", &prop)) {
2660 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2661 return -EINVAL;
2662 }
2663 data->ale_entries = prop;
2664
2665 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2666 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2667 return -EINVAL;
2668 }
2669 data->bd_ram_size = prop;
2670
2671 if (of_property_read_u32(node, "mac_control", &prop)) {
2672 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2673 return -EINVAL;
2674 }
2675 data->mac_control = prop;
2676
2677 if (of_property_read_bool(node, "dual_emac"))
2678 data->dual_emac = 1;
2679
2680 /*
2681 * Populate all the child nodes here...
2682 */
2683 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2684 /* We do not want to force this, as in some cases may not have child */
2685 if (ret)
2686 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2687
2688 for_each_available_child_of_node(node, slave_node) {
2689 struct cpsw_slave_data *slave_data = data->slave_data + i;
2690 const void *mac_addr = NULL;
2691 int lenp;
2692 const __be32 *parp;
2693
2694 /* This is no slave child node, continue */
2695 if (strcmp(slave_node->name, "slave"))
2696 continue;
2697
2698 slave_data->phy_node = of_parse_phandle(slave_node,
2699 "phy-handle", 0);
2700 parp = of_get_property(slave_node, "phy_id", &lenp);
2701 if (slave_data->phy_node) {
2702 dev_dbg(&pdev->dev,
2703 "slave[%d] using phy-handle=\"%pOF\"\n",
2704 i, slave_data->phy_node);
2705 } else if (of_phy_is_fixed_link(slave_node)) {
2706 /* In the case of a fixed PHY, the DT node associated
2707 * to the PHY is the Ethernet MAC DT node.
2708 */
2709 ret = of_phy_register_fixed_link(slave_node);
2710 if (ret) {
2711 if (ret != -EPROBE_DEFER)
2712 dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2713 return ret;
2714 }
2715 slave_data->phy_node = of_node_get(slave_node);
2716 } else if (parp) {
2717 u32 phyid;
2718 struct device_node *mdio_node;
2719 struct platform_device *mdio;
2720
2721 if (lenp != (sizeof(__be32) * 2)) {
2722 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2723 goto no_phy_slave;
2724 }
2725 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2726 phyid = be32_to_cpup(parp+1);
2727 mdio = of_find_device_by_node(mdio_node);
2728 of_node_put(mdio_node);
2729 if (!mdio) {
2730 dev_err(&pdev->dev, "Missing mdio platform device\n");
2731 return -EINVAL;
2732 }
2733 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2734 PHY_ID_FMT, mdio->name, phyid);
2735 put_device(&mdio->dev);
2736 } else {
2737 dev_err(&pdev->dev,
2738 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2739 i);
2740 goto no_phy_slave;
2741 }
2742 slave_data->phy_if = of_get_phy_mode(slave_node);
2743 if (slave_data->phy_if < 0) {
2744 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2745 i);
2746 return slave_data->phy_if;
2747 }
2748
2749 no_phy_slave:
2750 mac_addr = of_get_mac_address(slave_node);
2751 if (mac_addr) {
2752 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2753 } else {
2754 ret = ti_cm_get_macid(&pdev->dev, i,
2755 slave_data->mac_addr);
2756 if (ret)
2757 return ret;
2758 }
2759 if (data->dual_emac) {
2760 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2761 &prop)) {
2762 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2763 slave_data->dual_emac_res_vlan = i+1;
2764 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2765 slave_data->dual_emac_res_vlan, i);
2766 } else {
2767 slave_data->dual_emac_res_vlan = prop;
2768 }
2769 }
2770
2771 i++;
2772 if (i == data->slaves)
2773 break;
2774 }
2775
2776 return 0;
2777 }
2778
2779 static void cpsw_remove_dt(struct platform_device *pdev)
2780 {
2781 struct net_device *ndev = platform_get_drvdata(pdev);
2782 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2783 struct cpsw_platform_data *data = &cpsw->data;
2784 struct device_node *node = pdev->dev.of_node;
2785 struct device_node *slave_node;
2786 int i = 0;
2787
2788 for_each_available_child_of_node(node, slave_node) {
2789 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2790
2791 if (strcmp(slave_node->name, "slave"))
2792 continue;
2793
2794 if (of_phy_is_fixed_link(slave_node))
2795 of_phy_deregister_fixed_link(slave_node);
2796
2797 of_node_put(slave_data->phy_node);
2798
2799 i++;
2800 if (i == data->slaves)
2801 break;
2802 }
2803
2804 of_platform_depopulate(&pdev->dev);
2805 }
2806
2807 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2808 {
2809 struct cpsw_common *cpsw = priv->cpsw;
2810 struct cpsw_platform_data *data = &cpsw->data;
2811 struct net_device *ndev;
2812 struct cpsw_priv *priv_sl2;
2813 int ret = 0;
2814
2815 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2816 if (!ndev) {
2817 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2818 return -ENOMEM;
2819 }
2820
2821 priv_sl2 = netdev_priv(ndev);
2822 priv_sl2->cpsw = cpsw;
2823 priv_sl2->ndev = ndev;
2824 priv_sl2->dev = &ndev->dev;
2825 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2826
2827 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2828 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2829 ETH_ALEN);
2830 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2831 priv_sl2->mac_addr);
2832 } else {
2833 random_ether_addr(priv_sl2->mac_addr);
2834 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2835 priv_sl2->mac_addr);
2836 }
2837 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2838
2839 priv_sl2->emac_port = 1;
2840 cpsw->slaves[1].ndev = ndev;
2841 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2842
2843 ndev->netdev_ops = &cpsw_netdev_ops;
2844 ndev->ethtool_ops = &cpsw_ethtool_ops;
2845
2846 /* register the network device */
2847 SET_NETDEV_DEV(ndev, cpsw->dev);
2848 ret = register_netdev(ndev);
2849 if (ret) {
2850 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2851 free_netdev(ndev);
2852 ret = -ENODEV;
2853 }
2854
2855 return ret;
2856 }
2857
2858 #define CPSW_QUIRK_IRQ BIT(0)
2859
2860 static const struct platform_device_id cpsw_devtype[] = {
2861 {
2862 /* keep it for existing comaptibles */
2863 .name = "cpsw",
2864 .driver_data = CPSW_QUIRK_IRQ,
2865 }, {
2866 .name = "am335x-cpsw",
2867 .driver_data = CPSW_QUIRK_IRQ,
2868 }, {
2869 .name = "am4372-cpsw",
2870 .driver_data = 0,
2871 }, {
2872 .name = "dra7-cpsw",
2873 .driver_data = 0,
2874 }, {
2875 /* sentinel */
2876 }
2877 };
2878 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2879
2880 enum ti_cpsw_type {
2881 CPSW = 0,
2882 AM335X_CPSW,
2883 AM4372_CPSW,
2884 DRA7_CPSW,
2885 };
2886
2887 static const struct of_device_id cpsw_of_mtable[] = {
2888 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2889 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2890 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2891 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2892 { /* sentinel */ },
2893 };
2894 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2895
2896 static int cpsw_probe(struct platform_device *pdev)
2897 {
2898 struct clk *clk;
2899 struct cpsw_platform_data *data;
2900 struct net_device *ndev;
2901 struct cpsw_priv *priv;
2902 struct cpdma_params dma_params;
2903 struct cpsw_ale_params ale_params;
2904 void __iomem *ss_regs;
2905 void __iomem *cpts_regs;
2906 struct resource *res, *ss_res;
2907 const struct of_device_id *of_id;
2908 struct gpio_descs *mode;
2909 u32 slave_offset, sliver_offset, slave_size;
2910 struct cpsw_common *cpsw;
2911 int ret = 0, i;
2912 int irq;
2913
2914 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2915 if (!cpsw)
2916 return -ENOMEM;
2917
2918 cpsw->dev = &pdev->dev;
2919
2920 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2921 if (!ndev) {
2922 dev_err(&pdev->dev, "error allocating net_device\n");
2923 return -ENOMEM;
2924 }
2925
2926 platform_set_drvdata(pdev, ndev);
2927 priv = netdev_priv(ndev);
2928 priv->cpsw = cpsw;
2929 priv->ndev = ndev;
2930 priv->dev = &ndev->dev;
2931 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2932 cpsw->rx_packet_max = max(rx_packet_max, 128);
2933
2934 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2935 if (IS_ERR(mode)) {
2936 ret = PTR_ERR(mode);
2937 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2938 goto clean_ndev_ret;
2939 }
2940
2941 /*
2942 * This may be required here for child devices.
2943 */
2944 pm_runtime_enable(&pdev->dev);
2945
2946 /* Select default pin state */
2947 pinctrl_pm_select_default_state(&pdev->dev);
2948
2949 /* Need to enable clocks with runtime PM api to access module
2950 * registers
2951 */
2952 ret = pm_runtime_get_sync(&pdev->dev);
2953 if (ret < 0) {
2954 pm_runtime_put_noidle(&pdev->dev);
2955 goto clean_runtime_disable_ret;
2956 }
2957
2958 ret = cpsw_probe_dt(&cpsw->data, pdev);
2959 if (ret)
2960 goto clean_dt_ret;
2961
2962 data = &cpsw->data;
2963 cpsw->rx_ch_num = 1;
2964 cpsw->tx_ch_num = 1;
2965
2966 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2967 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2968 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2969 } else {
2970 eth_random_addr(priv->mac_addr);
2971 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2972 }
2973
2974 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2975
2976 cpsw->slaves = devm_kzalloc(&pdev->dev,
2977 sizeof(struct cpsw_slave) * data->slaves,
2978 GFP_KERNEL);
2979 if (!cpsw->slaves) {
2980 ret = -ENOMEM;
2981 goto clean_dt_ret;
2982 }
2983 for (i = 0; i < data->slaves; i++)
2984 cpsw->slaves[i].slave_num = i;
2985
2986 cpsw->slaves[0].ndev = ndev;
2987 priv->emac_port = 0;
2988
2989 clk = devm_clk_get(&pdev->dev, "fck");
2990 if (IS_ERR(clk)) {
2991 dev_err(priv->dev, "fck is not found\n");
2992 ret = -ENODEV;
2993 goto clean_dt_ret;
2994 }
2995 cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2996
2997 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2998 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2999 if (IS_ERR(ss_regs)) {
3000 ret = PTR_ERR(ss_regs);
3001 goto clean_dt_ret;
3002 }
3003 cpsw->regs = ss_regs;
3004
3005 cpsw->version = readl(&cpsw->regs->id_ver);
3006
3007 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3008 cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
3009 if (IS_ERR(cpsw->wr_regs)) {
3010 ret = PTR_ERR(cpsw->wr_regs);
3011 goto clean_dt_ret;
3012 }
3013
3014 memset(&dma_params, 0, sizeof(dma_params));
3015 memset(&ale_params, 0, sizeof(ale_params));
3016
3017 switch (cpsw->version) {
3018 case CPSW_VERSION_1:
3019 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
3020 cpts_regs = ss_regs + CPSW1_CPTS_OFFSET;
3021 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
3022 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
3023 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
3024 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
3025 slave_offset = CPSW1_SLAVE_OFFSET;
3026 slave_size = CPSW1_SLAVE_SIZE;
3027 sliver_offset = CPSW1_SLIVER_OFFSET;
3028 dma_params.desc_mem_phys = 0;
3029 break;
3030 case CPSW_VERSION_2:
3031 case CPSW_VERSION_3:
3032 case CPSW_VERSION_4:
3033 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3034 cpts_regs = ss_regs + CPSW2_CPTS_OFFSET;
3035 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
3036 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
3037 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
3038 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
3039 slave_offset = CPSW2_SLAVE_OFFSET;
3040 slave_size = CPSW2_SLAVE_SIZE;
3041 sliver_offset = CPSW2_SLIVER_OFFSET;
3042 dma_params.desc_mem_phys =
3043 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3044 break;
3045 default:
3046 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
3047 ret = -ENODEV;
3048 goto clean_dt_ret;
3049 }
3050 for (i = 0; i < cpsw->data.slaves; i++) {
3051 struct cpsw_slave *slave = &cpsw->slaves[i];
3052
3053 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3054 slave_offset += slave_size;
3055 sliver_offset += SLIVER_SIZE;
3056 }
3057
3058 dma_params.dev = &pdev->dev;
3059 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
3060 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
3061 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
3062 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
3063 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
3064
3065 dma_params.num_chan = data->channels;
3066 dma_params.has_soft_reset = true;
3067 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
3068 dma_params.desc_mem_size = data->bd_ram_size;
3069 dma_params.desc_align = 16;
3070 dma_params.has_ext_regs = true;
3071 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
3072 dma_params.bus_freq_mhz = cpsw->bus_freq_mhz;
3073 dma_params.descs_pool_size = descs_pool_size;
3074
3075 cpsw->dma = cpdma_ctlr_create(&dma_params);
3076 if (!cpsw->dma) {
3077 dev_err(priv->dev, "error initializing dma\n");
3078 ret = -ENOMEM;
3079 goto clean_dt_ret;
3080 }
3081
3082 cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
3083 if (IS_ERR(cpsw->txv[0].ch)) {
3084 dev_err(priv->dev, "error initializing tx dma channel\n");
3085 ret = PTR_ERR(cpsw->txv[0].ch);
3086 goto clean_dma_ret;
3087 }
3088
3089 cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3090 if (IS_ERR(cpsw->rxv[0].ch)) {
3091 dev_err(priv->dev, "error initializing rx dma channel\n");
3092 ret = PTR_ERR(cpsw->rxv[0].ch);
3093 goto clean_dma_ret;
3094 }
3095
3096 ale_params.dev = &pdev->dev;
3097 ale_params.ale_ageout = ale_ageout;
3098 ale_params.ale_entries = data->ale_entries;
3099 ale_params.ale_ports = CPSW_ALE_PORTS_NUM;
3100
3101 cpsw->ale = cpsw_ale_create(&ale_params);
3102 if (!cpsw->ale) {
3103 dev_err(priv->dev, "error initializing ale engine\n");
3104 ret = -ENODEV;
3105 goto clean_dma_ret;
3106 }
3107
3108 cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3109 if (IS_ERR(cpsw->cpts)) {
3110 ret = PTR_ERR(cpsw->cpts);
3111 goto clean_dma_ret;
3112 }
3113
3114 ndev->irq = platform_get_irq(pdev, 1);
3115 if (ndev->irq < 0) {
3116 dev_err(priv->dev, "error getting irq resource\n");
3117 ret = ndev->irq;
3118 goto clean_dma_ret;
3119 }
3120
3121 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
3122 if (of_id) {
3123 pdev->id_entry = of_id->data;
3124 if (pdev->id_entry->driver_data)
3125 cpsw->quirk_irq = true;
3126 }
3127
3128 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3129
3130 ndev->netdev_ops = &cpsw_netdev_ops;
3131 ndev->ethtool_ops = &cpsw_ethtool_ops;
3132 netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
3133 netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
3134 cpsw_split_res(ndev);
3135
3136 /* register the network device */
3137 SET_NETDEV_DEV(ndev, &pdev->dev);
3138 ret = register_netdev(ndev);
3139 if (ret) {
3140 dev_err(priv->dev, "error registering net device\n");
3141 ret = -ENODEV;
3142 goto clean_dma_ret;
3143 }
3144
3145 if (cpsw->data.dual_emac) {
3146 ret = cpsw_probe_dual_emac(priv);
3147 if (ret) {
3148 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3149 goto clean_unregister_netdev_ret;
3150 }
3151 }
3152
3153 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3154 * MISC IRQs which are always kept disabled with this driver so
3155 * we will not request them.
3156 *
3157 * If anyone wants to implement support for those, make sure to
3158 * first request and append them to irqs_table array.
3159 */
3160
3161 /* RX IRQ */
3162 irq = platform_get_irq(pdev, 1);
3163 if (irq < 0) {
3164 ret = irq;
3165 goto clean_dma_ret;
3166 }
3167
3168 cpsw->irqs_table[0] = irq;
3169 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3170 0, dev_name(&pdev->dev), cpsw);
3171 if (ret < 0) {
3172 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3173 goto clean_dma_ret;
3174 }
3175
3176 /* TX IRQ */
3177 irq = platform_get_irq(pdev, 2);
3178 if (irq < 0) {
3179 ret = irq;
3180 goto clean_dma_ret;
3181 }
3182
3183 cpsw->irqs_table[1] = irq;
3184 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3185 0, dev_name(&pdev->dev), cpsw);
3186 if (ret < 0) {
3187 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3188 goto clean_dma_ret;
3189 }
3190
3191 cpsw_notice(priv, probe,
3192 "initialized device (regs %pa, irq %d, pool size %d)\n",
3193 &ss_res->start, ndev->irq, dma_params.descs_pool_size);
3194
3195 pm_runtime_put(&pdev->dev);
3196
3197 return 0;
3198
3199 clean_unregister_netdev_ret:
3200 unregister_netdev(ndev);
3201 clean_dma_ret:
3202 cpdma_ctlr_destroy(cpsw->dma);
3203 clean_dt_ret:
3204 cpsw_remove_dt(pdev);
3205 pm_runtime_put_sync(&pdev->dev);
3206 clean_runtime_disable_ret:
3207 pm_runtime_disable(&pdev->dev);
3208 clean_ndev_ret:
3209 free_netdev(priv->ndev);
3210 return ret;
3211 }
3212
3213 static int cpsw_remove(struct platform_device *pdev)
3214 {
3215 struct net_device *ndev = platform_get_drvdata(pdev);
3216 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3217 int ret;
3218
3219 ret = pm_runtime_get_sync(&pdev->dev);
3220 if (ret < 0) {
3221 pm_runtime_put_noidle(&pdev->dev);
3222 return ret;
3223 }
3224
3225 if (cpsw->data.dual_emac)
3226 unregister_netdev(cpsw->slaves[1].ndev);
3227 unregister_netdev(ndev);
3228
3229 cpts_release(cpsw->cpts);
3230 cpdma_ctlr_destroy(cpsw->dma);
3231 cpsw_remove_dt(pdev);
3232 pm_runtime_put_sync(&pdev->dev);
3233 pm_runtime_disable(&pdev->dev);
3234 if (cpsw->data.dual_emac)
3235 free_netdev(cpsw->slaves[1].ndev);
3236 free_netdev(ndev);
3237 return 0;
3238 }
3239
3240 #ifdef CONFIG_PM_SLEEP
3241 static int cpsw_suspend(struct device *dev)
3242 {
3243 struct platform_device *pdev = to_platform_device(dev);
3244 struct net_device *ndev = platform_get_drvdata(pdev);
3245 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3246
3247 if (cpsw->data.dual_emac) {
3248 int i;
3249
3250 for (i = 0; i < cpsw->data.slaves; i++) {
3251 if (netif_running(cpsw->slaves[i].ndev))
3252 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3253 }
3254 } else {
3255 if (netif_running(ndev))
3256 cpsw_ndo_stop(ndev);
3257 }
3258
3259 /* Select sleep pin state */
3260 pinctrl_pm_select_sleep_state(dev);
3261
3262 return 0;
3263 }
3264
3265 static int cpsw_resume(struct device *dev)
3266 {
3267 struct platform_device *pdev = to_platform_device(dev);
3268 struct net_device *ndev = platform_get_drvdata(pdev);
3269 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3270
3271 /* Select default pin state */
3272 pinctrl_pm_select_default_state(dev);
3273
3274 /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3275 rtnl_lock();
3276 if (cpsw->data.dual_emac) {
3277 int i;
3278
3279 for (i = 0; i < cpsw->data.slaves; i++) {
3280 if (netif_running(cpsw->slaves[i].ndev))
3281 cpsw_ndo_open(cpsw->slaves[i].ndev);
3282 }
3283 } else {
3284 if (netif_running(ndev))
3285 cpsw_ndo_open(ndev);
3286 }
3287 rtnl_unlock();
3288
3289 return 0;
3290 }
3291 #endif
3292
3293 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3294
3295 static struct platform_driver cpsw_driver = {
3296 .driver = {
3297 .name = "cpsw",
3298 .pm = &cpsw_pm_ops,
3299 .of_match_table = cpsw_of_mtable,
3300 },
3301 .probe = cpsw_probe,
3302 .remove = cpsw_remove,
3303 };
3304
3305 module_platform_driver(cpsw_driver);
3306
3307 MODULE_LICENSE("GPL");
3308 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3309 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3310 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux with added FPC-III support