Linux 4.16.11
[linux/fpc-iii.git] / drivers / net / ethernet / ti / davinci_cpdma.h
blobfd65ce2b83deb0d715cb397cad1b9c59c3f59d1d
1 /*
2 * Texas Instruments CPDMA Driver
4 * Copyright (C) 2010 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #ifndef __DAVINCI_CPDMA_H__
16 #define __DAVINCI_CPDMA_H__
18 #define CPDMA_MAX_CHANNELS BITS_PER_LONG
20 #define CPDMA_RX_SOURCE_PORT(__status__) ((__status__ >> 16) & 0x7)
22 #define CPDMA_EOI_RX_THRESH 0x0
23 #define CPDMA_EOI_RX 0x1
24 #define CPDMA_EOI_TX 0x2
25 #define CPDMA_EOI_MISC 0x3
27 struct cpdma_params {
28 struct device *dev;
29 void __iomem *dmaregs;
30 void __iomem *txhdp, *rxhdp, *txcp, *rxcp;
31 void __iomem *rxthresh, *rxfree;
32 int num_chan;
33 bool has_soft_reset;
34 int min_packet_size;
35 u32 desc_mem_phys;
36 u32 desc_hw_addr;
37 int desc_mem_size;
38 int desc_align;
39 u32 bus_freq_mhz;
40 u32 descs_pool_size;
43 * Some instances of embedded cpdma controllers have extra control and
44 * status registers. The following flag enables access to these
45 * "extended" registers.
47 bool has_ext_regs;
50 struct cpdma_chan_stats {
51 u32 head_enqueue;
52 u32 tail_enqueue;
53 u32 pad_enqueue;
54 u32 misqueued;
55 u32 desc_alloc_fail;
56 u32 pad_alloc_fail;
57 u32 runt_receive_buff;
58 u32 runt_transmit_buff;
59 u32 empty_dequeue;
60 u32 busy_dequeue;
61 u32 good_dequeue;
62 u32 requeue;
63 u32 teardown_dequeue;
66 struct cpdma_ctlr;
67 struct cpdma_chan;
69 typedef void (*cpdma_handler_fn)(void *token, int len, int status);
71 struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params);
72 int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
73 int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
74 int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
76 struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
77 cpdma_handler_fn handler, int rx_type);
78 int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan);
79 int cpdma_chan_destroy(struct cpdma_chan *chan);
80 int cpdma_chan_start(struct cpdma_chan *chan);
81 int cpdma_chan_stop(struct cpdma_chan *chan);
83 int cpdma_chan_get_stats(struct cpdma_chan *chan,
84 struct cpdma_chan_stats *stats);
85 int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
86 int len, int directed);
87 int cpdma_chan_process(struct cpdma_chan *chan, int quota);
89 int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
90 void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value);
91 int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
92 u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr);
93 u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr);
94 bool cpdma_check_free_tx_desc(struct cpdma_chan *chan);
95 int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight);
96 int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate);
97 u32 cpdma_chan_get_rate(struct cpdma_chan *ch);
98 u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr);
100 enum cpdma_control {
101 CPDMA_TX_RLIM, /* read-write */
102 CPDMA_CMD_IDLE, /* write-only */
103 CPDMA_COPY_ERROR_FRAMES, /* read-write */
104 CPDMA_RX_OFF_LEN_UPDATE, /* read-write */
105 CPDMA_RX_OWNERSHIP_FLIP, /* read-write */
106 CPDMA_TX_PRIO_FIXED, /* read-write */
107 CPDMA_STAT_IDLE, /* read-only */
108 CPDMA_STAT_TX_ERR_CHAN, /* read-only */
109 CPDMA_STAT_TX_ERR_CODE, /* read-only */
110 CPDMA_STAT_RX_ERR_CHAN, /* read-only */
111 CPDMA_STAT_RX_ERR_CODE, /* read-only */
112 CPDMA_RX_BUFFER_OFFSET, /* read-write */
115 int cpdma_control_get(struct cpdma_ctlr *ctlr, int control);
116 int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value);
117 int cpdma_get_num_rx_descs(struct cpdma_ctlr *ctlr);
118 void cpdma_set_num_rx_descs(struct cpdma_ctlr *ctlr, int num_rx_desc);
119 int cpdma_get_num_tx_descs(struct cpdma_ctlr *ctlr);
120 int cpdma_chan_split_pool(struct cpdma_ctlr *ctlr);
122 #endif