2 * Driver for the Texas Instruments DP83867 PHY
4 * Copyright (C) 2015 Texas Instruments Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/ethtool.h>
17 #include <linux/kernel.h>
18 #include <linux/mii.h>
19 #include <linux/module.h>
21 #include <linux/phy.h>
23 #include <dt-bindings/net/ti-dp83867.h>
25 #define DP83867_PHY_ID 0x2000a231
26 #define DP83867_DEVADDR 0x1f
28 #define MII_DP83867_PHYCTRL 0x10
29 #define MII_DP83867_MICR 0x12
30 #define MII_DP83867_ISR 0x13
31 #define DP83867_CTRL 0x1f
32 #define DP83867_CFG3 0x1e
34 /* Extended Registers */
35 #define DP83867_CFG4 0x0031
36 #define DP83867_RGMIICTL 0x0032
37 #define DP83867_STRAP_STS1 0x006E
38 #define DP83867_RGMIIDCTL 0x0086
39 #define DP83867_IO_MUX_CFG 0x0170
41 #define DP83867_SW_RESET BIT(15)
42 #define DP83867_SW_RESTART BIT(14)
44 /* MICR Interrupt bits */
45 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
46 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
47 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
48 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
49 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
50 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
51 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
52 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
53 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
54 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
55 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
56 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
59 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
60 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
63 #define DP83867_STRAP_STS1_RESERVED BIT(11)
66 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
67 #define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14)
68 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
71 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
74 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
76 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
77 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
80 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
83 DP83867_PORT_MIRROING_KEEP
,
84 DP83867_PORT_MIRROING_EN
,
85 DP83867_PORT_MIRROING_DIS
,
88 struct dp83867_private
{
94 bool rxctrl_strap_quirk
;
97 static int dp83867_ack_interrupt(struct phy_device
*phydev
)
99 int err
= phy_read(phydev
, MII_DP83867_ISR
);
107 static int dp83867_config_intr(struct phy_device
*phydev
)
111 if (phydev
->interrupts
== PHY_INTERRUPT_ENABLED
) {
112 micr_status
= phy_read(phydev
, MII_DP83867_MICR
);
117 (MII_DP83867_MICR_AN_ERR_INT_EN
|
118 MII_DP83867_MICR_SPEED_CHNG_INT_EN
|
119 MII_DP83867_MICR_AUTONEG_COMP_INT_EN
|
120 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN
|
121 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN
|
122 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN
);
124 return phy_write(phydev
, MII_DP83867_MICR
, micr_status
);
128 return phy_write(phydev
, MII_DP83867_MICR
, micr_status
);
131 static int dp83867_config_port_mirroring(struct phy_device
*phydev
)
133 struct dp83867_private
*dp83867
=
134 (struct dp83867_private
*)phydev
->priv
;
137 val
= phy_read_mmd(phydev
, DP83867_DEVADDR
, DP83867_CFG4
);
139 if (dp83867
->port_mirroring
== DP83867_PORT_MIRROING_EN
)
140 val
|= DP83867_CFG4_PORT_MIRROR_EN
;
142 val
&= ~DP83867_CFG4_PORT_MIRROR_EN
;
144 phy_write_mmd(phydev
, DP83867_DEVADDR
, DP83867_CFG4
, val
);
149 #ifdef CONFIG_OF_MDIO
150 static int dp83867_of_init(struct phy_device
*phydev
)
152 struct dp83867_private
*dp83867
= phydev
->priv
;
153 struct device
*dev
= &phydev
->mdio
.dev
;
154 struct device_node
*of_node
= dev
->of_node
;
160 dp83867
->io_impedance
= -EINVAL
;
162 /* Optional configuration */
163 if (of_property_read_bool(of_node
, "ti,max-output-impedance"))
164 dp83867
->io_impedance
= DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX
;
165 else if (of_property_read_bool(of_node
, "ti,min-output-impedance"))
166 dp83867
->io_impedance
= DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN
;
168 dp83867
->rxctrl_strap_quirk
= of_property_read_bool(of_node
,
169 "ti,dp83867-rxctrl-strap-quirk");
171 ret
= of_property_read_u32(of_node
, "ti,rx-internal-delay",
172 &dp83867
->rx_id_delay
);
174 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
||
175 phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
))
178 ret
= of_property_read_u32(of_node
, "ti,tx-internal-delay",
179 &dp83867
->tx_id_delay
);
181 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
||
182 phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
))
185 if (of_property_read_bool(of_node
, "enet-phy-lane-swap"))
186 dp83867
->port_mirroring
= DP83867_PORT_MIRROING_EN
;
188 if (of_property_read_bool(of_node
, "enet-phy-lane-no-swap"))
189 dp83867
->port_mirroring
= DP83867_PORT_MIRROING_DIS
;
191 return of_property_read_u32(of_node
, "ti,fifo-depth",
192 &dp83867
->fifo_depth
);
195 static int dp83867_of_init(struct phy_device
*phydev
)
199 #endif /* CONFIG_OF_MDIO */
201 static int dp83867_config_init(struct phy_device
*phydev
)
203 struct dp83867_private
*dp83867
;
208 dp83867
= devm_kzalloc(&phydev
->mdio
.dev
, sizeof(*dp83867
),
213 phydev
->priv
= dp83867
;
214 ret
= dp83867_of_init(phydev
);
218 dp83867
= (struct dp83867_private
*)phydev
->priv
;
221 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
222 if (dp83867
->rxctrl_strap_quirk
) {
223 val
= phy_read_mmd(phydev
, DP83867_DEVADDR
, DP83867_CFG4
);
225 phy_write_mmd(phydev
, DP83867_DEVADDR
, DP83867_CFG4
, val
);
228 if (phy_interface_is_rgmii(phydev
)) {
229 val
= phy_read(phydev
, MII_DP83867_PHYCTRL
);
232 val
&= ~DP83867_PHYCR_FIFO_DEPTH_MASK
;
233 val
|= (dp83867
->fifo_depth
<< DP83867_PHYCR_FIFO_DEPTH_SHIFT
);
235 /* The code below checks if "port mirroring" N/A MODE4 has been
236 * enabled during power on bootstrap.
238 * Such N/A mode enabled by mistake can put PHY IC in some
239 * internal testing mode and disable RGMII transmission.
241 * In this particular case one needs to check STRAP_STS1
242 * register's bit 11 (marked as RESERVED).
245 bs
= phy_read_mmd(phydev
, DP83867_DEVADDR
, DP83867_STRAP_STS1
);
246 if (bs
& DP83867_STRAP_STS1_RESERVED
)
247 val
&= ~DP83867_PHYCR_RESERVED_MASK
;
249 ret
= phy_write(phydev
, MII_DP83867_PHYCTRL
, val
);
254 if ((phydev
->interface
>= PHY_INTERFACE_MODE_RGMII_ID
) &&
255 (phydev
->interface
<= PHY_INTERFACE_MODE_RGMII_RXID
)) {
256 val
= phy_read_mmd(phydev
, DP83867_DEVADDR
, DP83867_RGMIICTL
);
258 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
)
259 val
|= (DP83867_RGMII_TX_CLK_DELAY_EN
| DP83867_RGMII_RX_CLK_DELAY_EN
);
261 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
)
262 val
|= DP83867_RGMII_TX_CLK_DELAY_EN
;
264 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
)
265 val
|= DP83867_RGMII_RX_CLK_DELAY_EN
;
267 phy_write_mmd(phydev
, DP83867_DEVADDR
, DP83867_RGMIICTL
, val
);
269 delay
= (dp83867
->rx_id_delay
|
270 (dp83867
->tx_id_delay
<< DP83867_RGMII_TX_CLK_DELAY_SHIFT
));
272 phy_write_mmd(phydev
, DP83867_DEVADDR
, DP83867_RGMIIDCTL
,
275 if (dp83867
->io_impedance
>= 0) {
276 val
= phy_read_mmd(phydev
, DP83867_DEVADDR
,
279 val
&= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL
;
280 val
|= dp83867
->io_impedance
&
281 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL
;
283 phy_write_mmd(phydev
, DP83867_DEVADDR
,
284 DP83867_IO_MUX_CFG
, val
);
288 /* Enable Interrupt output INT_OE in CFG3 register */
289 if (phy_interrupt_is_valid(phydev
)) {
290 val
= phy_read(phydev
, DP83867_CFG3
);
292 phy_write(phydev
, DP83867_CFG3
, val
);
295 if (dp83867
->port_mirroring
!= DP83867_PORT_MIRROING_KEEP
)
296 dp83867_config_port_mirroring(phydev
);
301 static int dp83867_phy_reset(struct phy_device
*phydev
)
305 err
= phy_write(phydev
, DP83867_CTRL
, DP83867_SW_RESET
);
309 return dp83867_config_init(phydev
);
312 static struct phy_driver dp83867_driver
[] = {
314 .phy_id
= DP83867_PHY_ID
,
315 .phy_id_mask
= 0xfffffff0,
316 .name
= "TI DP83867",
317 .features
= PHY_GBIT_FEATURES
,
318 .flags
= PHY_HAS_INTERRUPT
,
320 .config_init
= dp83867_config_init
,
321 .soft_reset
= dp83867_phy_reset
,
324 .ack_interrupt
= dp83867_ack_interrupt
,
325 .config_intr
= dp83867_config_intr
,
327 .suspend
= genphy_suspend
,
328 .resume
= genphy_resume
,
331 module_phy_driver(dp83867_driver
);
333 static struct mdio_device_id __maybe_unused dp83867_tbl
[] = {
334 { DP83867_PHY_ID
, 0xfffffff0 },
338 MODULE_DEVICE_TABLE(mdio
, dp83867_tbl
);
340 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
341 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
342 MODULE_LICENSE("GPL");