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Linux 4.16.11
[linux/fpc-iii.git] / drivers / net / wireless / ath / wil6210 / interrupt.c
blob1835187ea075dcf381e2b0f8bf683377af4e7228
1 /*
2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <linux/interrupt.h>
19
20 #include "wil6210.h"
21 #include "trace.h"
22
23 /**
24 * Theory of operation:
25 *
26 * There is ISR pseudo-cause register,
27 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
28 * Its bits represents OR'ed bits from 3 real ISR registers:
29 * TX, RX, and MISC.
30 *
31 * Registers may be configured to either "write 1 to clear" or
32 * "clear on read" mode
33 *
34 * When handling interrupt, one have to mask/unmask interrupts for the
35 * real ISR registers, or hardware may malfunction.
36 *
37 */
38
39 #define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
40 #define WIL6210_IRQ_DISABLE_NO_HALP (0xF7FFFFFFUL)
41 #define WIL6210_IMC_RX (BIT_DMA_EP_RX_ICR_RX_DONE | \
42 BIT_DMA_EP_RX_ICR_RX_HTRSH)
43 #define WIL6210_IMC_RX_NO_RX_HTRSH (WIL6210_IMC_RX & \
44 (~(BIT_DMA_EP_RX_ICR_RX_HTRSH)))
45 #define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \
46 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
47 #define WIL6210_IMC_MISC_NO_HALP (ISR_MISC_FW_READY | \
48 ISR_MISC_MBOX_EVT | \
49 ISR_MISC_FW_ERROR)
50 #define WIL6210_IMC_MISC (WIL6210_IMC_MISC_NO_HALP | \
51 BIT_DMA_EP_MISC_ICR_HALP)
52 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
53 BIT_DMA_PSEUDO_CAUSE_TX | \
54 BIT_DMA_PSEUDO_CAUSE_MISC))
55
56 #if defined(CONFIG_WIL6210_ISR_COR)
57 /* configure to Clear-On-Read mode */
58 #define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
59 #define WIL_ICR_ICC_MISC_VALUE (0xF7FFFFFFUL)
60
61 static inline void wil_icr_clear(u32 x, void __iomem *addr)
62 {
63 }
64 #else /* defined(CONFIG_WIL6210_ISR_COR) */
65 /* configure to Write-1-to-Clear mode */
66 #define WIL_ICR_ICC_VALUE (0UL)
67 #define WIL_ICR_ICC_MISC_VALUE (0UL)
68
69 static inline void wil_icr_clear(u32 x, void __iomem *addr)
70 {
71 writel(x, addr);
72 }
73 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
74
75 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
76 {
77 u32 x = readl(addr);
78
79 wil_icr_clear(x, addr);
80
81 return x;
82 }
83
84 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
85 {
86 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS),
87 WIL6210_IRQ_DISABLE);
88 }
89
90 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
91 {
92 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS),
93 WIL6210_IRQ_DISABLE);
94 }
95
96 static void wil6210_mask_irq_misc(struct wil6210_priv *wil, bool mask_halp)
97 {
98 wil_dbg_irq(wil, "mask_irq_misc: mask_halp(%s)\n",
99 mask_halp ? "true" : "false");
100
101 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
102 mask_halp ? WIL6210_IRQ_DISABLE : WIL6210_IRQ_DISABLE_NO_HALP);
103 }
104
105 void wil6210_mask_halp(struct wil6210_priv *wil)
106 {
107 wil_dbg_irq(wil, "mask_halp\n");
108
109 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
110 BIT_DMA_EP_MISC_ICR_HALP);
111 }
112
113 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
114 {
115 wil_dbg_irq(wil, "mask_irq_pseudo\n");
116
117 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE);
118
119 clear_bit(wil_status_irqen, wil->status);
120 }
121
122 void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
123 {
124 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC),
125 WIL6210_IMC_TX);
126 }
127
128 void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
129 {
130 bool unmask_rx_htrsh = test_bit(wil_status_fwconnected, wil->status);
131
132 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC),
133 unmask_rx_htrsh ? WIL6210_IMC_RX : WIL6210_IMC_RX_NO_RX_HTRSH);
134 }
135
136 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil, bool unmask_halp)
137 {
138 wil_dbg_irq(wil, "unmask_irq_misc: unmask_halp(%s)\n",
139 unmask_halp ? "true" : "false");
140
141 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
142 unmask_halp ? WIL6210_IMC_MISC : WIL6210_IMC_MISC_NO_HALP);
143 }
144
145 static void wil6210_unmask_halp(struct wil6210_priv *wil)
146 {
147 wil_dbg_irq(wil, "unmask_halp\n");
148
149 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
150 BIT_DMA_EP_MISC_ICR_HALP);
151 }
152
153 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
154 {
155 wil_dbg_irq(wil, "unmask_irq_pseudo\n");
156
157 set_bit(wil_status_irqen, wil->status);
158
159 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK);
160 }
161
162 void wil_mask_irq(struct wil6210_priv *wil)
163 {
164 wil_dbg_irq(wil, "mask_irq\n");
165
166 wil6210_mask_irq_tx(wil);
167 wil6210_mask_irq_rx(wil);
168 wil6210_mask_irq_misc(wil, true);
169 wil6210_mask_irq_pseudo(wil);
170 }
171
172 void wil_unmask_irq(struct wil6210_priv *wil)
173 {
174 wil_dbg_irq(wil, "unmask_irq\n");
175
176 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC),
177 WIL_ICR_ICC_VALUE);
178 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC),
179 WIL_ICR_ICC_VALUE);
180 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC),
181 WIL_ICR_ICC_MISC_VALUE);
182
183 wil6210_unmask_irq_pseudo(wil);
184 wil6210_unmask_irq_tx(wil);
185 wil6210_unmask_irq_rx(wil);
186 wil6210_unmask_irq_misc(wil, true);
187 }
188
189 void wil_configure_interrupt_moderation(struct wil6210_priv *wil)
190 {
191 wil_dbg_irq(wil, "configure_interrupt_moderation\n");
192
193 /* disable interrupt moderation for monitor
194 * to get better timestamp precision
195 */
196 if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR)
197 return;
198
199 /* Disable and clear tx counter before (re)configuration */
200 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);
201 wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);
202 wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n",
203 wil->tx_max_burst_duration);
204 /* Configure TX max burst duration timer to use usec units */
205 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL,
206 BIT_DMA_ITR_TX_CNT_CTL_EN | BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL);
207
208 /* Disable and clear tx idle counter before (re)configuration */
209 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);
210 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);
211 wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n",
212 wil->tx_interframe_timeout);
213 /* Configure TX max burst duration timer to use usec units */
214 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |
215 BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL);
216
217 /* Disable and clear rx counter before (re)configuration */
218 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);
219 wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);
220 wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n",
221 wil->rx_max_burst_duration);
222 /* Configure TX max burst duration timer to use usec units */
223 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL,
224 BIT_DMA_ITR_RX_CNT_CTL_EN | BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL);
225
226 /* Disable and clear rx idle counter before (re)configuration */
227 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);
228 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);
229 wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n",
230 wil->rx_interframe_timeout);
231 /* Configure TX max burst duration timer to use usec units */
232 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |
233 BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL);
234 }
235
236 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
237 {
238 struct wil6210_priv *wil = cookie;
239 u32 isr = wil_ioread32_and_clear(wil->csr +
240 HOSTADDR(RGF_DMA_EP_RX_ICR) +
241 offsetof(struct RGF_ICR, ICR));
242 bool need_unmask = true;
243
244 trace_wil6210_irq_rx(isr);
245 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
246
247 if (unlikely(!isr)) {
248 wil_err_ratelimited(wil, "spurious IRQ: RX\n");
249 return IRQ_NONE;
250 }
251
252 wil6210_mask_irq_rx(wil);
253
254 /* RX_DONE and RX_HTRSH interrupts are the same if interrupt
255 * moderation is not used. Interrupt moderation may cause RX
256 * buffer overflow while RX_DONE is delayed. The required
257 * action is always the same - should empty the accumulated
258 * packets from the RX ring.
259 */
260 if (likely(isr & (BIT_DMA_EP_RX_ICR_RX_DONE |
261 BIT_DMA_EP_RX_ICR_RX_HTRSH))) {
262 wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n",
263 isr);
264
265 isr &= ~(BIT_DMA_EP_RX_ICR_RX_DONE |
266 BIT_DMA_EP_RX_ICR_RX_HTRSH);
267 if (likely(test_bit(wil_status_fwready, wil->status))) {
268 if (likely(test_bit(wil_status_napi_en, wil->status))) {
269 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
270 need_unmask = false;
271 napi_schedule(&wil->napi_rx);
272 } else {
273 wil_err_ratelimited(
274 wil,
275 "Got Rx interrupt while stopping interface\n");
276 }
277 } else {
278 wil_err_ratelimited(wil, "Got Rx interrupt while in reset\n");
279 }
280 }
281
282 if (unlikely(isr))
283 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
284
285 /* Rx IRQ will be enabled when NAPI processing finished */
286
287 atomic_inc(&wil->isr_count_rx);
288
289 if (unlikely(need_unmask))
290 wil6210_unmask_irq_rx(wil);
291
292 return IRQ_HANDLED;
293 }
294
295 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
296 {
297 struct wil6210_priv *wil = cookie;
298 u32 isr = wil_ioread32_and_clear(wil->csr +
299 HOSTADDR(RGF_DMA_EP_TX_ICR) +
300 offsetof(struct RGF_ICR, ICR));
301 bool need_unmask = true;
302
303 trace_wil6210_irq_tx(isr);
304 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
305
306 if (unlikely(!isr)) {
307 wil_err_ratelimited(wil, "spurious IRQ: TX\n");
308 return IRQ_NONE;
309 }
310
311 wil6210_mask_irq_tx(wil);
312
313 if (likely(isr & BIT_DMA_EP_TX_ICR_TX_DONE)) {
314 wil_dbg_irq(wil, "TX done\n");
315 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
316 /* clear also all VRING interrupts */
317 isr &= ~(BIT(25) - 1UL);
318 if (likely(test_bit(wil_status_fwready, wil->status))) {
319 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
320 need_unmask = false;
321 napi_schedule(&wil->napi_tx);
322 } else {
323 wil_err_ratelimited(wil, "Got Tx interrupt while in reset\n");
324 }
325 }
326
327 if (unlikely(isr))
328 wil_err_ratelimited(wil, "un-handled TX ISR bits 0x%08x\n",
329 isr);
330
331 /* Tx IRQ will be enabled when NAPI processing finished */
332
333 atomic_inc(&wil->isr_count_tx);
334
335 if (unlikely(need_unmask))
336 wil6210_unmask_irq_tx(wil);
337
338 return IRQ_HANDLED;
339 }
340
341 static void wil_notify_fw_error(struct wil6210_priv *wil)
342 {
343 struct device *dev = &wil_to_ndev(wil)->dev;
344 char *envp[3] = {
345 [0] = "SOURCE=wil6210",
346 [1] = "EVENT=FW_ERROR",
347 [2] = NULL,
348 };
349 wil_err(wil, "Notify about firmware error\n");
350 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
351 }
352
353 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
354 {
355 /* make shadow copy of registers that should not change on run time */
356 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
357 sizeof(struct wil6210_mbox_ctl));
358 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
359 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
360 }
361
362 static bool wil_validate_mbox_regs(struct wil6210_priv *wil)
363 {
364 size_t min_size = sizeof(struct wil6210_mbox_hdr) +
365 sizeof(struct wmi_cmd_hdr);
366
367 if (wil->mbox_ctl.rx.entry_size < min_size) {
368 wil_err(wil, "rx mbox entry too small (%d)\n",
369 wil->mbox_ctl.rx.entry_size);
370 return false;
371 }
372 if (wil->mbox_ctl.tx.entry_size < min_size) {
373 wil_err(wil, "tx mbox entry too small (%d)\n",
374 wil->mbox_ctl.tx.entry_size);
375 return false;
376 }
377
378 return true;
379 }
380
381 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
382 {
383 struct wil6210_priv *wil = cookie;
384 u32 isr = wil_ioread32_and_clear(wil->csr +
385 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
386 offsetof(struct RGF_ICR, ICR));
387
388 trace_wil6210_irq_misc(isr);
389 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
390
391 if (!isr) {
392 wil_err(wil, "spurious IRQ: MISC\n");
393 return IRQ_NONE;
394 }
395
396 wil6210_mask_irq_misc(wil, false);
397
398 if (isr & ISR_MISC_FW_ERROR) {
399 u32 fw_assert_code = wil_r(wil, wil->rgf_fw_assert_code_addr);
400 u32 ucode_assert_code =
401 wil_r(wil, wil->rgf_ucode_assert_code_addr);
402
403 wil_err(wil,
404 "Firmware error detected, assert codes FW 0x%08x, UCODE 0x%08x\n",
405 fw_assert_code, ucode_assert_code);
406 clear_bit(wil_status_fwready, wil->status);
407 /*
408 * do not clear @isr here - we do 2-nd part in thread
409 * there, user space get notified, and it should be done
410 * in non-atomic context
411 */
412 }
413
414 if (isr & ISR_MISC_FW_READY) {
415 wil_dbg_irq(wil, "IRQ: FW ready\n");
416 wil_cache_mbox_regs(wil);
417 if (wil_validate_mbox_regs(wil))
418 set_bit(wil_status_mbox_ready, wil->status);
419 /**
420 * Actual FW ready indicated by the
421 * WMI_FW_READY_EVENTID
422 */
423 isr &= ~ISR_MISC_FW_READY;
424 }
425
426 if (isr & BIT_DMA_EP_MISC_ICR_HALP) {
427 wil_dbg_irq(wil, "irq_misc: HALP IRQ invoked\n");
428 wil6210_mask_halp(wil);
429 isr &= ~BIT_DMA_EP_MISC_ICR_HALP;
430 complete(&wil->halp.comp);
431 }
432
433 wil->isr_misc = isr;
434
435 if (isr) {
436 return IRQ_WAKE_THREAD;
437 } else {
438 wil6210_unmask_irq_misc(wil, false);
439 return IRQ_HANDLED;
440 }
441 }
442
443 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
444 {
445 struct wil6210_priv *wil = cookie;
446 u32 isr = wil->isr_misc;
447
448 trace_wil6210_irq_misc_thread(isr);
449 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
450
451 if (isr & ISR_MISC_FW_ERROR) {
452 wil->recovery_state = fw_recovery_pending;
453 wil_fw_core_dump(wil);
454 wil_notify_fw_error(wil);
455 isr &= ~ISR_MISC_FW_ERROR;
456 if (wil->platform_ops.notify) {
457 wil_err(wil, "notify platform driver about FW crash");
458 wil->platform_ops.notify(wil->platform_handle,
459 WIL_PLATFORM_EVT_FW_CRASH);
460 } else {
461 wil_fw_error_recovery(wil);
462 }
463 }
464 if (isr & ISR_MISC_MBOX_EVT) {
465 wil_dbg_irq(wil, "MBOX event\n");
466 wmi_recv_cmd(wil);
467 isr &= ~ISR_MISC_MBOX_EVT;
468 }
469
470 if (isr)
471 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
472
473 wil->isr_misc = 0;
474
475 wil6210_unmask_irq_misc(wil, false);
476
477 return IRQ_HANDLED;
478 }
479
480 /**
481 * thread IRQ handler
482 */
483 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
484 {
485 struct wil6210_priv *wil = cookie;
486
487 wil_dbg_irq(wil, "Thread IRQ\n");
488 /* Discover real IRQ cause */
489 if (wil->isr_misc)
490 wil6210_irq_misc_thread(irq, cookie);
491
492 wil6210_unmask_irq_pseudo(wil);
493
494 if (wil->suspend_resp_rcvd) {
495 wil_dbg_irq(wil, "set suspend_resp_comp to true\n");
496 wil->suspend_resp_comp = true;
497 wake_up_interruptible(&wil->wq);
498 }
499
500 return IRQ_HANDLED;
501 }
502
503 /* DEBUG
504 * There is subtle bug in hardware that causes IRQ to raise when it should be
505 * masked. It is quite rare and hard to debug.
506 *
507 * Catch irq issue if it happens and print all I can.
508 */
509 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
510 {
511 if (!test_bit(wil_status_irqen, wil->status)) {
512 u32 icm_rx = wil_ioread32_and_clear(wil->csr +
513 HOSTADDR(RGF_DMA_EP_RX_ICR) +
514 offsetof(struct RGF_ICR, ICM));
515 u32 icr_rx = wil_ioread32_and_clear(wil->csr +
516 HOSTADDR(RGF_DMA_EP_RX_ICR) +
517 offsetof(struct RGF_ICR, ICR));
518 u32 imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR +
519 offsetof(struct RGF_ICR, IMV));
520 u32 icm_tx = wil_ioread32_and_clear(wil->csr +
521 HOSTADDR(RGF_DMA_EP_TX_ICR) +
522 offsetof(struct RGF_ICR, ICM));
523 u32 icr_tx = wil_ioread32_and_clear(wil->csr +
524 HOSTADDR(RGF_DMA_EP_TX_ICR) +
525 offsetof(struct RGF_ICR, ICR));
526 u32 imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR +
527 offsetof(struct RGF_ICR, IMV));
528 u32 icm_misc = wil_ioread32_and_clear(wil->csr +
529 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
530 offsetof(struct RGF_ICR, ICM));
531 u32 icr_misc = wil_ioread32_and_clear(wil->csr +
532 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
533 offsetof(struct RGF_ICR, ICR));
534 u32 imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR +
535 offsetof(struct RGF_ICR, IMV));
536
537 /* HALP interrupt can be unmasked when misc interrupts are
538 * masked
539 */
540 if (icr_misc & BIT_DMA_EP_MISC_ICR_HALP)
541 return 0;
542
543 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
544 "Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
545 "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
546 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
547 pseudo_cause,
548 icm_rx, icr_rx, imv_rx,
549 icm_tx, icr_tx, imv_tx,
550 icm_misc, icr_misc, imv_misc);
551
552 return -EINVAL;
553 }
554
555 return 0;
556 }
557
558 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
559 {
560 irqreturn_t rc = IRQ_HANDLED;
561 struct wil6210_priv *wil = cookie;
562 u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE);
563
564 /**
565 * pseudo_cause is Clear-On-Read, no need to ACK
566 */
567 if (unlikely((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff)))
568 return IRQ_NONE;
569
570 /* IRQ mask debug */
571 if (unlikely(wil6210_debug_irq_mask(wil, pseudo_cause)))
572 return IRQ_NONE;
573
574 trace_wil6210_irq_pseudo(pseudo_cause);
575 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
576
577 wil6210_mask_irq_pseudo(wil);
578
579 /* Discover real IRQ cause
580 * There are 2 possible phases for every IRQ:
581 * - hard IRQ handler called right here
582 * - threaded handler called later
583 *
584 * Hard IRQ handler reads and clears ISR.
585 *
586 * If threaded handler requested, hard IRQ handler
587 * returns IRQ_WAKE_THREAD and saves ISR register value
588 * for the threaded handler use.
589 *
590 * voting for wake thread - need at least 1 vote
591 */
592 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
593 (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
594 rc = IRQ_WAKE_THREAD;
595
596 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
597 (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
598 rc = IRQ_WAKE_THREAD;
599
600 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
601 (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
602 rc = IRQ_WAKE_THREAD;
603
604 /* if thread is requested, it will unmask IRQ */
605 if (rc != IRQ_WAKE_THREAD)
606 wil6210_unmask_irq_pseudo(wil);
607
608 return rc;
609 }
610
611 /* can't use wil_ioread32_and_clear because ICC value is not set yet */
612 static inline void wil_clear32(void __iomem *addr)
613 {
614 u32 x = readl(addr);
615
616 writel(x, addr);
617 }
618
619 void wil6210_clear_irq(struct wil6210_priv *wil)
620 {
621 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
622 offsetof(struct RGF_ICR, ICR));
623 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
624 offsetof(struct RGF_ICR, ICR));
625 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
626 offsetof(struct RGF_ICR, ICR));
627 wmb(); /* make sure write completed */
628 }
629
630 void wil6210_set_halp(struct wil6210_priv *wil)
631 {
632 wil_dbg_irq(wil, "set_halp\n");
633
634 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS),
635 BIT_DMA_EP_MISC_ICR_HALP);
636 }
637
638 void wil6210_clear_halp(struct wil6210_priv *wil)
639 {
640 wil_dbg_irq(wil, "clear_halp\n");
641
642 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR),
643 BIT_DMA_EP_MISC_ICR_HALP);
644 wil6210_unmask_halp(wil);
645 }
646
647 int wil6210_init_irq(struct wil6210_priv *wil, int irq, bool use_msi)
648 {
649 int rc;
650
651 wil_dbg_misc(wil, "init_irq: %s\n", use_msi ? "MSI" : "INTx");
652
653 rc = request_threaded_irq(irq, wil6210_hardirq,
654 wil6210_thread_irq,
655 use_msi ? 0 : IRQF_SHARED,
656 WIL_NAME, wil);
657 return rc;
658 }
659
660 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
661 {
662 wil_dbg_misc(wil, "fini_irq:\n");
663
664 wil_mask_irq(wil);
665 free_irq(irq, wil);
666 }
Linux with added FPC-III support