drivers/net/wireless/mediatek/mt7601u/initvals.h

   1 /*
   2  * (c) Copyright 2002-2010, Ralink Technology, Inc.
   3  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef __MT7601U_INITVALS_H
  16 #define __MT7601U_INITVALS_H
  17
  18 static const struct mt76_reg_pair bbp_common_vals[] = {
  19         {  65,  0x2c },
  20         {  66,  0x38 },
  21         {  68,  0x0b },
  22         {  69,  0x12 },
  23         {  70,  0x0a },
  24         {  73,  0x10 },
  25         {  81,  0x37 },
  26         {  82,  0x62 },
  27         {  83,  0x6a },
  28         {  84,  0x99 },
  29         {  86,  0x00 },
  30         {  91,  0x04 },
  31         {  92,  0x00 },
  32         { 103,  0x00 },
  33         { 105,  0x05 },
  34         { 106,  0x35 },
  35 };
  36
  37 static const struct mt76_reg_pair bbp_chip_vals[] = {
  38         {   1, 0x04 },  {   4, 0x40 },  {  20, 0x06 },  {  31, 0x08 },
  39         /* CCK Tx Control */
  40         { 178, 0xff },
  41         /* AGC/Sync controls */
  42         {  66, 0x14 },  {  68, 0x8b },  {  69, 0x12 },  {  70, 0x09 },
  43         {  73, 0x11 },  {  75, 0x60 },  {  76, 0x44 },  {  84, 0x9a },
  44         {  86, 0x38 },  {  91, 0x07 },  {  92, 0x02 },
  45         /* Rx Path Controls */
  46         {  99, 0x50 },  { 101, 0x00 },  { 103, 0xc0 },  { 104, 0x92 },
  47         { 105, 0x3c },  { 106, 0x03 },  { 128, 0x12 },
  48         /* Change RXWI content: Gain Report */
  49         { 142, 0x04 },  { 143, 0x37 },
  50         /* Change RXWI content: Antenna Report */
  51         { 142, 0x03 },  { 143, 0x99 },
  52         /* Calibration Index Register */
  53         /* CCK Receiver Control */
  54         { 160, 0xeb },  { 161, 0xc4 },  { 162, 0x77 },  { 163, 0xf9 },
  55         { 164, 0x88 },  { 165, 0x80 },  { 166, 0xff },  { 167, 0xe4 },
  56         /* Added AGC controls - these AGC/GLRT registers are accessed
  57          * through R195 and R196.
  58          */
  59         { 195, 0x00 },  { 196, 0x00 },
  60         { 195, 0x01 },  { 196, 0x04 },
  61         { 195, 0x02 },  { 196, 0x20 },
  62         { 195, 0x03 },  { 196, 0x0a },
  63         { 195, 0x06 },  { 196, 0x16 },
  64         { 195, 0x07 },  { 196, 0x05 },
  65         { 195, 0x08 },  { 196, 0x37 },
  66         { 195, 0x0a },  { 196, 0x15 },
  67         { 195, 0x0b },  { 196, 0x17 },
  68         { 195, 0x0c },  { 196, 0x06 },
  69         { 195, 0x0d },  { 196, 0x09 },
  70         { 195, 0x0e },  { 196, 0x05 },
  71         { 195, 0x0f },  { 196, 0x09 },
  72         { 195, 0x10 },  { 196, 0x20 },
  73         { 195, 0x20 },  { 196, 0x17 },
  74         { 195, 0x21 },  { 196, 0x06 },
  75         { 195, 0x22 },  { 196, 0x09 },
  76         { 195, 0x23 },  { 196, 0x17 },
  77         { 195, 0x24 },  { 196, 0x06 },
  78         { 195, 0x25 },  { 196, 0x09 },
  79         { 195, 0x26 },  { 196, 0x17 },
  80         { 195, 0x27 },  { 196, 0x06 },
  81         { 195, 0x28 },  { 196, 0x09 },
  82         { 195, 0x29 },  { 196, 0x05 },
  83         { 195, 0x2a },  { 196, 0x09 },
  84         { 195, 0x80 },  { 196, 0x8b },
  85         { 195, 0x81 },  { 196, 0x12 },
  86         { 195, 0x82 },  { 196, 0x09 },
  87         { 195, 0x83 },  { 196, 0x17 },
  88         { 195, 0x84 },  { 196, 0x11 },
  89         { 195, 0x85 },  { 196, 0x00 },
  90         { 195, 0x86 },  { 196, 0x00 },
  91         { 195, 0x87 },  { 196, 0x18 },
  92         { 195, 0x88 },  { 196, 0x60 },
  93         { 195, 0x89 },  { 196, 0x44 },
  94         { 195, 0x8a },  { 196, 0x8b },
  95         { 195, 0x8b },  { 196, 0x8b },
  96         { 195, 0x8c },  { 196, 0x8b },
  97         { 195, 0x8d },  { 196, 0x8b },
  98         { 195, 0x8e },  { 196, 0x09 },
  99         { 195, 0x8f },  { 196, 0x09 },
 100         { 195, 0x90 },  { 196, 0x09 },
 101         { 195, 0x91 },  { 196, 0x09 },
 102         { 195, 0x92 },  { 196, 0x11 },
 103         { 195, 0x93 },  { 196, 0x11 },
 104         { 195, 0x94 },  { 196, 0x11 },
 105         { 195, 0x95 },  { 196, 0x11 },
 106         /* PPAD */
 107         {  47, 0x80 },  {  60, 0x80 },  { 150, 0xd2 },  { 151, 0x32 },
 108         { 152, 0x23 },  { 153, 0x41 },  { 154, 0x00 },  { 155, 0x4f },
 109         { 253, 0x7e },  { 195, 0x30 },  { 196, 0x32 },  { 195, 0x31 },
 110         { 196, 0x23 },  { 195, 0x32 },  { 196, 0x45 },  { 195, 0x35 },
 111         { 196, 0x4a },  { 195, 0x36 },  { 196, 0x5a },  { 195, 0x37 },
 112         { 196, 0x5a },
 113 };
 114
 115 static const struct mt76_reg_pair mac_common_vals[] = {
 116         { MT_LEGACY_BASIC_RATE,         0x0000013f },
 117         { MT_HT_BASIC_RATE,             0x00008003 },
 118         { MT_MAC_SYS_CTRL,              0x00000000 },
 119         { MT_RX_FILTR_CFG,              0x00017f97 },
 120         { MT_BKOFF_SLOT_CFG,            0x00000209 },
 121         { MT_TX_SW_CFG0,                0x00000000 },
 122         { MT_TX_SW_CFG1,                0x00080606 },
 123         { MT_TX_LINK_CFG,               0x00001020 },
 124         { MT_TX_TIMEOUT_CFG,            0x000a2090 },
 125         { MT_MAX_LEN_CFG,               0x00003fff },
 126         { MT_PBF_TX_MAX_PCNT,           0x1fbf1f1f },
 127         { MT_PBF_RX_MAX_PCNT,           0x0000009f },
 128         { MT_TX_RETRY_CFG,              0x47d01f0f },
 129         { MT_AUTO_RSP_CFG,              0x00000013 },
 130         { MT_CCK_PROT_CFG,              0x05740003 },
 131         { MT_OFDM_PROT_CFG,             0x05740003 },
 132         { MT_MM40_PROT_CFG,             0x03f44084 },
 133         { MT_GF20_PROT_CFG,             0x01744004 },
 134         { MT_GF40_PROT_CFG,             0x03f44084 },
 135         { MT_MM20_PROT_CFG,             0x01744004 },
 136         { MT_TXOP_CTRL_CFG,             0x0000583f },
 137         { MT_TX_RTS_CFG,                0x01092b20 },
 138         { MT_EXP_ACK_TIME,              0x002400ca },
 139         { MT_TXOP_HLDR_ET,              0x00000002 },
 140         { MT_XIFS_TIME_CFG,             0x33a41010 },
 141         { MT_PWR_PIN_CFG,               0x00000000 },
 142 };
 143
 144 static const struct mt76_reg_pair mac_chip_vals[] = {
 145         { MT_TSO_CTRL,                  0x00006050 },
 146         { MT_BCN_OFFSET(0),             0x18100800 },
 147         { MT_BCN_OFFSET(1),             0x38302820 },
 148         { MT_PBF_SYS_CTRL,              0x00080c00 },
 149         { MT_PBF_CFG,                   0x7f723c1f },
 150         { MT_FCE_PSE_CTRL,              0x00000001 },
 151         { MT_PAUSE_ENABLE_CONTROL1,     0x00000000 },
 152         { MT_TX0_RF_GAIN_CORR,          0x003b0005 },
 153         { MT_TX0_RF_GAIN_ATTEN,         0x00006900 },
 154         { MT_TX0_BB_GAIN_ATTEN,         0x00000400 },
 155         { MT_TX_ALC_VGA3,               0x00060006 },
 156         { MT_TX_SW_CFG0,                0x00000402 },
 157         { MT_TX_SW_CFG1,                0x00000000 },
 158         { MT_TX_SW_CFG2,                0x00000000 },
 159         { MT_HEADER_TRANS_CTRL_REG,     0x00000000 },
 160         { MT_FCE_CSO,                   0x0000030f },
 161         { MT_FCE_PARAMETERS,            0x00256f0f },
 162 };
 163
 164 #endif