1 /* Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
2 * Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
3 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
4 * Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
5 * Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
6 * Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
7 * Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
8 * Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
9 * <http://rt2x00.serialmonkey.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
26 * Abstract: rt2800 MMIO device routines.
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/export.h>
34 #include "rt2x00mmio.h"
36 #include "rt2800lib.h"
37 #include "rt2800mmio.h"
40 * TX descriptor initialization
42 __le32
*rt2800mmio_get_txwi(struct queue_entry
*entry
)
44 return (__le32
*) entry
->skb
->data
;
46 EXPORT_SYMBOL_GPL(rt2800mmio_get_txwi
);
48 void rt2800mmio_write_tx_desc(struct queue_entry
*entry
,
49 struct txentry_desc
*txdesc
)
51 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
52 struct queue_entry_priv_mmio
*entry_priv
= entry
->priv_data
;
53 __le32
*txd
= entry_priv
->desc
;
55 const unsigned int txwi_size
= entry
->queue
->winfo_size
;
58 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
59 * must contains a TXWI structure + 802.11 header + padding + 802.11
60 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
61 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
62 * data. It means that LAST_SEC0 is always 0.
66 * Initialize TX descriptor
69 rt2x00_set_field32(&word
, TXD_W0_SD_PTR0
, skbdesc
->skb_dma
);
70 rt2x00_desc_write(txd
, 0, word
);
73 rt2x00_set_field32(&word
, TXD_W1_SD_LEN1
, entry
->skb
->len
);
74 rt2x00_set_field32(&word
, TXD_W1_LAST_SEC1
,
75 !test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
76 rt2x00_set_field32(&word
, TXD_W1_BURST
,
77 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
78 rt2x00_set_field32(&word
, TXD_W1_SD_LEN0
, txwi_size
);
79 rt2x00_set_field32(&word
, TXD_W1_LAST_SEC0
, 0);
80 rt2x00_set_field32(&word
, TXD_W1_DMA_DONE
, 0);
81 rt2x00_desc_write(txd
, 1, word
);
84 rt2x00_set_field32(&word
, TXD_W2_SD_PTR1
,
85 skbdesc
->skb_dma
+ txwi_size
);
86 rt2x00_desc_write(txd
, 2, word
);
89 rt2x00_set_field32(&word
, TXD_W3_WIV
,
90 !test_bit(ENTRY_TXD_ENCRYPT_IV
, &txdesc
->flags
));
91 rt2x00_set_field32(&word
, TXD_W3_QSEL
, 2);
92 rt2x00_desc_write(txd
, 3, word
);
95 * Register descriptor details in skb frame descriptor.
98 skbdesc
->desc_len
= TXD_DESC_SIZE
;
100 EXPORT_SYMBOL_GPL(rt2800mmio_write_tx_desc
);
103 * RX control handlers
105 void rt2800mmio_fill_rxdone(struct queue_entry
*entry
,
106 struct rxdone_entry_desc
*rxdesc
)
108 struct queue_entry_priv_mmio
*entry_priv
= entry
->priv_data
;
109 __le32
*rxd
= entry_priv
->desc
;
112 word
= rt2x00_desc_read(rxd
, 3);
114 if (rt2x00_get_field32(word
, RXD_W3_CRC_ERROR
))
115 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
118 * Unfortunately we don't know the cipher type used during
119 * decryption. This prevents us from correct providing
120 * correct statistics through debugfs.
122 rxdesc
->cipher_status
= rt2x00_get_field32(word
, RXD_W3_CIPHER_ERROR
);
124 if (rt2x00_get_field32(word
, RXD_W3_DECRYPTED
)) {
126 * Hardware has stripped IV/EIV data from 802.11 frame during
127 * decryption. Unfortunately the descriptor doesn't contain
128 * any fields with the EIV/IV data either, so they can't
129 * be restored by rt2x00lib.
131 rxdesc
->flags
|= RX_FLAG_IV_STRIPPED
;
134 * The hardware has already checked the Michael Mic and has
135 * stripped it from the frame. Signal this to mac80211.
137 rxdesc
->flags
|= RX_FLAG_MMIC_STRIPPED
;
139 if (rxdesc
->cipher_status
== RX_CRYPTO_SUCCESS
) {
140 rxdesc
->flags
|= RX_FLAG_DECRYPTED
;
141 } else if (rxdesc
->cipher_status
== RX_CRYPTO_FAIL_MIC
) {
143 * In order to check the Michael Mic, the packet must have
144 * been decrypted. Mac80211 doesnt check the MMIC failure
145 * flag to initiate MMIC countermeasures if the decoded flag
148 rxdesc
->flags
|= RX_FLAG_DECRYPTED
;
150 rxdesc
->flags
|= RX_FLAG_MMIC_ERROR
;
154 if (rt2x00_get_field32(word
, RXD_W3_MY_BSS
))
155 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
157 if (rt2x00_get_field32(word
, RXD_W3_L2PAD
))
158 rxdesc
->dev_flags
|= RXDONE_L2PAD
;
161 * Process the RXWI structure that is at the start of the buffer.
163 rt2800_process_rxwi(entry
, rxdesc
);
165 EXPORT_SYMBOL_GPL(rt2800mmio_fill_rxdone
);
168 * Interrupt functions.
170 static void rt2800mmio_wakeup(struct rt2x00_dev
*rt2x00dev
)
172 struct ieee80211_conf conf
= { .flags
= 0 };
173 struct rt2x00lib_conf libconf
= { .conf
= &conf
};
175 rt2800_config(rt2x00dev
, &libconf
, IEEE80211_CONF_CHANGE_PS
);
178 static bool rt2800mmio_txdone_entry_check(struct queue_entry
*entry
, u32 status
)
184 wcid
= rt2x00_get_field32(status
, TX_STA_FIFO_WCID
);
186 txwi
= rt2800_drv_get_txwi(entry
);
187 word
= rt2x00_desc_read(txwi
, 1);
188 tx_wcid
= rt2x00_get_field32(word
, TXWI_W1_WIRELESS_CLI_ID
);
190 return (tx_wcid
== wcid
);
193 static bool rt2800mmio_txdone_find_entry(struct queue_entry
*entry
, void *data
)
195 u32 status
= *(u32
*)data
;
198 * rt2800pci hardware might reorder frames when exchanging traffic
199 * with multiple BA enabled STAs.
201 * For example, a tx queue
202 * [ STA1 | STA2 | STA1 | STA2 ]
203 * can result in tx status reports
204 * [ STA1 | STA1 | STA2 | STA2 ]
205 * when the hw decides to aggregate the frames for STA1 into one AMPDU.
207 * To mitigate this effect, associate the tx status to the first frame
208 * in the tx queue with a matching wcid.
210 if (rt2800mmio_txdone_entry_check(entry
, status
) &&
211 !test_bit(ENTRY_DATA_STATUS_SET
, &entry
->flags
)) {
213 * Got a matching frame, associate the tx status with
216 entry
->status
= status
;
217 set_bit(ENTRY_DATA_STATUS_SET
, &entry
->flags
);
221 /* Check the next frame */
225 static bool rt2800mmio_txdone_match_first(struct queue_entry
*entry
, void *data
)
227 u32 status
= *(u32
*)data
;
230 * Find the first frame without tx status and assign this status to it
231 * regardless if it matches or not.
233 if (!test_bit(ENTRY_DATA_STATUS_SET
, &entry
->flags
)) {
235 * Got a matching frame, associate the tx status with
238 entry
->status
= status
;
239 set_bit(ENTRY_DATA_STATUS_SET
, &entry
->flags
);
243 /* Check the next frame */
246 static bool rt2800mmio_txdone_release_entries(struct queue_entry
*entry
,
249 if (test_bit(ENTRY_DATA_STATUS_SET
, &entry
->flags
)) {
250 rt2800_txdone_entry(entry
, entry
->status
,
251 rt2800mmio_get_txwi(entry
), true);
255 /* No more frames to release */
259 static bool rt2800mmio_txdone(struct rt2x00_dev
*rt2x00dev
)
261 struct data_queue
*queue
;
264 int max_tx_done
= 16;
266 while (kfifo_get(&rt2x00dev
->txstatus_fifo
, &status
)) {
267 qid
= rt2x00_get_field32(status
, TX_STA_FIFO_PID_QUEUE
);
268 if (unlikely(qid
>= QID_RX
)) {
270 * Unknown queue, this shouldn't happen. Just drop
273 rt2x00_warn(rt2x00dev
, "Got TX status report with unexpected pid %u, dropping\n",
278 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, qid
);
279 if (unlikely(queue
== NULL
)) {
281 * The queue is NULL, this shouldn't happen. Stop
282 * processing here and drop the tx status
284 rt2x00_warn(rt2x00dev
, "Got TX status for an unavailable queue %u, dropping\n",
289 if (unlikely(rt2x00queue_empty(queue
))) {
291 * The queue is empty. Stop processing here
292 * and drop the tx status.
294 rt2x00_warn(rt2x00dev
, "Got TX status for an empty queue %u, dropping\n",
300 * Let's associate this tx status with the first
303 if (!rt2x00queue_for_each_entry(queue
, Q_INDEX_DONE
,
305 rt2800mmio_txdone_find_entry
)) {
307 * We cannot match the tx status to any frame, so just
310 if (!rt2x00queue_for_each_entry(queue
, Q_INDEX_DONE
,
312 rt2800mmio_txdone_match_first
)) {
313 rt2x00_warn(rt2x00dev
, "No frame found for TX status on queue %u, dropping\n",
320 * Release all frames with a valid tx status.
322 rt2x00queue_for_each_entry(queue
, Q_INDEX_DONE
,
324 rt2800mmio_txdone_release_entries
);
326 if (--max_tx_done
== 0)
333 static inline void rt2800mmio_enable_interrupt(struct rt2x00_dev
*rt2x00dev
,
334 struct rt2x00_field32 irq_field
)
339 * Enable a single interrupt. The interrupt mask register
340 * access needs locking.
342 spin_lock_irq(&rt2x00dev
->irqmask_lock
);
343 reg
= rt2x00mmio_register_read(rt2x00dev
, INT_MASK_CSR
);
344 rt2x00_set_field32(®
, irq_field
, 1);
345 rt2x00mmio_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
346 spin_unlock_irq(&rt2x00dev
->irqmask_lock
);
349 void rt2800mmio_txstatus_tasklet(unsigned long data
)
351 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
352 if (rt2800mmio_txdone(rt2x00dev
))
353 tasklet_schedule(&rt2x00dev
->txstatus_tasklet
);
356 * No need to enable the tx status interrupt here as we always
357 * leave it enabled to minimize the possibility of a tx status
358 * register overflow. See comment in interrupt handler.
361 EXPORT_SYMBOL_GPL(rt2800mmio_txstatus_tasklet
);
363 void rt2800mmio_pretbtt_tasklet(unsigned long data
)
365 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
366 rt2x00lib_pretbtt(rt2x00dev
);
367 if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
368 rt2800mmio_enable_interrupt(rt2x00dev
, INT_MASK_CSR_PRE_TBTT
);
370 EXPORT_SYMBOL_GPL(rt2800mmio_pretbtt_tasklet
);
372 void rt2800mmio_tbtt_tasklet(unsigned long data
)
374 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
375 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
378 rt2x00lib_beacondone(rt2x00dev
);
380 if (rt2x00dev
->intf_ap_count
) {
382 * The rt2800pci hardware tbtt timer is off by 1us per tbtt
383 * causing beacon skew and as a result causing problems with
384 * some powersaving clients over time. Shorten the beacon
385 * interval every 64 beacons by 64us to mitigate this effect.
387 if (drv_data
->tbtt_tick
== (BCN_TBTT_OFFSET
- 2)) {
388 reg
= rt2x00mmio_register_read(rt2x00dev
, BCN_TIME_CFG
);
389 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
390 (rt2x00dev
->beacon_int
* 16) - 1);
391 rt2x00mmio_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
392 } else if (drv_data
->tbtt_tick
== (BCN_TBTT_OFFSET
- 1)) {
393 reg
= rt2x00mmio_register_read(rt2x00dev
, BCN_TIME_CFG
);
394 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
395 (rt2x00dev
->beacon_int
* 16));
396 rt2x00mmio_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
398 drv_data
->tbtt_tick
++;
399 drv_data
->tbtt_tick
%= BCN_TBTT_OFFSET
;
402 if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
403 rt2800mmio_enable_interrupt(rt2x00dev
, INT_MASK_CSR_TBTT
);
405 EXPORT_SYMBOL_GPL(rt2800mmio_tbtt_tasklet
);
407 void rt2800mmio_rxdone_tasklet(unsigned long data
)
409 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
410 if (rt2x00mmio_rxdone(rt2x00dev
))
411 tasklet_schedule(&rt2x00dev
->rxdone_tasklet
);
412 else if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
413 rt2800mmio_enable_interrupt(rt2x00dev
, INT_MASK_CSR_RX_DONE
);
415 EXPORT_SYMBOL_GPL(rt2800mmio_rxdone_tasklet
);
417 void rt2800mmio_autowake_tasklet(unsigned long data
)
419 struct rt2x00_dev
*rt2x00dev
= (struct rt2x00_dev
*)data
;
420 rt2800mmio_wakeup(rt2x00dev
);
421 if (test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
422 rt2800mmio_enable_interrupt(rt2x00dev
,
423 INT_MASK_CSR_AUTO_WAKEUP
);
425 EXPORT_SYMBOL_GPL(rt2800mmio_autowake_tasklet
);
427 static void rt2800mmio_txstatus_interrupt(struct rt2x00_dev
*rt2x00dev
)
433 * The TX_FIFO_STATUS interrupt needs special care. We should
434 * read TX_STA_FIFO but we should do it immediately as otherwise
435 * the register can overflow and we would lose status reports.
437 * Hence, read the TX_STA_FIFO register and copy all tx status
438 * reports into a kernel FIFO which is handled in the txstatus
439 * tasklet. We use a tasklet to process the tx status reports
440 * because we can schedule the tasklet multiple times (when the
441 * interrupt fires again during tx status processing).
443 * Furthermore we don't disable the TX_FIFO_STATUS
444 * interrupt here but leave it enabled so that the TX_STA_FIFO
445 * can also be read while the tx status tasklet gets executed.
447 * Since we have only one producer and one consumer we don't
448 * need to lock the kfifo.
450 for (i
= 0; i
< rt2x00dev
->tx
->limit
; i
++) {
451 status
= rt2x00mmio_register_read(rt2x00dev
, TX_STA_FIFO
);
453 if (!rt2x00_get_field32(status
, TX_STA_FIFO_VALID
))
456 if (!kfifo_put(&rt2x00dev
->txstatus_fifo
, status
)) {
457 rt2x00_warn(rt2x00dev
, "TX status FIFO overrun, drop tx status report\n");
462 /* Schedule the tasklet for processing the tx status. */
463 tasklet_schedule(&rt2x00dev
->txstatus_tasklet
);
466 irqreturn_t
rt2800mmio_interrupt(int irq
, void *dev_instance
)
468 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
471 /* Read status and ACK all interrupts */
472 reg
= rt2x00mmio_register_read(rt2x00dev
, INT_SOURCE_CSR
);
473 rt2x00mmio_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
478 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
482 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
483 * for interrupts and interrupt masks we can just use the value of
484 * INT_SOURCE_CSR to create the interrupt mask.
488 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TX_FIFO_STATUS
)) {
489 rt2800mmio_txstatus_interrupt(rt2x00dev
);
491 * Never disable the TX_FIFO_STATUS interrupt.
493 rt2x00_set_field32(&mask
, INT_MASK_CSR_TX_FIFO_STATUS
, 1);
496 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_PRE_TBTT
))
497 tasklet_hi_schedule(&rt2x00dev
->pretbtt_tasklet
);
499 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TBTT
))
500 tasklet_hi_schedule(&rt2x00dev
->tbtt_tasklet
);
502 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_RX_DONE
))
503 tasklet_schedule(&rt2x00dev
->rxdone_tasklet
);
505 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_AUTO_WAKEUP
))
506 tasklet_schedule(&rt2x00dev
->autowake_tasklet
);
509 * Disable all interrupts for which a tasklet was scheduled right now,
510 * the tasklet will reenable the appropriate interrupts.
512 spin_lock(&rt2x00dev
->irqmask_lock
);
513 reg
= rt2x00mmio_register_read(rt2x00dev
, INT_MASK_CSR
);
515 rt2x00mmio_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
516 spin_unlock(&rt2x00dev
->irqmask_lock
);
520 EXPORT_SYMBOL_GPL(rt2800mmio_interrupt
);
522 void rt2800mmio_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
523 enum dev_state state
)
529 * When interrupts are being enabled, the interrupt registers
530 * should clear the register to assure a clean state.
532 if (state
== STATE_RADIO_IRQ_ON
) {
533 reg
= rt2x00mmio_register_read(rt2x00dev
, INT_SOURCE_CSR
);
534 rt2x00mmio_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
537 spin_lock_irqsave(&rt2x00dev
->irqmask_lock
, flags
);
539 if (state
== STATE_RADIO_IRQ_ON
) {
540 rt2x00_set_field32(®
, INT_MASK_CSR_RX_DONE
, 1);
541 rt2x00_set_field32(®
, INT_MASK_CSR_TBTT
, 1);
542 rt2x00_set_field32(®
, INT_MASK_CSR_PRE_TBTT
, 1);
543 rt2x00_set_field32(®
, INT_MASK_CSR_TX_FIFO_STATUS
, 1);
544 rt2x00_set_field32(®
, INT_MASK_CSR_AUTO_WAKEUP
, 1);
546 rt2x00mmio_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
547 spin_unlock_irqrestore(&rt2x00dev
->irqmask_lock
, flags
);
549 if (state
== STATE_RADIO_IRQ_OFF
) {
551 * Wait for possibly running tasklets to finish.
553 tasklet_kill(&rt2x00dev
->txstatus_tasklet
);
554 tasklet_kill(&rt2x00dev
->rxdone_tasklet
);
555 tasklet_kill(&rt2x00dev
->autowake_tasklet
);
556 tasklet_kill(&rt2x00dev
->tbtt_tasklet
);
557 tasklet_kill(&rt2x00dev
->pretbtt_tasklet
);
560 EXPORT_SYMBOL_GPL(rt2800mmio_toggle_irq
);
565 void rt2800mmio_start_queue(struct data_queue
*queue
)
567 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
570 switch (queue
->qid
) {
572 reg
= rt2x00mmio_register_read(rt2x00dev
, MAC_SYS_CTRL
);
573 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
574 rt2x00mmio_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
577 reg
= rt2x00mmio_register_read(rt2x00dev
, BCN_TIME_CFG
);
578 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 1);
579 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 1);
580 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
581 rt2x00mmio_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
583 reg
= rt2x00mmio_register_read(rt2x00dev
, INT_TIMER_EN
);
584 rt2x00_set_field32(®
, INT_TIMER_EN_PRE_TBTT_TIMER
, 1);
585 rt2x00mmio_register_write(rt2x00dev
, INT_TIMER_EN
, reg
);
591 EXPORT_SYMBOL_GPL(rt2800mmio_start_queue
);
593 void rt2800mmio_kick_queue(struct data_queue
*queue
)
595 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
596 struct queue_entry
*entry
;
598 switch (queue
->qid
) {
603 entry
= rt2x00queue_get_entry(queue
, Q_INDEX
);
604 rt2x00mmio_register_write(rt2x00dev
, TX_CTX_IDX(queue
->qid
),
608 entry
= rt2x00queue_get_entry(queue
, Q_INDEX
);
609 rt2x00mmio_register_write(rt2x00dev
, TX_CTX_IDX(5),
616 EXPORT_SYMBOL_GPL(rt2800mmio_kick_queue
);
618 void rt2800mmio_stop_queue(struct data_queue
*queue
)
620 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
623 switch (queue
->qid
) {
625 reg
= rt2x00mmio_register_read(rt2x00dev
, MAC_SYS_CTRL
);
626 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
627 rt2x00mmio_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
630 reg
= rt2x00mmio_register_read(rt2x00dev
, BCN_TIME_CFG
);
631 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
632 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
633 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
634 rt2x00mmio_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
636 reg
= rt2x00mmio_register_read(rt2x00dev
, INT_TIMER_EN
);
637 rt2x00_set_field32(®
, INT_TIMER_EN_PRE_TBTT_TIMER
, 0);
638 rt2x00mmio_register_write(rt2x00dev
, INT_TIMER_EN
, reg
);
641 * Wait for current invocation to finish. The tasklet
642 * won't be scheduled anymore afterwards since we disabled
643 * the TBTT and PRE TBTT timer.
645 tasklet_kill(&rt2x00dev
->tbtt_tasklet
);
646 tasklet_kill(&rt2x00dev
->pretbtt_tasklet
);
653 EXPORT_SYMBOL_GPL(rt2800mmio_stop_queue
);
655 void rt2800mmio_queue_init(struct data_queue
*queue
)
657 struct rt2x00_dev
*rt2x00dev
= queue
->rt2x00dev
;
658 unsigned short txwi_size
, rxwi_size
;
660 rt2800_get_txwi_rxwi_size(rt2x00dev
, &txwi_size
, &rxwi_size
);
662 switch (queue
->qid
) {
665 queue
->data_size
= AGGREGATION_SIZE
;
666 queue
->desc_size
= RXD_DESC_SIZE
;
667 queue
->winfo_size
= rxwi_size
;
668 queue
->priv_size
= sizeof(struct queue_entry_priv_mmio
);
676 queue
->data_size
= AGGREGATION_SIZE
;
677 queue
->desc_size
= TXD_DESC_SIZE
;
678 queue
->winfo_size
= txwi_size
;
679 queue
->priv_size
= sizeof(struct queue_entry_priv_mmio
);
684 queue
->data_size
= 0; /* No DMA required for beacons */
685 queue
->desc_size
= TXD_DESC_SIZE
;
686 queue
->winfo_size
= txwi_size
;
687 queue
->priv_size
= sizeof(struct queue_entry_priv_mmio
);
697 EXPORT_SYMBOL_GPL(rt2800mmio_queue_init
);
700 * Initialization functions.
702 bool rt2800mmio_get_entry_state(struct queue_entry
*entry
)
704 struct queue_entry_priv_mmio
*entry_priv
= entry
->priv_data
;
707 if (entry
->queue
->qid
== QID_RX
) {
708 word
= rt2x00_desc_read(entry_priv
->desc
, 1);
710 return (!rt2x00_get_field32(word
, RXD_W1_DMA_DONE
));
712 word
= rt2x00_desc_read(entry_priv
->desc
, 1);
714 return (!rt2x00_get_field32(word
, TXD_W1_DMA_DONE
));
717 EXPORT_SYMBOL_GPL(rt2800mmio_get_entry_state
);
719 void rt2800mmio_clear_entry(struct queue_entry
*entry
)
721 struct queue_entry_priv_mmio
*entry_priv
= entry
->priv_data
;
722 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
723 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
726 if (entry
->queue
->qid
== QID_RX
) {
727 word
= rt2x00_desc_read(entry_priv
->desc
, 0);
728 rt2x00_set_field32(&word
, RXD_W0_SDP0
, skbdesc
->skb_dma
);
729 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
731 word
= rt2x00_desc_read(entry_priv
->desc
, 1);
732 rt2x00_set_field32(&word
, RXD_W1_DMA_DONE
, 0);
733 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
736 * Set RX IDX in register to inform hardware that we have
737 * handled this entry and it is available for reuse again.
739 rt2x00mmio_register_write(rt2x00dev
, RX_CRX_IDX
,
742 word
= rt2x00_desc_read(entry_priv
->desc
, 1);
743 rt2x00_set_field32(&word
, TXD_W1_DMA_DONE
, 1);
744 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
747 EXPORT_SYMBOL_GPL(rt2800mmio_clear_entry
);
749 int rt2800mmio_init_queues(struct rt2x00_dev
*rt2x00dev
)
751 struct queue_entry_priv_mmio
*entry_priv
;
754 * Initialize registers.
756 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
757 rt2x00mmio_register_write(rt2x00dev
, TX_BASE_PTR0
,
758 entry_priv
->desc_dma
);
759 rt2x00mmio_register_write(rt2x00dev
, TX_MAX_CNT0
,
760 rt2x00dev
->tx
[0].limit
);
761 rt2x00mmio_register_write(rt2x00dev
, TX_CTX_IDX0
, 0);
762 rt2x00mmio_register_write(rt2x00dev
, TX_DTX_IDX0
, 0);
764 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
765 rt2x00mmio_register_write(rt2x00dev
, TX_BASE_PTR1
,
766 entry_priv
->desc_dma
);
767 rt2x00mmio_register_write(rt2x00dev
, TX_MAX_CNT1
,
768 rt2x00dev
->tx
[1].limit
);
769 rt2x00mmio_register_write(rt2x00dev
, TX_CTX_IDX1
, 0);
770 rt2x00mmio_register_write(rt2x00dev
, TX_DTX_IDX1
, 0);
772 entry_priv
= rt2x00dev
->tx
[2].entries
[0].priv_data
;
773 rt2x00mmio_register_write(rt2x00dev
, TX_BASE_PTR2
,
774 entry_priv
->desc_dma
);
775 rt2x00mmio_register_write(rt2x00dev
, TX_MAX_CNT2
,
776 rt2x00dev
->tx
[2].limit
);
777 rt2x00mmio_register_write(rt2x00dev
, TX_CTX_IDX2
, 0);
778 rt2x00mmio_register_write(rt2x00dev
, TX_DTX_IDX2
, 0);
780 entry_priv
= rt2x00dev
->tx
[3].entries
[0].priv_data
;
781 rt2x00mmio_register_write(rt2x00dev
, TX_BASE_PTR3
,
782 entry_priv
->desc_dma
);
783 rt2x00mmio_register_write(rt2x00dev
, TX_MAX_CNT3
,
784 rt2x00dev
->tx
[3].limit
);
785 rt2x00mmio_register_write(rt2x00dev
, TX_CTX_IDX3
, 0);
786 rt2x00mmio_register_write(rt2x00dev
, TX_DTX_IDX3
, 0);
788 rt2x00mmio_register_write(rt2x00dev
, TX_BASE_PTR4
, 0);
789 rt2x00mmio_register_write(rt2x00dev
, TX_MAX_CNT4
, 0);
790 rt2x00mmio_register_write(rt2x00dev
, TX_CTX_IDX4
, 0);
791 rt2x00mmio_register_write(rt2x00dev
, TX_DTX_IDX4
, 0);
793 rt2x00mmio_register_write(rt2x00dev
, TX_BASE_PTR5
, 0);
794 rt2x00mmio_register_write(rt2x00dev
, TX_MAX_CNT5
, 0);
795 rt2x00mmio_register_write(rt2x00dev
, TX_CTX_IDX5
, 0);
796 rt2x00mmio_register_write(rt2x00dev
, TX_DTX_IDX5
, 0);
798 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
799 rt2x00mmio_register_write(rt2x00dev
, RX_BASE_PTR
,
800 entry_priv
->desc_dma
);
801 rt2x00mmio_register_write(rt2x00dev
, RX_MAX_CNT
,
802 rt2x00dev
->rx
[0].limit
);
803 rt2x00mmio_register_write(rt2x00dev
, RX_CRX_IDX
,
804 rt2x00dev
->rx
[0].limit
- 1);
805 rt2x00mmio_register_write(rt2x00dev
, RX_DRX_IDX
, 0);
807 rt2800_disable_wpdma(rt2x00dev
);
809 rt2x00mmio_register_write(rt2x00dev
, DELAY_INT_CFG
, 0);
813 EXPORT_SYMBOL_GPL(rt2800mmio_init_queues
);
815 int rt2800mmio_init_registers(struct rt2x00_dev
*rt2x00dev
)
822 reg
= rt2x00mmio_register_read(rt2x00dev
, WPDMA_RST_IDX
);
823 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX0
, 1);
824 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX1
, 1);
825 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX2
, 1);
826 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX3
, 1);
827 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX4
, 1);
828 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX5
, 1);
829 rt2x00_set_field32(®
, WPDMA_RST_IDX_DRX_IDX0
, 1);
830 rt2x00mmio_register_write(rt2x00dev
, WPDMA_RST_IDX
, reg
);
832 rt2x00mmio_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e1f);
833 rt2x00mmio_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e00);
835 if (rt2x00_is_pcie(rt2x00dev
) &&
836 (rt2x00_rt(rt2x00dev
, RT3090
) ||
837 rt2x00_rt(rt2x00dev
, RT3390
) ||
838 rt2x00_rt(rt2x00dev
, RT3572
) ||
839 rt2x00_rt(rt2x00dev
, RT3593
) ||
840 rt2x00_rt(rt2x00dev
, RT5390
) ||
841 rt2x00_rt(rt2x00dev
, RT5392
) ||
842 rt2x00_rt(rt2x00dev
, RT5592
))) {
843 reg
= rt2x00mmio_register_read(rt2x00dev
, AUX_CTRL
);
844 rt2x00_set_field32(®
, AUX_CTRL_FORCE_PCIE_CLK
, 1);
845 rt2x00_set_field32(®
, AUX_CTRL_WAKE_PCIE_EN
, 1);
846 rt2x00mmio_register_write(rt2x00dev
, AUX_CTRL
, reg
);
849 rt2x00mmio_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
852 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_CSR
, 1);
853 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_BBP
, 1);
854 rt2x00mmio_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
856 rt2x00mmio_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
860 EXPORT_SYMBOL_GPL(rt2800mmio_init_registers
);
863 * Device state switch handlers.
865 int rt2800mmio_enable_radio(struct rt2x00_dev
*rt2x00dev
)
867 /* Wait for DMA, ignore error until we initialize queues. */
868 rt2800_wait_wpdma_ready(rt2x00dev
);
870 if (unlikely(rt2800mmio_init_queues(rt2x00dev
)))
873 return rt2800_enable_radio(rt2x00dev
);
875 EXPORT_SYMBOL_GPL(rt2800mmio_enable_radio
);
877 MODULE_AUTHOR(DRV_PROJECT
);
878 MODULE_VERSION(DRV_VERSION
);
879 MODULE_DESCRIPTION("rt2800 MMIO library");
880 MODULE_LICENSE("GPL");