drivers/pci/dwc/pcie-designware-ep.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * Synopsys DesignWare PCIe Endpoint controller driver
   4  *
   5  * Copyright (C) 2017 Texas Instruments
   6  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   7  */
   8
   9 #include <linux/of.h>
  10
  11 #include "pcie-designware.h"
  12 #include <linux/pci-epc.h>
  13 #include <linux/pci-epf.h>
  14
  15 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
  16 {
  17         struct pci_epc *epc = ep->epc;
  18
  19         pci_epc_linkup(epc);
  20 }
  21
  22 void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
  23 {
  24         u32 reg;
  25
  26         reg = PCI_BASE_ADDRESS_0 + (4 * bar);
  27         dw_pcie_dbi_ro_wr_en(pci);
  28         dw_pcie_writel_dbi2(pci, reg, 0x0);
  29         dw_pcie_writel_dbi(pci, reg, 0x0);
  30         dw_pcie_dbi_ro_wr_dis(pci);
  31 }
  32
  33 static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
  34                                    struct pci_epf_header *hdr)
  35 {
  36         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
  37         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
  38
  39         dw_pcie_dbi_ro_wr_en(pci);
  40         dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
  41         dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
  42         dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
  43         dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code);
  44         dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE,
  45                            hdr->subclass_code | hdr->baseclass_code << 8);
  46         dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE,
  47                            hdr->cache_line_size);
  48         dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID,
  49                            hdr->subsys_vendor_id);
  50         dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
  51         dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
  52                            hdr->interrupt_pin);
  53         dw_pcie_dbi_ro_wr_dis(pci);
  54
  55         return 0;
  56 }
  57
  58 static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
  59                                   dma_addr_t cpu_addr,
  60                                   enum dw_pcie_as_type as_type)
  61 {
  62         int ret;
  63         u32 free_win;
  64         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
  65
  66         free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
  67         if (free_win >= ep->num_ib_windows) {
  68                 dev_err(pci->dev, "no free inbound window\n");
  69                 return -EINVAL;
  70         }
  71
  72         ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
  73                                        as_type);
  74         if (ret < 0) {
  75                 dev_err(pci->dev, "Failed to program IB window\n");
  76                 return ret;
  77         }
  78
  79         ep->bar_to_atu[bar] = free_win;
  80         set_bit(free_win, ep->ib_window_map);
  81
  82         return 0;
  83 }
  84
  85 static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
  86                                    u64 pci_addr, size_t size)
  87 {
  88         u32 free_win;
  89         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
  90
  91         free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
  92         if (free_win >= ep->num_ob_windows) {
  93                 dev_err(pci->dev, "no free outbound window\n");
  94                 return -EINVAL;
  95         }
  96
  97         dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
  98                                   phys_addr, pci_addr, size);
  99
 100         set_bit(free_win, ep->ob_window_map);
 101         ep->outbound_addr[free_win] = phys_addr;
 102
 103         return 0;
 104 }
 105
 106 static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
 107                                  enum pci_barno bar)
 108 {
 109         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
 110         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 111         u32 atu_index = ep->bar_to_atu[bar];
 112
 113         dw_pcie_ep_reset_bar(pci, bar);
 114
 115         dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
 116         clear_bit(atu_index, ep->ib_window_map);
 117 }
 118
 119 static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
 120                               enum pci_barno bar,
 121                               dma_addr_t bar_phys, size_t size, int flags)
 122 {
 123         int ret;
 124         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
 125         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 126         enum dw_pcie_as_type as_type;
 127         u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
 128
 129         if (!(flags & PCI_BASE_ADDRESS_SPACE))
 130                 as_type = DW_PCIE_AS_MEM;
 131         else
 132                 as_type = DW_PCIE_AS_IO;
 133
 134         ret = dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);
 135         if (ret)
 136                 return ret;
 137
 138         dw_pcie_dbi_ro_wr_en(pci);
 139         dw_pcie_writel_dbi2(pci, reg, size - 1);
 140         dw_pcie_writel_dbi(pci, reg, flags);
 141         dw_pcie_dbi_ro_wr_dis(pci);
 142
 143         return 0;
 144 }
 145
 146 static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
 147                               u32 *atu_index)
 148 {
 149         u32 index;
 150
 151         for (index = 0; index < ep->num_ob_windows; index++) {
 152                 if (ep->outbound_addr[index] != addr)
 153                         continue;
 154                 *atu_index = index;
 155                 return 0;
 156         }
 157
 158         return -EINVAL;
 159 }
 160
 161 static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
 162                                   phys_addr_t addr)
 163 {
 164         int ret;
 165         u32 atu_index;
 166         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
 167         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 168
 169         ret = dw_pcie_find_index(ep, addr, &atu_index);
 170         if (ret < 0)
 171                 return;
 172
 173         dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
 174         clear_bit(atu_index, ep->ob_window_map);
 175 }
 176
 177 static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
 178                                phys_addr_t addr,
 179                                u64 pci_addr, size_t size)
 180 {
 181         int ret;
 182         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
 183         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 184
 185         ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
 186         if (ret) {
 187                 dev_err(pci->dev, "failed to enable address\n");
 188                 return ret;
 189         }
 190
 191         return 0;
 192 }
 193
 194 static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
 195 {
 196         int val;
 197         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
 198         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 199
 200         val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
 201         if (!(val & MSI_CAP_MSI_EN_MASK))
 202                 return -EINVAL;
 203
 204         val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
 205         return val;
 206 }
 207
 208 static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 encode_int)
 209 {
 210         int val;
 211         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
 212         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 213
 214         val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
 215         val &= ~MSI_CAP_MMC_MASK;
 216         val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
 217         dw_pcie_dbi_ro_wr_en(pci);
 218         dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
 219         dw_pcie_dbi_ro_wr_dis(pci);
 220
 221         return 0;
 222 }
 223
 224 static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
 225                                 enum pci_epc_irq_type type, u8 interrupt_num)
 226 {
 227         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
 228
 229         if (!ep->ops->raise_irq)
 230                 return -EINVAL;
 231
 232         return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
 233 }
 234
 235 static void dw_pcie_ep_stop(struct pci_epc *epc)
 236 {
 237         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
 238         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 239
 240         if (!pci->ops->stop_link)
 241                 return;
 242
 243         pci->ops->stop_link(pci);
 244 }
 245
 246 static int dw_pcie_ep_start(struct pci_epc *epc)
 247 {
 248         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
 249         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 250
 251         if (!pci->ops->start_link)
 252                 return -EINVAL;
 253
 254         return pci->ops->start_link(pci);
 255 }
 256
 257 static const struct pci_epc_ops epc_ops = {
 258         .write_header           = dw_pcie_ep_write_header,
 259         .set_bar                = dw_pcie_ep_set_bar,
 260         .clear_bar              = dw_pcie_ep_clear_bar,
 261         .map_addr               = dw_pcie_ep_map_addr,
 262         .unmap_addr             = dw_pcie_ep_unmap_addr,
 263         .set_msi                = dw_pcie_ep_set_msi,
 264         .get_msi                = dw_pcie_ep_get_msi,
 265         .raise_irq              = dw_pcie_ep_raise_irq,
 266         .start                  = dw_pcie_ep_start,
 267         .stop                   = dw_pcie_ep_stop,
 268 };
 269
 270 int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
 271                              u8 interrupt_num)
 272 {
 273         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 274         struct pci_epc *epc = ep->epc;
 275         u16 msg_ctrl, msg_data;
 276         u32 msg_addr_lower, msg_addr_upper;
 277         u64 msg_addr;
 278         bool has_upper;
 279         int ret;
 280
 281         /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
 282         msg_ctrl = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
 283         has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
 284         msg_addr_lower = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
 285         if (has_upper) {
 286                 msg_addr_upper = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
 287                 msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_64);
 288         } else {
 289                 msg_addr_upper = 0;
 290                 msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_32);
 291         }
 292         msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
 293         ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
 294                                   epc->mem->page_size);
 295         if (ret)
 296                 return ret;
 297
 298         writel(msg_data | (interrupt_num - 1), ep->msi_mem);
 299
 300         dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
 301
 302         return 0;
 303 }
 304
 305 void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
 306 {
 307         struct pci_epc *epc = ep->epc;
 308
 309         pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
 310                               epc->mem->page_size);
 311
 312         pci_epc_mem_exit(epc);
 313 }
 314
 315 int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 316 {
 317         int ret;
 318         void *addr;
 319         struct pci_epc *epc;
 320         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 321         struct device *dev = pci->dev;
 322         struct device_node *np = dev->of_node;
 323
 324         if (!pci->dbi_base || !pci->dbi_base2) {
 325                 dev_err(dev, "dbi_base/deb_base2 is not populated\n");
 326                 return -EINVAL;
 327         }
 328
 329         ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
 330         if (ret < 0) {
 331                 dev_err(dev, "unable to read *num-ib-windows* property\n");
 332                 return ret;
 333         }
 334         if (ep->num_ib_windows > MAX_IATU_IN) {
 335                 dev_err(dev, "invalid *num-ib-windows*\n");
 336                 return -EINVAL;
 337         }
 338
 339         ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
 340         if (ret < 0) {
 341                 dev_err(dev, "unable to read *num-ob-windows* property\n");
 342                 return ret;
 343         }
 344         if (ep->num_ob_windows > MAX_IATU_OUT) {
 345                 dev_err(dev, "invalid *num-ob-windows*\n");
 346                 return -EINVAL;
 347         }
 348
 349         ep->ib_window_map = devm_kzalloc(dev, sizeof(long) *
 350                                          BITS_TO_LONGS(ep->num_ib_windows),
 351                                          GFP_KERNEL);
 352         if (!ep->ib_window_map)
 353                 return -ENOMEM;
 354
 355         ep->ob_window_map = devm_kzalloc(dev, sizeof(long) *
 356                                          BITS_TO_LONGS(ep->num_ob_windows),
 357                                          GFP_KERNEL);
 358         if (!ep->ob_window_map)
 359                 return -ENOMEM;
 360
 361         addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
 362                             GFP_KERNEL);
 363         if (!addr)
 364                 return -ENOMEM;
 365         ep->outbound_addr = addr;
 366
 367         if (ep->ops->ep_init)
 368                 ep->ops->ep_init(ep);
 369
 370         epc = devm_pci_epc_create(dev, &epc_ops);
 371         if (IS_ERR(epc)) {
 372                 dev_err(dev, "failed to create epc device\n");
 373                 return PTR_ERR(epc);
 374         }
 375
 376         ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
 377         if (ret < 0)
 378                 epc->max_functions = 1;
 379
 380         ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
 381                                  ep->page_size);
 382         if (ret < 0) {
 383                 dev_err(dev, "Failed to initialize address space\n");
 384                 return ret;
 385         }
 386
 387         ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
 388                                              epc->mem->page_size);
 389         if (!ep->msi_mem) {
 390                 dev_err(dev, "Failed to reserve memory for MSI\n");
 391                 return -ENOMEM;
 392         }
 393
 394         ep->epc = epc;
 395         epc_set_drvdata(epc, ep);
 396         dw_pcie_setup(pci);
 397
 398         return 0;
 399 }