drivers/pci/dwc/pcie-qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Qualcomm PCIe root complex driver
   4  *
   5  * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   6  * Copyright 2015 Linaro Limited.
   7  *
   8  * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/delay.h>
  13 #include <linux/gpio.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/of_device.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/pci.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/phy/phy.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/reset.h>
  26 #include <linux/slab.h>
  27 #include <linux/types.h>
  28
  29 #include "pcie-designware.h"
  30
  31 #define PCIE20_PARF_SYS_CTRL                    0x00
  32 #define MST_WAKEUP_EN                           BIT(13)
  33 #define SLV_WAKEUP_EN                           BIT(12)
  34 #define MSTR_ACLK_CGC_DIS                       BIT(10)
  35 #define SLV_ACLK_CGC_DIS                        BIT(9)
  36 #define CORE_CLK_CGC_DIS                        BIT(6)
  37 #define AUX_PWR_DET                             BIT(4)
  38 #define L23_CLK_RMV_DIS                         BIT(2)
  39 #define L1_CLK_RMV_DIS                          BIT(1)
  40
  41 #define PCIE20_COMMAND_STATUS                   0x04
  42 #define CMD_BME_VAL                             0x4
  43 #define PCIE20_DEVICE_CONTROL2_STATUS2          0x98
  44 #define PCIE_CAP_CPL_TIMEOUT_DISABLE            0x10
  45
  46 #define PCIE20_PARF_PHY_CTRL                    0x40
  47 #define PCIE20_PARF_PHY_REFCLK                  0x4C
  48 #define PCIE20_PARF_DBI_BASE_ADDR               0x168
  49 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE         0x16C
  50 #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL        0x174
  51 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT       0x178
  52 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2    0x1A8
  53 #define PCIE20_PARF_LTSSM                       0x1B0
  54 #define PCIE20_PARF_SID_OFFSET                  0x234
  55 #define PCIE20_PARF_BDF_TRANSLATE_CFG           0x24C
  56
  57 #define PCIE20_ELBI_SYS_CTRL                    0x04
  58 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE          BIT(0)
  59
  60 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL0         0x818
  61 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K        0x4
  62 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K        0x5
  63 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1         0x81c
  64 #define CFG_BRIDGE_SB_INIT                      BIT(0)
  65
  66 #define PCIE20_CAP                              0x70
  67 #define PCIE20_CAP_LINK_CAPABILITIES            (PCIE20_CAP + 0xC)
  68 #define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11))
  69 #define PCIE20_CAP_LINK_1                       (PCIE20_CAP + 0x14)
  70 #define PCIE_CAP_LINK1_VAL                      0x2FD7F
  71
  72 #define PCIE20_PARF_Q2A_FLUSH                   0x1AC
  73
  74 #define PCIE20_MISC_CONTROL_1_REG               0x8BC
  75 #define DBI_RO_WR_EN                            1
  76
  77 #define PERST_DELAY_US                          1000
  78
  79 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE      0x358
  80 #define SLV_ADDR_SPACE_SZ                       0x10000000
  81
  82 struct qcom_pcie_resources_2_1_0 {
  83         struct clk *iface_clk;
  84         struct clk *core_clk;
  85         struct clk *phy_clk;
  86         struct reset_control *pci_reset;
  87         struct reset_control *axi_reset;
  88         struct reset_control *ahb_reset;
  89         struct reset_control *por_reset;
  90         struct reset_control *phy_reset;
  91         struct regulator *vdda;
  92         struct regulator *vdda_phy;
  93         struct regulator *vdda_refclk;
  94 };
  95
  96 struct qcom_pcie_resources_1_0_0 {
  97         struct clk *iface;
  98         struct clk *aux;
  99         struct clk *master_bus;
 100         struct clk *slave_bus;
 101         struct reset_control *core;
 102         struct regulator *vdda;
 103 };
 104
 105 struct qcom_pcie_resources_2_3_2 {
 106         struct clk *aux_clk;
 107         struct clk *master_clk;
 108         struct clk *slave_clk;
 109         struct clk *cfg_clk;
 110         struct clk *pipe_clk;
 111 };
 112
 113 struct qcom_pcie_resources_2_4_0 {
 114         struct clk *aux_clk;
 115         struct clk *master_clk;
 116         struct clk *slave_clk;
 117         struct reset_control *axi_m_reset;
 118         struct reset_control *axi_s_reset;
 119         struct reset_control *pipe_reset;
 120         struct reset_control *axi_m_vmid_reset;
 121         struct reset_control *axi_s_xpu_reset;
 122         struct reset_control *parf_reset;
 123         struct reset_control *phy_reset;
 124         struct reset_control *axi_m_sticky_reset;
 125         struct reset_control *pipe_sticky_reset;
 126         struct reset_control *pwr_reset;
 127         struct reset_control *ahb_reset;
 128         struct reset_control *phy_ahb_reset;
 129 };
 130
 131 struct qcom_pcie_resources_2_3_3 {
 132         struct clk *iface;
 133         struct clk *axi_m_clk;
 134         struct clk *axi_s_clk;
 135         struct clk *ahb_clk;
 136         struct clk *aux_clk;
 137         struct reset_control *rst[7];
 138 };
 139
 140 union qcom_pcie_resources {
 141         struct qcom_pcie_resources_1_0_0 v1_0_0;
 142         struct qcom_pcie_resources_2_1_0 v2_1_0;
 143         struct qcom_pcie_resources_2_3_2 v2_3_2;
 144         struct qcom_pcie_resources_2_3_3 v2_3_3;
 145         struct qcom_pcie_resources_2_4_0 v2_4_0;
 146 };
 147
 148 struct qcom_pcie;
 149
 150 struct qcom_pcie_ops {
 151         int (*get_resources)(struct qcom_pcie *pcie);
 152         int (*init)(struct qcom_pcie *pcie);
 153         int (*post_init)(struct qcom_pcie *pcie);
 154         void (*deinit)(struct qcom_pcie *pcie);
 155         void (*post_deinit)(struct qcom_pcie *pcie);
 156         void (*ltssm_enable)(struct qcom_pcie *pcie);
 157 };
 158
 159 struct qcom_pcie {
 160         struct dw_pcie *pci;
 161         void __iomem *parf;                     /* DT parf */
 162         void __iomem *elbi;                     /* DT elbi */
 163         union qcom_pcie_resources res;
 164         struct phy *phy;
 165         struct gpio_desc *reset;
 166         const struct qcom_pcie_ops *ops;
 167 };
 168
 169 #define to_qcom_pcie(x)         dev_get_drvdata((x)->dev)
 170
 171 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
 172 {
 173         gpiod_set_value_cansleep(pcie->reset, 1);
 174         usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
 175 }
 176
 177 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
 178 {
 179         gpiod_set_value_cansleep(pcie->reset, 0);
 180         usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
 181 }
 182
 183 static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
 184 {
 185         struct pcie_port *pp = arg;
 186
 187         return dw_handle_msi_irq(pp);
 188 }
 189
 190 static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
 191 {
 192         struct dw_pcie *pci = pcie->pci;
 193
 194         if (dw_pcie_link_up(pci))
 195                 return 0;
 196
 197         /* Enable Link Training state machine */
 198         if (pcie->ops->ltssm_enable)
 199                 pcie->ops->ltssm_enable(pcie);
 200
 201         return dw_pcie_wait_for_link(pci);
 202 }
 203
 204 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
 205 {
 206         u32 val;
 207
 208         /* enable link training */
 209         val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
 210         val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
 211         writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
 212 }
 213
 214 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
 215 {
 216         struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 217         struct dw_pcie *pci = pcie->pci;
 218         struct device *dev = pci->dev;
 219
 220         res->vdda = devm_regulator_get(dev, "vdda");
 221         if (IS_ERR(res->vdda))
 222                 return PTR_ERR(res->vdda);
 223
 224         res->vdda_phy = devm_regulator_get(dev, "vdda_phy");
 225         if (IS_ERR(res->vdda_phy))
 226                 return PTR_ERR(res->vdda_phy);
 227
 228         res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk");
 229         if (IS_ERR(res->vdda_refclk))
 230                 return PTR_ERR(res->vdda_refclk);
 231
 232         res->iface_clk = devm_clk_get(dev, "iface");
 233         if (IS_ERR(res->iface_clk))
 234                 return PTR_ERR(res->iface_clk);
 235
 236         res->core_clk = devm_clk_get(dev, "core");
 237         if (IS_ERR(res->core_clk))
 238                 return PTR_ERR(res->core_clk);
 239
 240         res->phy_clk = devm_clk_get(dev, "phy");
 241         if (IS_ERR(res->phy_clk))
 242                 return PTR_ERR(res->phy_clk);
 243
 244         res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
 245         if (IS_ERR(res->pci_reset))
 246                 return PTR_ERR(res->pci_reset);
 247
 248         res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");
 249         if (IS_ERR(res->axi_reset))
 250                 return PTR_ERR(res->axi_reset);
 251
 252         res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
 253         if (IS_ERR(res->ahb_reset))
 254                 return PTR_ERR(res->ahb_reset);
 255
 256         res->por_reset = devm_reset_control_get_exclusive(dev, "por");
 257         if (IS_ERR(res->por_reset))
 258                 return PTR_ERR(res->por_reset);
 259
 260         res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
 261         return PTR_ERR_OR_ZERO(res->phy_reset);
 262 }
 263
 264 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
 265 {
 266         struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 267
 268         reset_control_assert(res->pci_reset);
 269         reset_control_assert(res->axi_reset);
 270         reset_control_assert(res->ahb_reset);
 271         reset_control_assert(res->por_reset);
 272         reset_control_assert(res->pci_reset);
 273         clk_disable_unprepare(res->iface_clk);
 274         clk_disable_unprepare(res->core_clk);
 275         clk_disable_unprepare(res->phy_clk);
 276         regulator_disable(res->vdda);
 277         regulator_disable(res->vdda_phy);
 278         regulator_disable(res->vdda_refclk);
 279 }
 280
 281 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 282 {
 283         struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 284         struct dw_pcie *pci = pcie->pci;
 285         struct device *dev = pci->dev;
 286         u32 val;
 287         int ret;
 288
 289         ret = regulator_enable(res->vdda);
 290         if (ret) {
 291                 dev_err(dev, "cannot enable vdda regulator\n");
 292                 return ret;
 293         }
 294
 295         ret = regulator_enable(res->vdda_refclk);
 296         if (ret) {
 297                 dev_err(dev, "cannot enable vdda_refclk regulator\n");
 298                 goto err_refclk;
 299         }
 300
 301         ret = regulator_enable(res->vdda_phy);
 302         if (ret) {
 303                 dev_err(dev, "cannot enable vdda_phy regulator\n");
 304                 goto err_vdda_phy;
 305         }
 306
 307         ret = reset_control_assert(res->ahb_reset);
 308         if (ret) {
 309                 dev_err(dev, "cannot assert ahb reset\n");
 310                 goto err_assert_ahb;
 311         }
 312
 313         ret = clk_prepare_enable(res->iface_clk);
 314         if (ret) {
 315                 dev_err(dev, "cannot prepare/enable iface clock\n");
 316                 goto err_assert_ahb;
 317         }
 318
 319         ret = clk_prepare_enable(res->phy_clk);
 320         if (ret) {
 321                 dev_err(dev, "cannot prepare/enable phy clock\n");
 322                 goto err_clk_phy;
 323         }
 324
 325         ret = clk_prepare_enable(res->core_clk);
 326         if (ret) {
 327                 dev_err(dev, "cannot prepare/enable core clock\n");
 328                 goto err_clk_core;
 329         }
 330
 331         ret = reset_control_deassert(res->ahb_reset);
 332         if (ret) {
 333                 dev_err(dev, "cannot deassert ahb reset\n");
 334                 goto err_deassert_ahb;
 335         }
 336
 337         /* enable PCIe clocks and resets */
 338         val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
 339         val &= ~BIT(0);
 340         writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
 341
 342         /* enable external reference clock */
 343         val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
 344         val |= BIT(16);
 345         writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
 346
 347         ret = reset_control_deassert(res->phy_reset);
 348         if (ret) {
 349                 dev_err(dev, "cannot deassert phy reset\n");
 350                 return ret;
 351         }
 352
 353         ret = reset_control_deassert(res->pci_reset);
 354         if (ret) {
 355                 dev_err(dev, "cannot deassert pci reset\n");
 356                 return ret;
 357         }
 358
 359         ret = reset_control_deassert(res->por_reset);
 360         if (ret) {
 361                 dev_err(dev, "cannot deassert por reset\n");
 362                 return ret;
 363         }
 364
 365         ret = reset_control_deassert(res->axi_reset);
 366         if (ret) {
 367                 dev_err(dev, "cannot deassert axi reset\n");
 368                 return ret;
 369         }
 370
 371         /* wait for clock acquisition */
 372         usleep_range(1000, 1500);
 373
 374
 375         /* Set the Max TLP size to 2K, instead of using default of 4K */
 376         writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
 377                pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
 378         writel(CFG_BRIDGE_SB_INIT,
 379                pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
 380
 381         return 0;
 382
 383 err_deassert_ahb:
 384         clk_disable_unprepare(res->core_clk);
 385 err_clk_core:
 386         clk_disable_unprepare(res->phy_clk);
 387 err_clk_phy:
 388         clk_disable_unprepare(res->iface_clk);
 389 err_assert_ahb:
 390         regulator_disable(res->vdda_phy);
 391 err_vdda_phy:
 392         regulator_disable(res->vdda_refclk);
 393 err_refclk:
 394         regulator_disable(res->vdda);
 395
 396         return ret;
 397 }
 398
 399 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
 400 {
 401         struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
 402         struct dw_pcie *pci = pcie->pci;
 403         struct device *dev = pci->dev;
 404
 405         res->vdda = devm_regulator_get(dev, "vdda");
 406         if (IS_ERR(res->vdda))
 407                 return PTR_ERR(res->vdda);
 408
 409         res->iface = devm_clk_get(dev, "iface");
 410         if (IS_ERR(res->iface))
 411                 return PTR_ERR(res->iface);
 412
 413         res->aux = devm_clk_get(dev, "aux");
 414         if (IS_ERR(res->aux))
 415                 return PTR_ERR(res->aux);
 416
 417         res->master_bus = devm_clk_get(dev, "master_bus");
 418         if (IS_ERR(res->master_bus))
 419                 return PTR_ERR(res->master_bus);
 420
 421         res->slave_bus = devm_clk_get(dev, "slave_bus");
 422         if (IS_ERR(res->slave_bus))
 423                 return PTR_ERR(res->slave_bus);
 424
 425         res->core = devm_reset_control_get_exclusive(dev, "core");
 426         return PTR_ERR_OR_ZERO(res->core);
 427 }
 428
 429 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
 430 {
 431         struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
 432
 433         reset_control_assert(res->core);
 434         clk_disable_unprepare(res->slave_bus);
 435         clk_disable_unprepare(res->master_bus);
 436         clk_disable_unprepare(res->iface);
 437         clk_disable_unprepare(res->aux);
 438         regulator_disable(res->vdda);
 439 }
 440
 441 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
 442 {
 443         struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
 444         struct dw_pcie *pci = pcie->pci;
 445         struct device *dev = pci->dev;
 446         int ret;
 447
 448         ret = reset_control_deassert(res->core);
 449         if (ret) {
 450                 dev_err(dev, "cannot deassert core reset\n");
 451                 return ret;
 452         }
 453
 454         ret = clk_prepare_enable(res->aux);
 455         if (ret) {
 456                 dev_err(dev, "cannot prepare/enable aux clock\n");
 457                 goto err_res;
 458         }
 459
 460         ret = clk_prepare_enable(res->iface);
 461         if (ret) {
 462                 dev_err(dev, "cannot prepare/enable iface clock\n");
 463                 goto err_aux;
 464         }
 465
 466         ret = clk_prepare_enable(res->master_bus);
 467         if (ret) {
 468                 dev_err(dev, "cannot prepare/enable master_bus clock\n");
 469                 goto err_iface;
 470         }
 471
 472         ret = clk_prepare_enable(res->slave_bus);
 473         if (ret) {
 474                 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
 475                 goto err_master;
 476         }
 477
 478         ret = regulator_enable(res->vdda);
 479         if (ret) {
 480                 dev_err(dev, "cannot enable vdda regulator\n");
 481                 goto err_slave;
 482         }
 483
 484         /* change DBI base address */
 485         writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
 486
 487         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 488                 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
 489
 490                 val |= BIT(31);
 491                 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
 492         }
 493
 494         return 0;
 495 err_slave:
 496         clk_disable_unprepare(res->slave_bus);
 497 err_master:
 498         clk_disable_unprepare(res->master_bus);
 499 err_iface:
 500         clk_disable_unprepare(res->iface);
 501 err_aux:
 502         clk_disable_unprepare(res->aux);
 503 err_res:
 504         reset_control_assert(res->core);
 505
 506         return ret;
 507 }
 508
 509 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
 510 {
 511         u32 val;
 512
 513         /* enable link training */
 514         val = readl(pcie->parf + PCIE20_PARF_LTSSM);
 515         val |= BIT(8);
 516         writel(val, pcie->parf + PCIE20_PARF_LTSSM);
 517 }
 518
 519 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
 520 {
 521         struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
 522         struct dw_pcie *pci = pcie->pci;
 523         struct device *dev = pci->dev;
 524
 525         res->aux_clk = devm_clk_get(dev, "aux");
 526         if (IS_ERR(res->aux_clk))
 527                 return PTR_ERR(res->aux_clk);
 528
 529         res->cfg_clk = devm_clk_get(dev, "cfg");
 530         if (IS_ERR(res->cfg_clk))
 531                 return PTR_ERR(res->cfg_clk);
 532
 533         res->master_clk = devm_clk_get(dev, "bus_master");
 534         if (IS_ERR(res->master_clk))
 535                 return PTR_ERR(res->master_clk);
 536
 537         res->slave_clk = devm_clk_get(dev, "bus_slave");
 538         if (IS_ERR(res->slave_clk))
 539                 return PTR_ERR(res->slave_clk);
 540
 541         res->pipe_clk = devm_clk_get(dev, "pipe");
 542         return PTR_ERR_OR_ZERO(res->pipe_clk);
 543 }
 544
 545 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
 546 {
 547         struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
 548
 549         clk_disable_unprepare(res->slave_clk);
 550         clk_disable_unprepare(res->master_clk);
 551         clk_disable_unprepare(res->cfg_clk);
 552         clk_disable_unprepare(res->aux_clk);
 553 }
 554
 555 static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
 556 {
 557         struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
 558
 559         clk_disable_unprepare(res->pipe_clk);
 560 }
 561
 562 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
 563 {
 564         struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
 565         struct dw_pcie *pci = pcie->pci;
 566         struct device *dev = pci->dev;
 567         u32 val;
 568         int ret;
 569
 570         ret = clk_prepare_enable(res->aux_clk);
 571         if (ret) {
 572                 dev_err(dev, "cannot prepare/enable aux clock\n");
 573                 return ret;
 574         }
 575
 576         ret = clk_prepare_enable(res->cfg_clk);
 577         if (ret) {
 578                 dev_err(dev, "cannot prepare/enable cfg clock\n");
 579                 goto err_cfg_clk;
 580         }
 581
 582         ret = clk_prepare_enable(res->master_clk);
 583         if (ret) {
 584                 dev_err(dev, "cannot prepare/enable master clock\n");
 585                 goto err_master_clk;
 586         }
 587
 588         ret = clk_prepare_enable(res->slave_clk);
 589         if (ret) {
 590                 dev_err(dev, "cannot prepare/enable slave clock\n");
 591                 goto err_slave_clk;
 592         }
 593
 594         /* enable PCIe clocks and resets */
 595         val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
 596         val &= ~BIT(0);
 597         writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
 598
 599         /* change DBI base address */
 600         writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
 601
 602         /* MAC PHY_POWERDOWN MUX DISABLE  */
 603         val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
 604         val &= ~BIT(29);
 605         writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
 606
 607         val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
 608         val |= BIT(4);
 609         writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
 610
 611         val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
 612         val |= BIT(31);
 613         writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
 614
 615         return 0;
 616
 617 err_slave_clk:
 618         clk_disable_unprepare(res->master_clk);
 619 err_master_clk:
 620         clk_disable_unprepare(res->cfg_clk);
 621 err_cfg_clk:
 622         clk_disable_unprepare(res->aux_clk);
 623
 624         return ret;
 625 }
 626
 627 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
 628 {
 629         struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
 630         struct dw_pcie *pci = pcie->pci;
 631         struct device *dev = pci->dev;
 632         int ret;
 633
 634         ret = clk_prepare_enable(res->pipe_clk);
 635         if (ret) {
 636                 dev_err(dev, "cannot prepare/enable pipe clock\n");
 637                 return ret;
 638         }
 639
 640         return 0;
 641 }
 642
 643 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
 644 {
 645         struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
 646         struct dw_pcie *pci = pcie->pci;
 647         struct device *dev = pci->dev;
 648
 649         res->aux_clk = devm_clk_get(dev, "aux");
 650         if (IS_ERR(res->aux_clk))
 651                 return PTR_ERR(res->aux_clk);
 652
 653         res->master_clk = devm_clk_get(dev, "master_bus");
 654         if (IS_ERR(res->master_clk))
 655                 return PTR_ERR(res->master_clk);
 656
 657         res->slave_clk = devm_clk_get(dev, "slave_bus");
 658         if (IS_ERR(res->slave_clk))
 659                 return PTR_ERR(res->slave_clk);
 660
 661         res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
 662         if (IS_ERR(res->axi_m_reset))
 663                 return PTR_ERR(res->axi_m_reset);
 664
 665         res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");
 666         if (IS_ERR(res->axi_s_reset))
 667                 return PTR_ERR(res->axi_s_reset);
 668
 669         res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
 670         if (IS_ERR(res->pipe_reset))
 671                 return PTR_ERR(res->pipe_reset);
 672
 673         res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
 674                                                                  "axi_m_vmid");
 675         if (IS_ERR(res->axi_m_vmid_reset))
 676                 return PTR_ERR(res->axi_m_vmid_reset);
 677
 678         res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
 679                                                                 "axi_s_xpu");
 680         if (IS_ERR(res->axi_s_xpu_reset))
 681                 return PTR_ERR(res->axi_s_xpu_reset);
 682
 683         res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
 684         if (IS_ERR(res->parf_reset))
 685                 return PTR_ERR(res->parf_reset);
 686
 687         res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
 688         if (IS_ERR(res->phy_reset))
 689                 return PTR_ERR(res->phy_reset);
 690
 691         res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
 692                                                                    "axi_m_sticky");
 693         if (IS_ERR(res->axi_m_sticky_reset))
 694                 return PTR_ERR(res->axi_m_sticky_reset);
 695
 696         res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,
 697                                                                   "pipe_sticky");
 698         if (IS_ERR(res->pipe_sticky_reset))
 699                 return PTR_ERR(res->pipe_sticky_reset);
 700
 701         res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");
 702         if (IS_ERR(res->pwr_reset))
 703                 return PTR_ERR(res->pwr_reset);
 704
 705         res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
 706         if (IS_ERR(res->ahb_reset))
 707                 return PTR_ERR(res->ahb_reset);
 708
 709         res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
 710         if (IS_ERR(res->phy_ahb_reset))
 711                 return PTR_ERR(res->phy_ahb_reset);
 712
 713         return 0;
 714 }
 715
 716 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
 717 {
 718         struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
 719
 720         reset_control_assert(res->axi_m_reset);
 721         reset_control_assert(res->axi_s_reset);
 722         reset_control_assert(res->pipe_reset);
 723         reset_control_assert(res->pipe_sticky_reset);
 724         reset_control_assert(res->phy_reset);
 725         reset_control_assert(res->phy_ahb_reset);
 726         reset_control_assert(res->axi_m_sticky_reset);
 727         reset_control_assert(res->pwr_reset);
 728         reset_control_assert(res->ahb_reset);
 729         clk_disable_unprepare(res->aux_clk);
 730         clk_disable_unprepare(res->master_clk);
 731         clk_disable_unprepare(res->slave_clk);
 732 }
 733
 734 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
 735 {
 736         struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
 737         struct dw_pcie *pci = pcie->pci;
 738         struct device *dev = pci->dev;
 739         u32 val;
 740         int ret;
 741
 742         ret = reset_control_assert(res->axi_m_reset);
 743         if (ret) {
 744                 dev_err(dev, "cannot assert axi master reset\n");
 745                 return ret;
 746         }
 747
 748         ret = reset_control_assert(res->axi_s_reset);
 749         if (ret) {
 750                 dev_err(dev, "cannot assert axi slave reset\n");
 751                 return ret;
 752         }
 753
 754         usleep_range(10000, 12000);
 755
 756         ret = reset_control_assert(res->pipe_reset);
 757         if (ret) {
 758                 dev_err(dev, "cannot assert pipe reset\n");
 759                 return ret;
 760         }
 761
 762         ret = reset_control_assert(res->pipe_sticky_reset);
 763         if (ret) {
 764                 dev_err(dev, "cannot assert pipe sticky reset\n");
 765                 return ret;
 766         }
 767
 768         ret = reset_control_assert(res->phy_reset);
 769         if (ret) {
 770                 dev_err(dev, "cannot assert phy reset\n");
 771                 return ret;
 772         }
 773
 774         ret = reset_control_assert(res->phy_ahb_reset);
 775         if (ret) {
 776                 dev_err(dev, "cannot assert phy ahb reset\n");
 777                 return ret;
 778         }
 779
 780         usleep_range(10000, 12000);
 781
 782         ret = reset_control_assert(res->axi_m_sticky_reset);
 783         if (ret) {
 784                 dev_err(dev, "cannot assert axi master sticky reset\n");
 785                 return ret;
 786         }
 787
 788         ret = reset_control_assert(res->pwr_reset);
 789         if (ret) {
 790                 dev_err(dev, "cannot assert power reset\n");
 791                 return ret;
 792         }
 793
 794         ret = reset_control_assert(res->ahb_reset);
 795         if (ret) {
 796                 dev_err(dev, "cannot assert ahb reset\n");
 797                 return ret;
 798         }
 799
 800         usleep_range(10000, 12000);
 801
 802         ret = reset_control_deassert(res->phy_ahb_reset);
 803         if (ret) {
 804                 dev_err(dev, "cannot deassert phy ahb reset\n");
 805                 return ret;
 806         }
 807
 808         ret = reset_control_deassert(res->phy_reset);
 809         if (ret) {
 810                 dev_err(dev, "cannot deassert phy reset\n");
 811                 goto err_rst_phy;
 812         }
 813
 814         ret = reset_control_deassert(res->pipe_reset);
 815         if (ret) {
 816                 dev_err(dev, "cannot deassert pipe reset\n");
 817                 goto err_rst_pipe;
 818         }
 819
 820         ret = reset_control_deassert(res->pipe_sticky_reset);
 821         if (ret) {
 822                 dev_err(dev, "cannot deassert pipe sticky reset\n");
 823                 goto err_rst_pipe_sticky;
 824         }
 825
 826         usleep_range(10000, 12000);
 827
 828         ret = reset_control_deassert(res->axi_m_reset);
 829         if (ret) {
 830                 dev_err(dev, "cannot deassert axi master reset\n");
 831                 goto err_rst_axi_m;
 832         }
 833
 834         ret = reset_control_deassert(res->axi_m_sticky_reset);
 835         if (ret) {
 836                 dev_err(dev, "cannot deassert axi master sticky reset\n");
 837                 goto err_rst_axi_m_sticky;
 838         }
 839
 840         ret = reset_control_deassert(res->axi_s_reset);
 841         if (ret) {
 842                 dev_err(dev, "cannot deassert axi slave reset\n");
 843                 goto err_rst_axi_s;
 844         }
 845
 846         ret = reset_control_deassert(res->pwr_reset);
 847         if (ret) {
 848                 dev_err(dev, "cannot deassert power reset\n");
 849                 goto err_rst_pwr;
 850         }
 851
 852         ret = reset_control_deassert(res->ahb_reset);
 853         if (ret) {
 854                 dev_err(dev, "cannot deassert ahb reset\n");
 855                 goto err_rst_ahb;
 856         }
 857
 858         usleep_range(10000, 12000);
 859
 860         ret = clk_prepare_enable(res->aux_clk);
 861         if (ret) {
 862                 dev_err(dev, "cannot prepare/enable iface clock\n");
 863                 goto err_clk_aux;
 864         }
 865
 866         ret = clk_prepare_enable(res->master_clk);
 867         if (ret) {
 868                 dev_err(dev, "cannot prepare/enable core clock\n");
 869                 goto err_clk_axi_m;
 870         }
 871
 872         ret = clk_prepare_enable(res->slave_clk);
 873         if (ret) {
 874                 dev_err(dev, "cannot prepare/enable phy clock\n");
 875                 goto err_clk_axi_s;
 876         }
 877
 878         /* enable PCIe clocks and resets */
 879         val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
 880         val &= !BIT(0);
 881         writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
 882
 883         /* change DBI base address */
 884         writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
 885
 886         /* MAC PHY_POWERDOWN MUX DISABLE  */
 887         val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
 888         val &= ~BIT(29);
 889         writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
 890
 891         val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
 892         val |= BIT(4);
 893         writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
 894
 895         val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
 896         val |= BIT(31);
 897         writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
 898
 899         return 0;
 900
 901 err_clk_axi_s:
 902         clk_disable_unprepare(res->master_clk);
 903 err_clk_axi_m:
 904         clk_disable_unprepare(res->aux_clk);
 905 err_clk_aux:
 906         reset_control_assert(res->ahb_reset);
 907 err_rst_ahb:
 908         reset_control_assert(res->pwr_reset);
 909 err_rst_pwr:
 910         reset_control_assert(res->axi_s_reset);
 911 err_rst_axi_s:
 912         reset_control_assert(res->axi_m_sticky_reset);
 913 err_rst_axi_m_sticky:
 914         reset_control_assert(res->axi_m_reset);
 915 err_rst_axi_m:
 916         reset_control_assert(res->pipe_sticky_reset);
 917 err_rst_pipe_sticky:
 918         reset_control_assert(res->pipe_reset);
 919 err_rst_pipe:
 920         reset_control_assert(res->phy_reset);
 921 err_rst_phy:
 922         reset_control_assert(res->phy_ahb_reset);
 923         return ret;
 924 }
 925
 926 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
 927 {
 928         struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
 929         struct dw_pcie *pci = pcie->pci;
 930         struct device *dev = pci->dev;
 931         int i;
 932         const char *rst_names[] = { "axi_m", "axi_s", "pipe",
 933                                     "axi_m_sticky", "sticky",
 934                                     "ahb", "sleep", };
 935
 936         res->iface = devm_clk_get(dev, "iface");
 937         if (IS_ERR(res->iface))
 938                 return PTR_ERR(res->iface);
 939
 940         res->axi_m_clk = devm_clk_get(dev, "axi_m");
 941         if (IS_ERR(res->axi_m_clk))
 942                 return PTR_ERR(res->axi_m_clk);
 943
 944         res->axi_s_clk = devm_clk_get(dev, "axi_s");
 945         if (IS_ERR(res->axi_s_clk))
 946                 return PTR_ERR(res->axi_s_clk);
 947
 948         res->ahb_clk = devm_clk_get(dev, "ahb");
 949         if (IS_ERR(res->ahb_clk))
 950                 return PTR_ERR(res->ahb_clk);
 951
 952         res->aux_clk = devm_clk_get(dev, "aux");
 953         if (IS_ERR(res->aux_clk))
 954                 return PTR_ERR(res->aux_clk);
 955
 956         for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
 957                 res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
 958                 if (IS_ERR(res->rst[i]))
 959                         return PTR_ERR(res->rst[i]);
 960         }
 961
 962         return 0;
 963 }
 964
 965 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
 966 {
 967         struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
 968
 969         clk_disable_unprepare(res->iface);
 970         clk_disable_unprepare(res->axi_m_clk);
 971         clk_disable_unprepare(res->axi_s_clk);
 972         clk_disable_unprepare(res->ahb_clk);
 973         clk_disable_unprepare(res->aux_clk);
 974 }
 975
 976 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
 977 {
 978         struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
 979         struct dw_pcie *pci = pcie->pci;
 980         struct device *dev = pci->dev;
 981         int i, ret;
 982         u32 val;
 983
 984         for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
 985                 ret = reset_control_assert(res->rst[i]);
 986                 if (ret) {
 987                         dev_err(dev, "reset #%d assert failed (%d)\n", i, ret);
 988                         return ret;
 989                 }
 990         }
 991
 992         usleep_range(2000, 2500);
 993
 994         for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
 995                 ret = reset_control_deassert(res->rst[i]);
 996                 if (ret) {
 997                         dev_err(dev, "reset #%d deassert failed (%d)\n", i,
 998                                 ret);
 999                         return ret;
1000                 }
1001         }
1002
1003         /*
1004          * Don't have a way to see if the reset has completed.
1005          * Wait for some time.
1006          */
1007         usleep_range(2000, 2500);
1008
1009         ret = clk_prepare_enable(res->iface);
1010         if (ret) {
1011                 dev_err(dev, "cannot prepare/enable core clock\n");
1012                 goto err_clk_iface;
1013         }
1014
1015         ret = clk_prepare_enable(res->axi_m_clk);
1016         if (ret) {
1017                 dev_err(dev, "cannot prepare/enable core clock\n");
1018                 goto err_clk_axi_m;
1019         }
1020
1021         ret = clk_prepare_enable(res->axi_s_clk);
1022         if (ret) {
1023                 dev_err(dev, "cannot prepare/enable axi slave clock\n");
1024                 goto err_clk_axi_s;
1025         }
1026
1027         ret = clk_prepare_enable(res->ahb_clk);
1028         if (ret) {
1029                 dev_err(dev, "cannot prepare/enable ahb clock\n");
1030                 goto err_clk_ahb;
1031         }
1032
1033         ret = clk_prepare_enable(res->aux_clk);
1034         if (ret) {
1035                 dev_err(dev, "cannot prepare/enable aux clock\n");
1036                 goto err_clk_aux;
1037         }
1038
1039         writel(SLV_ADDR_SPACE_SZ,
1040                 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1041
1042         val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1043         val &= ~BIT(0);
1044         writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1045
1046         writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1047
1048         writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
1049                 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1050                 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1051                 pcie->parf + PCIE20_PARF_SYS_CTRL);
1052         writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1053
1054         writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS);
1055         writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
1056         writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1);
1057
1058         val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
1059         val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT;
1060         writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
1061
1062         writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base +
1063                 PCIE20_DEVICE_CONTROL2_STATUS2);
1064
1065         return 0;
1066
1067 err_clk_aux:
1068         clk_disable_unprepare(res->ahb_clk);
1069 err_clk_ahb:
1070         clk_disable_unprepare(res->axi_s_clk);
1071 err_clk_axi_s:
1072         clk_disable_unprepare(res->axi_m_clk);
1073 err_clk_axi_m:
1074         clk_disable_unprepare(res->iface);
1075 err_clk_iface:
1076         /*
1077          * Not checking for failure, will anyway return
1078          * the original failure in 'ret'.
1079          */
1080         for (i = 0; i < ARRAY_SIZE(res->rst); i++)
1081                 reset_control_assert(res->rst[i]);
1082
1083         return ret;
1084 }
1085
1086 static int qcom_pcie_link_up(struct dw_pcie *pci)
1087 {
1088         u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
1089
1090         return !!(val & PCI_EXP_LNKSTA_DLLLA);
1091 }
1092
1093 static int qcom_pcie_host_init(struct pcie_port *pp)
1094 {
1095         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1096         struct qcom_pcie *pcie = to_qcom_pcie(pci);
1097         int ret;
1098
1099         qcom_ep_reset_assert(pcie);
1100
1101         ret = pcie->ops->init(pcie);
1102         if (ret)
1103                 return ret;
1104
1105         ret = phy_power_on(pcie->phy);
1106         if (ret)
1107                 goto err_deinit;
1108
1109         if (pcie->ops->post_init) {
1110                 ret = pcie->ops->post_init(pcie);
1111                 if (ret)
1112                         goto err_disable_phy;
1113         }
1114
1115         dw_pcie_setup_rc(pp);
1116
1117         if (IS_ENABLED(CONFIG_PCI_MSI))
1118                 dw_pcie_msi_init(pp);
1119
1120         qcom_ep_reset_deassert(pcie);
1121
1122         ret = qcom_pcie_establish_link(pcie);
1123         if (ret)
1124                 goto err;
1125
1126         return 0;
1127 err:
1128         qcom_ep_reset_assert(pcie);
1129         if (pcie->ops->post_deinit)
1130                 pcie->ops->post_deinit(pcie);
1131 err_disable_phy:
1132         phy_power_off(pcie->phy);
1133 err_deinit:
1134         pcie->ops->deinit(pcie);
1135
1136         return ret;
1137 }
1138
1139 static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
1140                                  u32 *val)
1141 {
1142         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1143
1144         /* the device class is not reported correctly from the register */
1145         if (where == PCI_CLASS_REVISION && size == 4) {
1146                 *val = readl(pci->dbi_base + PCI_CLASS_REVISION);
1147                 *val &= 0xff;   /* keep revision id */
1148                 *val |= PCI_CLASS_BRIDGE_PCI << 16;
1149                 return PCIBIOS_SUCCESSFUL;
1150         }
1151
1152         return dw_pcie_read(pci->dbi_base + where, size, val);
1153 }
1154
1155 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1156         .host_init = qcom_pcie_host_init,
1157         .rd_own_conf = qcom_pcie_rd_own_conf,
1158 };
1159
1160 /* Qcom IP rev.: 2.1.0  Synopsys IP rev.: 4.01a */
1161 static const struct qcom_pcie_ops ops_2_1_0 = {
1162         .get_resources = qcom_pcie_get_resources_2_1_0,
1163         .init = qcom_pcie_init_2_1_0,
1164         .deinit = qcom_pcie_deinit_2_1_0,
1165         .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1166 };
1167
1168 /* Qcom IP rev.: 1.0.0  Synopsys IP rev.: 4.11a */
1169 static const struct qcom_pcie_ops ops_1_0_0 = {
1170         .get_resources = qcom_pcie_get_resources_1_0_0,
1171         .init = qcom_pcie_init_1_0_0,
1172         .deinit = qcom_pcie_deinit_1_0_0,
1173         .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1174 };
1175
1176 /* Qcom IP rev.: 2.3.2  Synopsys IP rev.: 4.21a */
1177 static const struct qcom_pcie_ops ops_2_3_2 = {
1178         .get_resources = qcom_pcie_get_resources_2_3_2,
1179         .init = qcom_pcie_init_2_3_2,
1180         .post_init = qcom_pcie_post_init_2_3_2,
1181         .deinit = qcom_pcie_deinit_2_3_2,
1182         .post_deinit = qcom_pcie_post_deinit_2_3_2,
1183         .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1184 };
1185
1186 /* Qcom IP rev.: 2.4.0  Synopsys IP rev.: 4.20a */
1187 static const struct qcom_pcie_ops ops_2_4_0 = {
1188         .get_resources = qcom_pcie_get_resources_2_4_0,
1189         .init = qcom_pcie_init_2_4_0,
1190         .deinit = qcom_pcie_deinit_2_4_0,
1191         .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1192 };
1193
1194 /* Qcom IP rev.: 2.3.3  Synopsys IP rev.: 4.30a */
1195 static const struct qcom_pcie_ops ops_2_3_3 = {
1196         .get_resources = qcom_pcie_get_resources_2_3_3,
1197         .init = qcom_pcie_init_2_3_3,
1198         .deinit = qcom_pcie_deinit_2_3_3,
1199         .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1200 };
1201
1202 static const struct dw_pcie_ops dw_pcie_ops = {
1203         .link_up = qcom_pcie_link_up,
1204 };
1205
1206 static int qcom_pcie_probe(struct platform_device *pdev)
1207 {
1208         struct device *dev = &pdev->dev;
1209         struct resource *res;
1210         struct pcie_port *pp;
1211         struct dw_pcie *pci;
1212         struct qcom_pcie *pcie;
1213         int ret;
1214
1215         pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1216         if (!pcie)
1217                 return -ENOMEM;
1218
1219         pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1220         if (!pci)
1221                 return -ENOMEM;
1222
1223         pci->dev = dev;
1224         pci->ops = &dw_pcie_ops;
1225         pp = &pci->pp;
1226
1227         pcie->pci = pci;
1228
1229         pcie->ops = of_device_get_match_data(dev);
1230
1231         pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
1232         if (IS_ERR(pcie->reset))
1233                 return PTR_ERR(pcie->reset);
1234
1235         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
1236         pcie->parf = devm_ioremap_resource(dev, res);
1237         if (IS_ERR(pcie->parf))
1238                 return PTR_ERR(pcie->parf);
1239
1240         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1241         pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
1242         if (IS_ERR(pci->dbi_base))
1243                 return PTR_ERR(pci->dbi_base);
1244
1245         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
1246         pcie->elbi = devm_ioremap_resource(dev, res);
1247         if (IS_ERR(pcie->elbi))
1248                 return PTR_ERR(pcie->elbi);
1249
1250         pcie->phy = devm_phy_optional_get(dev, "pciephy");
1251         if (IS_ERR(pcie->phy))
1252                 return PTR_ERR(pcie->phy);
1253
1254         ret = pcie->ops->get_resources(pcie);
1255         if (ret)
1256                 return ret;
1257
1258         pp->root_bus_nr = -1;
1259         pp->ops = &qcom_pcie_dw_ops;
1260
1261         if (IS_ENABLED(CONFIG_PCI_MSI)) {
1262                 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
1263                 if (pp->msi_irq < 0)
1264                         return pp->msi_irq;
1265
1266                 ret = devm_request_irq(dev, pp->msi_irq,
1267                                        qcom_pcie_msi_irq_handler,
1268                                        IRQF_SHARED | IRQF_NO_THREAD,
1269                                        "qcom-pcie-msi", pp);
1270                 if (ret) {
1271                         dev_err(dev, "cannot request msi irq\n");
1272                         return ret;
1273                 }
1274         }
1275
1276         ret = phy_init(pcie->phy);
1277         if (ret)
1278                 return ret;
1279
1280         platform_set_drvdata(pdev, pcie);
1281
1282         ret = dw_pcie_host_init(pp);
1283         if (ret) {
1284                 dev_err(dev, "cannot initialize host\n");
1285                 return ret;
1286         }
1287
1288         return 0;
1289 }
1290
1291 static const struct of_device_id qcom_pcie_match[] = {
1292         { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
1293         { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
1294         { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
1295         { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
1296         { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
1297         { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
1298         { }
1299 };
1300
1301 static struct platform_driver qcom_pcie_driver = {
1302         .probe = qcom_pcie_probe,
1303         .driver = {
1304                 .name = "qcom-pcie",
1305                 .suppress_bind_attrs = true,
1306                 .of_match_table = qcom_pcie_match,
1307         },
1308 };
1309 builtin_platform_driver(qcom_pcie_driver);