Linux 4.16.11
[linux/fpc-iii.git] / drivers / pci / dwc / pcie-spear13xx.c
blobecb58f7b7566666ae5ee01736c0c3e2b0f3f43b2
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
5 * SPEAr13xx PCIe Glue Layer Source Code
7 * Copyright (C) 2010-2014 ST Microelectronics
8 * Pratyush Anand <pratyush.anand@gmail.com>
9 * Mohit Kumar <mohit.kumar.dhaka@gmail.com>
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/of.h>
17 #include <linux/pci.h>
18 #include <linux/phy/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/resource.h>
22 #include "pcie-designware.h"
24 struct spear13xx_pcie {
25 struct dw_pcie *pci;
26 void __iomem *app_base;
27 struct phy *phy;
28 struct clk *clk;
29 bool is_gen1;
32 struct pcie_app_reg {
33 u32 app_ctrl_0; /* cr0 */
34 u32 app_ctrl_1; /* cr1 */
35 u32 app_status_0; /* cr2 */
36 u32 app_status_1; /* cr3 */
37 u32 msg_status; /* cr4 */
38 u32 msg_payload; /* cr5 */
39 u32 int_sts; /* cr6 */
40 u32 int_clr; /* cr7 */
41 u32 int_mask; /* cr8 */
42 u32 mst_bmisc; /* cr9 */
43 u32 phy_ctrl; /* cr10 */
44 u32 phy_status; /* cr11 */
45 u32 cxpl_debug_info_0; /* cr12 */
46 u32 cxpl_debug_info_1; /* cr13 */
47 u32 ven_msg_ctrl_0; /* cr14 */
48 u32 ven_msg_ctrl_1; /* cr15 */
49 u32 ven_msg_data_0; /* cr16 */
50 u32 ven_msg_data_1; /* cr17 */
51 u32 ven_msi_0; /* cr18 */
52 u32 ven_msi_1; /* cr19 */
53 u32 mst_rmisc; /* cr20 */
56 /* CR0 ID */
57 #define APP_LTSSM_ENABLE_ID 3
58 #define DEVICE_TYPE_RC (4 << 25)
59 #define MISCTRL_EN_ID 30
60 #define REG_TRANSLATION_ENABLE 31
62 /* CR3 ID */
63 #define XMLH_LINK_UP (1 << 6)
65 /* CR6 */
66 #define MSI_CTRL_INT (1 << 26)
68 #define EXP_CAP_ID_OFFSET 0x70
70 #define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev)
72 static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
74 struct dw_pcie *pci = spear13xx_pcie->pci;
75 struct pcie_port *pp = &pci->pp;
76 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
77 u32 val;
78 u32 exp_cap_off = EXP_CAP_ID_OFFSET;
80 if (dw_pcie_link_up(pci)) {
81 dev_err(pci->dev, "link already up\n");
82 return 0;
85 dw_pcie_setup_rc(pp);
88 * this controller support only 128 bytes read size, however its
89 * default value in capability register is 512 bytes. So force
90 * it to 128 here.
92 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
93 val &= ~PCI_EXP_DEVCTL_READRQ;
94 dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
96 dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
97 dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
100 * if is_gen1 is set then handle it, so that some buggy card
101 * also works
103 if (spear13xx_pcie->is_gen1) {
104 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
105 4, &val);
106 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
107 val &= ~((u32)PCI_EXP_LNKCAP_SLS);
108 val |= PCI_EXP_LNKCAP_SLS_2_5GB;
109 dw_pcie_write(pci->dbi_base + exp_cap_off +
110 PCI_EXP_LNKCAP, 4, val);
113 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
114 2, &val);
115 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
116 val &= ~((u32)PCI_EXP_LNKCAP_SLS);
117 val |= PCI_EXP_LNKCAP_SLS_2_5GB;
118 dw_pcie_write(pci->dbi_base + exp_cap_off +
119 PCI_EXP_LNKCTL2, 2, val);
123 /* enable ltssm */
124 writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
125 | (1 << APP_LTSSM_ENABLE_ID)
126 | ((u32)1 << REG_TRANSLATION_ENABLE),
127 &app_reg->app_ctrl_0);
129 return dw_pcie_wait_for_link(pci);
132 static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
134 struct spear13xx_pcie *spear13xx_pcie = arg;
135 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
136 struct dw_pcie *pci = spear13xx_pcie->pci;
137 struct pcie_port *pp = &pci->pp;
138 unsigned int status;
140 status = readl(&app_reg->int_sts);
142 if (status & MSI_CTRL_INT) {
143 BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
144 dw_handle_msi_irq(pp);
147 writel(status, &app_reg->int_clr);
149 return IRQ_HANDLED;
152 static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie)
154 struct dw_pcie *pci = spear13xx_pcie->pci;
155 struct pcie_port *pp = &pci->pp;
156 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
158 /* Enable MSI interrupt */
159 if (IS_ENABLED(CONFIG_PCI_MSI)) {
160 dw_pcie_msi_init(pp);
161 writel(readl(&app_reg->int_mask) |
162 MSI_CTRL_INT, &app_reg->int_mask);
166 static int spear13xx_pcie_link_up(struct dw_pcie *pci)
168 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
169 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
171 if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
172 return 1;
174 return 0;
177 static int spear13xx_pcie_host_init(struct pcie_port *pp)
179 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
180 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
182 spear13xx_pcie_establish_link(spear13xx_pcie);
183 spear13xx_pcie_enable_interrupts(spear13xx_pcie);
185 return 0;
188 static const struct dw_pcie_host_ops spear13xx_pcie_host_ops = {
189 .host_init = spear13xx_pcie_host_init,
192 static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
193 struct platform_device *pdev)
195 struct dw_pcie *pci = spear13xx_pcie->pci;
196 struct pcie_port *pp = &pci->pp;
197 struct device *dev = &pdev->dev;
198 int ret;
200 pp->irq = platform_get_irq(pdev, 0);
201 if (pp->irq < 0) {
202 dev_err(dev, "failed to get irq\n");
203 return pp->irq;
205 ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
206 IRQF_SHARED | IRQF_NO_THREAD,
207 "spear1340-pcie", spear13xx_pcie);
208 if (ret) {
209 dev_err(dev, "failed to request irq %d\n", pp->irq);
210 return ret;
213 pp->root_bus_nr = -1;
214 pp->ops = &spear13xx_pcie_host_ops;
216 ret = dw_pcie_host_init(pp);
217 if (ret) {
218 dev_err(dev, "failed to initialize host\n");
219 return ret;
222 return 0;
225 static const struct dw_pcie_ops dw_pcie_ops = {
226 .link_up = spear13xx_pcie_link_up,
229 static int spear13xx_pcie_probe(struct platform_device *pdev)
231 struct device *dev = &pdev->dev;
232 struct dw_pcie *pci;
233 struct spear13xx_pcie *spear13xx_pcie;
234 struct device_node *np = dev->of_node;
235 struct resource *dbi_base;
236 int ret;
238 spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
239 if (!spear13xx_pcie)
240 return -ENOMEM;
242 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
243 if (!pci)
244 return -ENOMEM;
246 pci->dev = dev;
247 pci->ops = &dw_pcie_ops;
249 spear13xx_pcie->pci = pci;
251 spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
252 if (IS_ERR(spear13xx_pcie->phy)) {
253 ret = PTR_ERR(spear13xx_pcie->phy);
254 if (ret == -EPROBE_DEFER)
255 dev_info(dev, "probe deferred\n");
256 else
257 dev_err(dev, "couldn't get pcie-phy\n");
258 return ret;
261 phy_init(spear13xx_pcie->phy);
263 spear13xx_pcie->clk = devm_clk_get(dev, NULL);
264 if (IS_ERR(spear13xx_pcie->clk)) {
265 dev_err(dev, "couldn't get clk for pcie\n");
266 return PTR_ERR(spear13xx_pcie->clk);
268 ret = clk_prepare_enable(spear13xx_pcie->clk);
269 if (ret) {
270 dev_err(dev, "couldn't enable clk for pcie\n");
271 return ret;
274 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
275 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
276 if (IS_ERR(pci->dbi_base)) {
277 dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
278 ret = PTR_ERR(pci->dbi_base);
279 goto fail_clk;
281 spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
283 if (of_property_read_bool(np, "st,pcie-is-gen1"))
284 spear13xx_pcie->is_gen1 = true;
286 platform_set_drvdata(pdev, spear13xx_pcie);
288 ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
289 if (ret < 0)
290 goto fail_clk;
292 return 0;
294 fail_clk:
295 clk_disable_unprepare(spear13xx_pcie->clk);
297 return ret;
300 static const struct of_device_id spear13xx_pcie_of_match[] = {
301 { .compatible = "st,spear1340-pcie", },
305 static struct platform_driver spear13xx_pcie_driver = {
306 .probe = spear13xx_pcie_probe,
307 .driver = {
308 .name = "spear-pcie",
309 .of_match_table = of_match_ptr(spear13xx_pcie_of_match),
310 .suppress_bind_attrs = true,
314 builtin_platform_driver(spear13xx_pcie_driver);